In Documentation/devicetree/bindings/riscv/cpus.yaml I find for riscv,isa:
enum:
- rv64imac
- rv64imafdc
This implies that 'rv64imafc' or 'rv64imafdqc' would be illegal values
while these combinations of extensions would be compliant with "The
RISC-V Instruction Set Manual".
To me it does not make much sense to try to enumerate all permissible
permutations of RISC-V extensions.
Shouldn't this enum be removed and replaced by examples?
Best regards
Heinrich
On Tue, 06 Apr 2021 12:05:34 PDT (-0700), [email protected] wrote:
> In Documentation/devicetree/bindings/riscv/cpus.yaml I find for riscv,isa:
>
> enum:
> - rv64imac
> - rv64imafdc
>
> This implies that 'rv64imafc' or 'rv64imafdqc' would be illegal values
> while these combinations of extensions would be compliant with "The
> RISC-V Instruction Set Manual".
>
> To me it does not make much sense to try to enumerate all permissible
> permutations of RISC-V extensions.
>
> Shouldn't this enum be removed and replaced by examples?
I'm generally OK with that, but I'm not sure how to do it: won't we fail
the scheme checks if we don't have something defined for "riscv,isa"?