Hi,
These patches add the missing OCP2SCP3 module and fixup the SATA hwmod
for DRA7 SoC. Both patches are tested on 3.16-rc1.
SATA should have worked on DRA7-evm with just these 2 patches on top of
3.16-rc1,but it didn't :(. So something else is missing and needs to be
investigated. SATA worked fine on omap5-uevm though so the problem is
DRA7 specific.
The patches are required for 3.16 in any case.
cheers,
-roger
Roger Quadros (2):
ARM: DRA7: hwmod: Add OCP2SCP3 module
ARM: DRA7: hwmod: Fixup SATA hwmod
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
1 file changed, 26 insertions(+), 5 deletions(-)
--
1.8.3.2
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros <[email protected]>
Tested-by: Roger Quadros <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398..cedef6b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
};
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp2scp3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+ .name = "ocp2scp3",
+ .class = &dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
/*
* 'qspi' class
*
@@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per1__mmc4,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
+ &dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
--
1.8.3.2
Get rid of optional clock as that is now managed by the
AHCI platform driver.
Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: Roger Quadros <[email protected]>
Tested-by: Roger Quadros <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index cedef6b..bc42eab 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1292,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
};
/* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
- { .role = "ref_clk", .clk = "sata_ref_clk" },
-};
static struct omap_hwmod dra7xx_sata_hwmod = {
.name = "sata",
@@ -1302,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.clkdm_name = "l3init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "func_48m_fclk",
+ .mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1309,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = sata_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
};
/*
--
1.8.3.2
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 20b4398..cedef6b 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
> },
> };
>
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_ocp2scp3_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
is it not possible to move this down in the file where all interface
structs are defined?
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> + .name = "ocp2scp3",
> + .class = &dra7xx_ocp2scp_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_HWCTRL,
> + },
> + },
> +};
> +
> /*
> * 'qspi' class
> *
> @@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_per1__mmc4,
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> + &dra7xx_l4_cfg__ocp2scp3,
> &dra7xx_l3_main_1__qspi,
> &dra7xx_l4_cfg__sata,
> &dra7xx_l4_cfg__smartreflex_core,
>
On 06/18/2014 03:34 PM, Rajendra Nayak wrote:
> On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
>> This module is needed for the SATA and PCIe PHYs.
>>
>> Signed-off-by: Roger Quadros <[email protected]>
>> Tested-by: Roger Quadros <[email protected]>
>> ---
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +++++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 20b4398..cedef6b 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>> },
>> };
>>
>> +/* ocp2scp3 */
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
>> +
>> +/* l4_cfg -> ocp2scp3 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_ocp2scp3_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>
> is it not possible to move this down in the file where all interface
> structs are defined?
yes, i'll send a v2 with this fixed as well as add .main_clk to the hwmod
like in ocp2scp1.
cheers,
-roger
>
>> +
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> + .name = "ocp2scp3",
>> + .class = &dra7xx_ocp2scp_hwmod_class,
>> + .clkdm_name = "l3init_clkdm",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
>> + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
>> + .modulemode = MODULEMODE_HWCTRL,
>> + },
>> + },
>> +};
>> +
>> /*
>> * 'qspi' class
>> *
>> @@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>> &dra7xx_l4_per1__mmc4,
>> &dra7xx_l4_cfg__mpu,
>> &dra7xx_l4_cfg__ocp2scp1,
>> + &dra7xx_l4_cfg__ocp2scp3,
>> &dra7xx_l3_main_1__qspi,
>> &dra7xx_l4_cfg__sata,
>> &dra7xx_l4_cfg__smartreflex_core,
>>
>
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros <[email protected]>
Tested-by: Roger Quadros <[email protected]>
---
v2:
- added .main_clk to hwmod.
- moved interface structure to the right place.
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398..c9daee4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
};
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+ .name = "ocp2scp3",
+ .class = &dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
/*
* 'qspi' class
*
@@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp2scp3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b300000,
@@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per1__mmc4,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
+ &dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
--
1.8.3.2
On Wed, 18 Jun 2014, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
Is this one a fix? It looks to me like a new IP block addition.
- Paul
On Thursday 19 June 2014 11:18 AM, Paul Walmsley wrote:
> On Wed, 18 Jun 2014, Roger Quadros wrote:
>
>> This module is needed for the SATA and PCIe PHYs.
>>
>> Signed-off-by: Roger Quadros <[email protected]>
>> Tested-by: Roger Quadros <[email protected]>
>
> Is this one a fix? It looks to me like a new IP block addition.
This is not a regression fix, but this is the only thing preventing
users from using SATA on DRA7x - the DT fragments are already there.
Since its still early -rc cycle, I am hoping enabling support for new
devices can still go in.
Thanks,
Sekhar
Hi Roger
On Wed, 18 Jun 2014, Roger Quadros wrote:
> These patches add the missing OCP2SCP3 module and fixup the SATA hwmod
> for DRA7 SoC. Both patches are tested on 3.16-rc1.
Could you please post a quick serial capture of a boot log for these
patches, as Felipe has done for other patches?
thanks,
- Paul
On Monday 23 June 2014 10:27 AM, Paul Walmsley wrote:
> Hi Roger
>
> On Wed, 18 Jun 2014, Roger Quadros wrote:
>
>> These patches add the missing OCP2SCP3 module and fixup the SATA hwmod
>> for DRA7 SoC. Both patches are tested on 3.16-rc1.
>
> Could you please post a quick serial capture of a boot log for these
> patches, as Felipe has done for other patches?
Roger is OOO so posting the logs on his behalf.
$ git log -3
3e0ca738 4 minutes ago (HEAD) ARM: DRA7: hwmod: Add OCP2SCP3 module
9961b81 4 minutes ago ARM: DRA7: hwmod: Fixup SATA hwmod
7171511 7 days ago (v3.16-rc1, linus-git/master) Linux 3.16-rc1
Attached is the minicom capture.
Thanks,
Sekhar
On Mon, 23 Jun 2014, Sekhar Nori wrote:
> On Monday 23 June 2014 10:27 AM, Paul Walmsley wrote:
> > Hi Roger
> >
> > On Wed, 18 Jun 2014, Roger Quadros wrote:
> >
> >> These patches add the missing OCP2SCP3 module and fixup the SATA hwmod
> >> for DRA7 SoC. Both patches are tested on 3.16-rc1.
> >
> > Could you please post a quick serial capture of a boot log for these
> > patches, as Felipe has done for other patches?
>
> Roger is OOO so posting the logs on his behalf.
>
> $ git log -3
> 3e0ca738 4 minutes ago (HEAD) ARM: DRA7: hwmod: Add OCP2SCP3 module
> 9961b81 4 minutes ago ARM: DRA7: hwmod: Fixup SATA hwmod
> 7171511 7 days ago (v3.16-rc1, linus-git/master) Linux 3.16-rc1
>
> Attached is the minicom capture.
Thanks, so can I add your Tested-by: ?
- Paul
On Monday 23 June 2014 10:04 PM, Paul Walmsley wrote:
> On Mon, 23 Jun 2014, Sekhar Nori wrote:
>
>> On Monday 23 June 2014 10:27 AM, Paul Walmsley wrote:
>>> Hi Roger
>>>
>>> On Wed, 18 Jun 2014, Roger Quadros wrote:
>>>
>>>> These patches add the missing OCP2SCP3 module and fixup the SATA hwmod
>>>> for DRA7 SoC. Both patches are tested on 3.16-rc1.
>>>
>>> Could you please post a quick serial capture of a boot log for these
>>> patches, as Felipe has done for other patches?
>>
>> Roger is OOO so posting the logs on his behalf.
>>
>> $ git log -3
>> 3e0ca738 4 minutes ago (HEAD) ARM: DRA7: hwmod: Add OCP2SCP3 module
>> 9961b81 4 minutes ago ARM: DRA7: hwmod: Fixup SATA hwmod
>> 7171511 7 days ago (v3.16-rc1, linus-git/master) Linux 3.16-rc1
>>
>> Attached is the minicom capture.
>
> Thanks, so can I add your Tested-by: ?
Sure Paul.
Tested-by: Sekhar Nori <[email protected]>
Thanks,
Sekhar
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
I used this patch for testing PCIe.
Tested-by: Kishon Vijay Abraham I <[email protected]>
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 20b4398..cedef6b 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
> },
> };
>
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_ocp2scp3_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> + .name = "ocp2scp3",
> + .class = &dra7xx_ocp2scp_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_HWCTRL,
> + },
> + },
> +};
> +
> /*
> * 'qspi' class
> *
> @@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_per1__mmc4,
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> + &dra7xx_l4_cfg__ocp2scp3,
> &dra7xx_l3_main_1__qspi,
> &dra7xx_l4_cfg__sata,
> &dra7xx_l4_cfg__smartreflex_core,
>
Kishon,
On 06/25/2014 08:46 PM, Kishon Vijay Abraham I wrote:
>
> On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
>> This module is needed for the SATA and PCIe PHYs.
>>
>> Signed-off-by: Roger Quadros <[email protected]>
>> Tested-by: Roger Quadros <[email protected]>
>
> I used this patch for testing PCIe.
> Tested-by: Kishon Vijay Abraham I <[email protected]>
There is a v2 of this patch in reply to the original patch. Could you please give your Tested-by tag on that one?
Thanks.
cheers,
-roger
>> ---
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +++++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 20b4398..cedef6b 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>> },
>> };
>>
>> +/* ocp2scp3 */
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
>> +
>> +/* l4_cfg -> ocp2scp3 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_ocp2scp3_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> + .name = "ocp2scp3",
>> + .class = &dra7xx_ocp2scp_hwmod_class,
>> + .clkdm_name = "l3init_clkdm",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
>> + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
>> + .modulemode = MODULEMODE_HWCTRL,
>> + },
>> + },
>> +};
>> +
>> /*
>> * 'qspi' class
>> *
>> @@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>> &dra7xx_l4_per1__mmc4,
>> &dra7xx_l4_cfg__mpu,
>> &dra7xx_l4_cfg__ocp2scp1,
>> + &dra7xx_l4_cfg__ocp2scp3,
>> &dra7xx_l3_main_1__qspi,
>> &dra7xx_l4_cfg__sata,
>> &dra7xx_l4_cfg__smartreflex_core,
>>
Rajendra,
On 06/18/2014 10:50 PM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
could you please Ack this one? Thanks.
cheers,
-roger
> ---
> v2:
> - added .main_clk to hwmod.
> - moved interface structure to the right place.
>
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 20b4398..c9daee4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
> },
> };
>
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> + .name = "ocp2scp3",
> + .class = &dra7xx_ocp2scp_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_HWCTRL,
> + },
> + },
> +};
> +
> /*
> * 'qspi' class
> *
> @@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_ocp2scp3_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
> {
> .pa_start = 0x4b300000,
> @@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_per1__mmc4,
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> + &dra7xx_l4_cfg__ocp2scp3,
> &dra7xx_l3_main_1__qspi,
> &dra7xx_l4_cfg__sata,
> &dra7xx_l4_cfg__smartreflex_core,
>
Rajendra,
On 06/18/2014 03:16 PM, Roger Quadros wrote:
> Get rid of optional clock as that is now managed by the
> AHCI platform driver.
>
> Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
> is passed as the second memory resource in the device tree.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
Need your Ack for this one as well. Thanks.
cheers,
-roger
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index cedef6b..bc42eab 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1292,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
> };
>
> /* sata */
> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
> - { .role = "ref_clk", .clk = "sata_ref_clk" },
> -};
>
> static struct omap_hwmod dra7xx_sata_hwmod = {
> .name = "sata",
> @@ -1302,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
> .clkdm_name = "l3init_clkdm",
> .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> .main_clk = "func_48m_fclk",
> + .mpu_rt_idx = 1,
> .prcm = {
> .omap4 = {
> .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> @@ -1309,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
> .modulemode = MODULEMODE_SWCTRL,
> },
> },
> - .opt_clks = sata_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
> };
>
> /*
>
On Thursday 19 June 2014 01:20 AM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
Reviewed-by: Rajendra Nayak <[email protected]>
> ---
> v2:
> - added .main_clk to hwmod.
> - moved interface structure to the right place.
>
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 20b4398..c9daee4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
> },
> };
>
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> + .name = "ocp2scp3",
> + .class = &dra7xx_ocp2scp_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_HWCTRL,
> + },
> + },
> +};
> +
> /*
> * 'qspi' class
> *
> @@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_ocp2scp3_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
> {
> .pa_start = 0x4b300000,
> @@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_per1__mmc4,
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> + &dra7xx_l4_cfg__ocp2scp3,
> &dra7xx_l3_main_1__qspi,
> &dra7xx_l4_cfg__sata,
> &dra7xx_l4_cfg__smartreflex_core,
>
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
> Get rid of optional clock as that is now managed by the
> AHCI platform driver.
The optional clock info in hwmod is actually unused for a lot of
other modules too.
http://www.spinics.net/lists/arm-kernel/msg333025.html
>
> Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
> is passed as the second memory resource in the device tree.
>
> Signed-off-by: Roger Quadros <[email protected]>
> Tested-by: Roger Quadros <[email protected]>
Reviewed-by: Rajendra Nayak <[email protected]>
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index cedef6b..bc42eab 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1292,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
> };
>
> /* sata */
> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
> - { .role = "ref_clk", .clk = "sata_ref_clk" },
> -};
>
> static struct omap_hwmod dra7xx_sata_hwmod = {
> .name = "sata",
> @@ -1302,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
> .clkdm_name = "l3init_clkdm",
> .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> .main_clk = "func_48m_fclk",
> + .mpu_rt_idx = 1,
> .prcm = {
> .omap4 = {
> .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> @@ -1309,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
> .modulemode = MODULEMODE_SWCTRL,
> },
> },
> - .opt_clks = sata_opt_clks,
> - .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
> };
>
> /*
>