In order to be able to gather more information about the supported ISA
extensions from userspace using the hwprobe syscall, add more ISA extensions
report. This series adds the following ISA extensions support:
- Zfh[min]
- Zvfh[min]
- Zihintntl
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknh[ab]
- Zvksed
- Zvksh
- Zvkn
- Zvknc
- Zvkng
- Zvks
- Zvksc
- Zvksg
- Zvkt
Clément Léger (13):
riscv: fatorize hwprobe ISA extension reporting
riscv: add ISA extension probing for Zv* extensions
riscv: hwprobe: export Zv* ISA extensions
dt-bindings: riscv: add Zv* ratified crypto ISA extensions description
riscv: add ISA extension probing for Zfh/Zfhmin
riscv: hwprobe: export Zfh/Zfhmin ISA extensions
dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description
riscv: add ISA extension probing for Zihintntl
riscv: hwprobe: export Zhintntl ISA extension
dt-bindings: riscv: add Zihintntl ISA extension description
riscv: add ISA extension probing for Zvfh[min]
riscv: hwprobe: export Zvfh[min] ISA extensions
dt-bindings: riscv: add Zvfh[min] ISA extension description
.../devicetree/bindings/riscv/extensions.yaml | 127 ++++++++++++++++++
Documentation/riscv/hwprobe.rst | 65 +++++++++
arch/riscv/include/asm/hwcap.h | 21 +++
arch/riscv/include/uapi/asm/hwprobe.h | 21 +++
arch/riscv/kernel/cpufeature.c | 21 +++
arch/riscv/kernel/sys_riscv.c | 53 ++++++--
6 files changed, 294 insertions(+), 14 deletions(-)
--
2.42.0
Add description of Zfh and Zfhmin ISA extensions[1] which can now be
reported through hwprobe for userspace usage.
[1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view
Signed-off-by: Clément Léger <[email protected]>
---
.../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 4002c65145c9..4c923800d751 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -190,6 +190,19 @@ properties:
instructions as ratified at commit 6d33919 ("Merge pull request #158
from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zfh
+ description:
+ The standard Zfh extension for 16-bit half-precision binary
+ floating-point instructions, as ratified in commit 64074bc ("Update
+ version numbers for Zfh/Zfinx") of riscv-isa-manual.
+
+ - const: zfhmin
+ description:
+ The standard Zfhmin extension which provides minimal support for
+ 16-bit half-precision binary floating-point instructions, as ratified
+ in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
+ riscv-isa-manual.
+
- const: zicbom
description:
The standard Zicbom extension for base cache management operations as
--
2.42.0
Add probing for Zvfh[min] ISA extension[1] which were ratified in
june 2023 around commit e2ccd0548d6c ("Remove draft warnings from
Zvfh[min]") in riscv-v-spec[2].
[1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view
[2] https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c
Signed-off-by: Clément Léger <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpufeature.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 1f09b8b3da2a..ea141cfb8f9c 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -77,6 +77,8 @@
#define RISCV_ISA_EXT_ZFH 59
#define RISCV_ISA_EXT_ZFHMIN 60
#define RISCV_ISA_EXT_ZIHINTNTL 61
+#define RISCV_ISA_EXT_ZVFH 62
+#define RISCV_ISA_EXT_ZVFHMIN 63
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 136e90263ba2..f17b9aca5fba 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -179,6 +179,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
__RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+ __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
+ __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
__RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
--
2.42.0
Factorize ISA extension reporting by using a macro rather than
copy/pasting extension names. This will allow adding new extensions more
easily.
Signed-off-by: Clément Léger <[email protected]>
---
arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 473159b5f303..5ce593ce07a4 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
for_each_cpu(cpu, cpus) {
struct riscv_isainfo *isainfo = &hart_isa[cpu];
- if (riscv_isa_extension_available(isainfo->isa, ZBA))
- pair->value |= RISCV_HWPROBE_EXT_ZBA;
- else
- missing |= RISCV_HWPROBE_EXT_ZBA;
-
- if (riscv_isa_extension_available(isainfo->isa, ZBB))
- pair->value |= RISCV_HWPROBE_EXT_ZBB;
- else
- missing |= RISCV_HWPROBE_EXT_ZBB;
-
- if (riscv_isa_extension_available(isainfo->isa, ZBS))
- pair->value |= RISCV_HWPROBE_EXT_ZBS;
- else
- missing |= RISCV_HWPROBE_EXT_ZBS;
+#define CHECK_ISA_EXT(__ext) \
+ do { \
+ if (riscv_isa_extension_available(isainfo->isa, __ext)) \
+ pair->value |= RISCV_HWPROBE_EXT_##__ext; \
+ else \
+ missing |= RISCV_HWPROBE_EXT_##__ext; \
+ } while (false) \
+
+ CHECK_ISA_EXT(ZBA);
+ CHECK_ISA_EXT(ZBB);
+ CHECK_ISA_EXT(ZBS);
+#undef CHECK_ISA_EXT
}
/* Now turn off reporting features if any CPU is missing it. */
--
2.42.0
Export Zihintntl extension[1] through hwprobe.
[1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
Signed-off-by: Clément Léger <[email protected]>
---
Documentation/riscv/hwprobe.rst | 3 +++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_riscv.c | 1 +
3 files changed, 5 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 06f49a095f19..a577b1d72dff 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -131,6 +131,9 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
supported as defined in the RISC-V ISA manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
+ is supported as defined in the RISC-V ISA manual.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index c9016abf099e..3c4aa5d01f93 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -47,6 +47,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZVKT (1 << 21)
#define RISCV_HWPROBE_EXT_ZFH (1 << 22)
#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23)
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 24)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index da916981934b..ca17829f3e16 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -156,6 +156,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZBA);
CHECK_ISA_EXT(ZBB);
CHECK_ISA_EXT(ZBS);
+ CHECK_ISA_EXT(ZIHINTNTL);
if (has_vector()) {
CHECK_ISA_EXT(ZVBB);
--
2.42.0
Add probing of some Zv* ISA extensions that are mentioned in "RISC-V
Cryptography Extensions Volume II" [1]. These ISA extensions are the
following:
- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.
[1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
Signed-off-by: Clément Léger <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++
arch/riscv/kernel/cpufeature.c | 16 ++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b7b58258f6c7..4e46981ac6c8 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -58,6 +58,22 @@
#define RISCV_ISA_EXT_ZICSR 40
#define RISCV_ISA_EXT_ZIFENCEI 41
#define RISCV_ISA_EXT_ZIHPM 42
+#define RISCV_ISA_EXT_ZVBB 43
+#define RISCV_ISA_EXT_ZVBC 44
+#define RISCV_ISA_EXT_ZVKB 45
+#define RISCV_ISA_EXT_ZVKG 46
+#define RISCV_ISA_EXT_ZVKN 47
+#define RISCV_ISA_EXT_ZVKNC 48
+#define RISCV_ISA_EXT_ZVKNED 49
+#define RISCV_ISA_EXT_ZVKNG 50
+#define RISCV_ISA_EXT_ZVKNHA 51
+#define RISCV_ISA_EXT_ZVKNHB 52
+#define RISCV_ISA_EXT_ZVKS 53
+#define RISCV_ISA_EXT_ZVKSC 54
+#define RISCV_ISA_EXT_ZVKSED 55
+#define RISCV_ISA_EXT_ZVKSH 56
+#define RISCV_ISA_EXT_ZVKSG 57
+#define RISCV_ISA_EXT_ZVKT 58
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1cfbba65d11a..859d647f3ced 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -174,6 +174,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
+ __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
+ __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+ __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
+ __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
+ __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
+ __RISCV_ISA_EXT_DATA(zvknc, RISCV_ISA_EXT_ZVKNC),
+ __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
+ __RISCV_ISA_EXT_DATA(zvkng, RISCV_ISA_EXT_ZVKNG),
+ __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
+ __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
+ __RISCV_ISA_EXT_DATA(zvks, RISCV_ISA_EXT_ZVKS),
+ __RISCV_ISA_EXT_DATA(zvksc, RISCV_ISA_EXT_ZVKSC),
+ __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
+ __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
+ __RISCV_ISA_EXT_DATA(zvksg, RISCV_ISA_EXT_ZVKSG),
+ __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
--
2.42.0
Add probing for Zvfh/Zfhmin ISA extensions[1].
[1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view
Signed-off-by: Clément Léger <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpufeature.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4e46981ac6c8..35f00401afc8 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -74,6 +74,8 @@
#define RISCV_ISA_EXT_ZVKSH 56
#define RISCV_ISA_EXT_ZVKSG 57
#define RISCV_ISA_EXT_ZVKT 58
+#define RISCV_ISA_EXT_ZFH 59
+#define RISCV_ISA_EXT_ZFHMIN 60
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 859d647f3ced..9ee7814641a4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -171,6 +171,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+ __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
+ __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
--
2.42.0
Export Zv* ISA extensions that were added in "RISC-V Cryptography
Extensions Volume II" specification[1] through hwprobe. This adds
support for the following instructions:
- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.
[1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
Signed-off-by: Clément Léger <[email protected]>
---
Documentation/riscv/hwprobe.rst | 48 +++++++++++++++++++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 16 +++++++++
arch/riscv/kernel/sys_riscv.c | 19 +++++++++++
3 files changed, 83 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index a52996b22f75..edfed33669ea 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -77,6 +77,54 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
in version 1.0 of the Bit-Manipulation ISA extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKN`: The Zvkn extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNC`: The Zvknc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNG`: The Zvkng extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKS`: The Zvks extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSC`: The Zvksc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSG`: The Zvksg extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 006bfb48343d..d868eb431cd6 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -29,6 +29,22 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 6)
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 7)
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 8)
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 9)
+#define RISCV_HWPROBE_EXT_ZVKN (1 << 10)
+#define RISCV_HWPROBE_EXT_ZVKNC (1 << 11)
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 12)
+#define RISCV_HWPROBE_EXT_ZVKNG (1 << 13)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 14)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 15)
+#define RISCV_HWPROBE_EXT_ZVKS (1 << 16)
+#define RISCV_HWPROBE_EXT_ZVKSC (1 << 17)
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 18)
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 19)
+#define RISCV_HWPROBE_EXT_ZVKSG (1 << 20)
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 21)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 5ce593ce07a4..4f5e51c192d5 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -156,6 +156,25 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZBA);
CHECK_ISA_EXT(ZBB);
CHECK_ISA_EXT(ZBS);
+
+ if (has_vector()) {
+ CHECK_ISA_EXT(ZVBB);
+ CHECK_ISA_EXT(ZVBC);
+ CHECK_ISA_EXT(ZVKB);
+ CHECK_ISA_EXT(ZVKG);
+ CHECK_ISA_EXT(ZVKN);
+ CHECK_ISA_EXT(ZVKNC);
+ CHECK_ISA_EXT(ZVKNED);
+ CHECK_ISA_EXT(ZVKNG);
+ CHECK_ISA_EXT(ZVKNHA);
+ CHECK_ISA_EXT(ZVKNHB);
+ CHECK_ISA_EXT(ZVKS);
+ CHECK_ISA_EXT(ZVKSC);
+ CHECK_ISA_EXT(ZVKSED);
+ CHECK_ISA_EXT(ZVKSH);
+ CHECK_ISA_EXT(ZVKSG);
+ CHECK_ISA_EXT(ZVKT);
+ }
#undef CHECK_ISA_EXT
}
--
2.42.0
Export Zfh/Zfhmin ISA extensions[1] through hwprobe only if FPU support
is available.
[1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view
Signed-off-by: Clément Léger <[email protected]>
---
Documentation/riscv/hwprobe.rst | 6 ++++++
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_riscv.c | 5 +++++
3 files changed, 13 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index edfed33669ea..06f49a095f19 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -125,6 +125,12 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
+ as defined in the RISC-V ISA manual.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
+ supported as defined in the RISC-V ISA manual.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index d868eb431cd6..c9016abf099e 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -45,6 +45,8 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZVKSH (1 << 19)
#define RISCV_HWPROBE_EXT_ZVKSG (1 << 20)
#define RISCV_HWPROBE_EXT_ZVKT (1 << 21)
+#define RISCV_HWPROBE_EXT_ZFH (1 << 22)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 4f5e51c192d5..da916981934b 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -175,6 +175,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZVKSG);
CHECK_ISA_EXT(ZVKT);
}
+
+ if (has_fpu()) {
+ CHECK_ISA_EXT(ZFH);
+ CHECK_ISA_EXT(ZFHMIN);
+ }
#undef CHECK_ISA_EXT
}
--
2.42.0
Add probing for Zihintntl ISA extension[1] that was ratified in commit
0dc91f5 ("Zihintntl is ratified") in riscv-isa-manual[2].
[1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
[2] https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d
Signed-off-by: Clément Léger <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 35f00401afc8..1f09b8b3da2a 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -76,6 +76,7 @@
#define RISCV_ISA_EXT_ZVKT 58
#define RISCV_ISA_EXT_ZFH 59
#define RISCV_ISA_EXT_ZFHMIN 60
+#define RISCV_ISA_EXT_ZIHINTNTL 61
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 9ee7814641a4..136e90263ba2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -169,6 +169,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
+ __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
--
2.42.0
Export Zvfh[min] ISA extension[1] through hwprobe.
[1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view
Signed-off-by: Clément Léger <[email protected]>
---
Documentation/riscv/hwprobe.rst | 8 ++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_riscv.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index a577b1d72dff..c2c3588891d1 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -134,6 +134,14 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
is supported as defined in the RISC-V ISA manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
+ defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+ ("Remove draft warnings from Zvfh[min]").
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
+ defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+ ("Remove draft warnings from Zvfh[min]").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 3c4aa5d01f93..ee68eb90d4c7 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -48,6 +48,8 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZFH (1 << 22)
#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23)
#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 24)
+#define RISCV_HWPROBE_EXT_ZVFH (1 << 25)
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 26)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index ca17829f3e16..63e123314524 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -175,6 +175,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZVKSH);
CHECK_ISA_EXT(ZVKSG);
CHECK_ISA_EXT(ZVKT);
+ CHECK_ISA_EXT(ZVFH);
+ CHECK_ISA_EXT(ZVFHMIN);
}
if (has_fpu()) {
--
2.42.0
Add description for Zihintntl ISA extension[1] which can now be reported
through hwprobe for userspace usage.
[1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
Signed-off-by: Clément Léger <[email protected]>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 4c923800d751..70c2b0351357 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -247,6 +247,12 @@ properties:
The standard Zihintpause extension for pause hints, as ratified in
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
+ - const: zihintntl
+ description:
+ The standard Zihintntl extension for non-temporal locality hints, as
+ ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
+ riscv-isa-manual.
+
- const: zihpm
description:
The standard Zihpm extension for hardware performance counters, as
--
2.42.0
Add Zv* vector crypto extensions that were added in "RISC-V Cryptography
Extensions Volume II" specificationi[1]:
- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.
[1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
Signed-off-by: Clément Léger <[email protected]>
---
.../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..4002c65145c9 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -246,5 +246,101 @@ properties:
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.
+ - const: zvbb
+ description:
+ The standard Zvbb extension for vectored basic bit-manipulation
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvbc
+ description:
+ The standard Zvbc extension for vectored carryless multiplication
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkb
+ description:
+ The standard Zvkb extension for vector cryptography bit-manipulation
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkg
+ description:
+ The standard Zvkg extension for vector GCM/GMAC instructions, as
+ ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+ of riscv-crypto.
+
+ - const: zvkn
+ description:
+ The standard Zvkn extension for NIST algorithm suite instructions, as
+ ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+ of riscv-crypto.
+
+ - const: zvknc
+ description:
+ The standard Zvknc extension for NIST algorithm suite with carryless
+ multiply instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkned
+ description:
+ The standard Zvkned extension for Vector AES block cipher
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkng
+ description:
+ The standard Zvkng extension for NIST algorithm suite with GCM
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvknha
+ description: |
+ The standard Zvknha extension for NIST suite: vector SHA-2 secure,
+ hash (SHA-256 only) instructions, as ratified in commit
+ 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvknhb
+ description: |
+ The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
+ hash (SHA-256 and SHA-512) instructions, as ratified in commit
+ 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvks
+ description:
+ The standard Zvks extension for ShangMi algorithm suite
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksc
+ description:
+ The standard Zvksc extension for ShangMi algorithm suite with
+ carryless multiplication instructions, as ratified in commit 56ed795
+ ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksed
+ description: |
+ The standard Zvksed extension for ShangMi suite: SM4 block cipher
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksh
+ description: |
+ The standard Zvksh extension for ShangMi suite: SM3 secure hash
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksg
+ description:
+ The standard Zvksg extension for ShangMi algorithm suite with GCM
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkt
+ description:
+ The standard zvkt extension for vector data-independent execution
+ latency, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
additionalProperties: true
...
--
2.42.0
Add description for Zvfh[min] ISA extension[1] which can now be
reported through hwprobe for userspace usage.
[1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view
Signed-off-by: Clément Léger <[email protected]>
---
.../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 70c2b0351357..ae7db420ab92 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -277,6 +277,18 @@ properties:
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: zvfh
+ description:
+ The standard Zvfh extension for vectored half-precision
+ floating-point instructions, as ratified in commit e2ccd05
+ ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+ - const: zvfhmin
+ description:
+ The standard Zvfhmin extension for vectored minimal half-precision
+ floating-point instructions, as ratified in commit e2ccd05
+ ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
- const: zvkb
description:
The standard Zvkb extension for vector cryptography bit-manipulation
--
2.42.0
correct misspelling of "fatorize" in subject line
rday
On second thought, maybe it would make more sense to squash all logical
commits together (dt-bindings, hwporobe, etc) with all the ISA
extensions in each. Tell me if you think it would be better.
Clément
On 11/10/2023 13:14, Clément Léger wrote:
> In order to be able to gather more information about the supported ISA
> extensions from userspace using the hwprobe syscall, add more ISA extensions
> report. This series adds the following ISA extensions support:
>
> - Zfh[min]
> - Zvfh[min]
> - Zihintntl
> - Zvbb
> - Zvbc
> - Zvkb
> - Zvkg
> - Zvkned
> - Zvknh[ab]
> - Zvksed
> - Zvksh
> - Zvkn
> - Zvknc
> - Zvkng
> - Zvks
> - Zvksc
> - Zvksg
> - Zvkt
>
> Clément Léger (13):
> riscv: fatorize hwprobe ISA extension reporting
> riscv: add ISA extension probing for Zv* extensions
> riscv: hwprobe: export Zv* ISA extensions
> dt-bindings: riscv: add Zv* ratified crypto ISA extensions description
> riscv: add ISA extension probing for Zfh/Zfhmin
> riscv: hwprobe: export Zfh/Zfhmin ISA extensions
> dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description
> riscv: add ISA extension probing for Zihintntl
> riscv: hwprobe: export Zhintntl ISA extension
> dt-bindings: riscv: add Zihintntl ISA extension description
> riscv: add ISA extension probing for Zvfh[min]
> riscv: hwprobe: export Zvfh[min] ISA extensions
> dt-bindings: riscv: add Zvfh[min] ISA extension description
>
> .../devicetree/bindings/riscv/extensions.yaml | 127 ++++++++++++++++++
> Documentation/riscv/hwprobe.rst | 65 +++++++++
> arch/riscv/include/asm/hwcap.h | 21 +++
> arch/riscv/include/uapi/asm/hwprobe.h | 21 +++
> arch/riscv/kernel/cpufeature.c | 21 +++
> arch/riscv/kernel/sys_riscv.c | 53 ++++++--
> 6 files changed, 294 insertions(+), 14 deletions(-)
>
On Thu, Oct 12, 2023 at 09:15:46AM +0200, Cl?ment L?ger wrote:
> On second thought, maybe it would make more sense to squash all logical
> commits together (dt-bindings, hwporobe, etc) with all the ISA
> extensions in each. Tell me if you think it would be better.
I don't think there's anything wrong with the current approach.
On 12/10/2023 10:21, Conor Dooley wrote:
> On Thu, Oct 12, 2023 at 09:15:46AM +0200, Clément Léger wrote:
>> On second thought, maybe it would make more sense to squash all logical
>> commits together (dt-bindings, hwporobe, etc) with all the ISA
>> extensions in each. Tell me if you think it would be better.
>
> I don't think there's anything wrong with the current approach.
Hi Conor,
Ok then, let's keep like this if there are no objection, I thought it
was a bit "too many" commits just for a few lines, but at least it's
unitary.
Thanks
Clément
On 11/10/2023 13:14, Clément Léger wrote:
> Add probing of some Zv* ISA extensions that are mentioned in "RISC-V
> Cryptography Extensions Volume II" [1]. These ISA extensions are the
> following:
>
> - Zvbb: Vector Basic Bit-manipulation
> - Zvbc: Vector Carryless Multiplication
> - Zvkb: Vector Cryptography Bit-manipulation
> - Zvkg: Vector GCM/GMAC.
> - Zvkned: NIST Suite: Vector AES Block Cipher
> - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
> - Zvksed: ShangMi Suite: SM4 Block Cipher
> - Zvksh: ShangMi Suite: SM3 Secure Hash
> - Zvkn: NIST Algorithm Suite
> - Zvknc: NIST Algorithm Suite with carryless multiply
> - Zvkng: NIST Algorithm Suite with GCM.
> - Zvks: ShangMi Algorithm Suite
> - Zvksc: ShangMi Algorithm Suite with carryless multiplication
> - Zvksg: ShangMi Algorithm Suite with GCM.
> - Zvkt: Vector Data-Independent Execution Latency.
>
> [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
>
> Signed-off-by: Clément Léger <[email protected]>
> ---
> arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++
> arch/riscv/kernel/cpufeature.c | 16 ++++++++++++++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b7b58258f6c7..4e46981ac6c8 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -58,6 +58,22 @@
> #define RISCV_ISA_EXT_ZICSR 40
> #define RISCV_ISA_EXT_ZIFENCEI 41
> #define RISCV_ISA_EXT_ZIHPM 42
> +#define RISCV_ISA_EXT_ZVBB 43
> +#define RISCV_ISA_EXT_ZVBC 44
> +#define RISCV_ISA_EXT_ZVKB 45
> +#define RISCV_ISA_EXT_ZVKG 46
> +#define RISCV_ISA_EXT_ZVKN 47
> +#define RISCV_ISA_EXT_ZVKNC 48
> +#define RISCV_ISA_EXT_ZVKNED 49
> +#define RISCV_ISA_EXT_ZVKNG 50
> +#define RISCV_ISA_EXT_ZVKNHA 51
> +#define RISCV_ISA_EXT_ZVKNHB 52
> +#define RISCV_ISA_EXT_ZVKS 53
> +#define RISCV_ISA_EXT_ZVKSC 54
> +#define RISCV_ISA_EXT_ZVKSED 55
> +#define RISCV_ISA_EXT_ZVKSH 56
> +#define RISCV_ISA_EXT_ZVKSG 57
About Zvks/Zvkn, these extensions are actually shorthand for a few other
sub-extensions, it is still not clear if it should be parsed as is.
There are multiple solutions:
- Handle them as-is, simply enable the extension, if reported through
hwprobe, userspace will be responsible to detect the sub-extensions
(current approach)
- "Unfold" the extension in order to enable all the sub-extensions and
keep the main one (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb,
Zvkt, Zvkn)
- "Unfold" but don't keep the extension "shorthand" in the ISA extension
list (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb, Zvkt)
Thanks,
Clément
> +#define RISCV_ISA_EXT_ZVKT 58
>
> #define RISCV_ISA_EXT_MAX 64
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1cfbba65d11a..859d647f3ced 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -174,6 +174,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
> + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
> + __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
> + __RISCV_ISA_EXT_DATA(zvknc, RISCV_ISA_EXT_ZVKNC),
> + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
> + __RISCV_ISA_EXT_DATA(zvkng, RISCV_ISA_EXT_ZVKNG),
> + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
> + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
> + __RISCV_ISA_EXT_DATA(zvks, RISCV_ISA_EXT_ZVKS),
> + __RISCV_ISA_EXT_DATA(zvksc, RISCV_ISA_EXT_ZVKSC),
> + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
> + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
> + __RISCV_ISA_EXT_DATA(zvksg, RISCV_ISA_EXT_ZVKSG),
> + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
Yo,
On Wed, Oct 11, 2023 at 01:14:29PM +0200, Cl?ment L?ger wrote:
> Add Zv* vector crypto extensions that were added in "RISC-V Cryptography
> Extensions Volume II" specificationi[1]:
>
> - Zvbb: Vector Basic Bit-manipulation
> - Zvbc: Vector Carryless Multiplication
> - Zvkb: Vector Cryptography Bit-manipulation
> - Zvkg: Vector GCM/GMAC.
> - Zvkned: NIST Suite: Vector AES Block Cipher
> - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
> - Zvksed: ShangMi Suite: SM4 Block Cipher
> - Zvksh: ShangMi Suite: SM3 Secure Hash
> - Zvkn: NIST Algorithm Suite
> - Zvknc: NIST Algorithm Suite with carryless multiply
> - Zvkng: NIST Algorithm Suite with GCM.
> - Zvks: ShangMi Algorithm Suite
> - Zvksc: ShangMi Algorithm Suite with carryless multiplication
> - Zvksg: ShangMi Algorithm Suite with GCM.
> - Zvkt: Vector Data-Independent Execution Latency.
>
> [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
Link: <whatever> [1]
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> Signed-off-by: Cl?ment L?ger <[email protected]>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..4002c65145c9 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -246,5 +246,101 @@ properties:
> in commit 2e5236 ("Ztso is now ratified.") of the
> riscv-isa-manual.
>
> + - const: zvbb
> + description:
> + The standard Zvbb extension for vectored basic bit-manipulation
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvbc
> + description:
> + The standard Zvbc extension for vectored carryless multiplication
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvkb
> + description:
> + The standard Zvkb extension for vector cryptography bit-manipulation
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvkg
> + description:
> + The standard Zvkg extension for vector GCM/GMAC instructions, as
> + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
> + of riscv-crypto.
> +
> + - const: zvkn
> + description:
> + The standard Zvkn extension for NIST algorithm suite instructions, as
> + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
> + of riscv-crypto.
> +
> + - const: zvknc
> + description:
> + The standard Zvknc extension for NIST algorithm suite with carryless
> + multiply instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvkned
> + description:
> + The standard Zvkned extension for Vector AES block cipher
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvkng
> + description:
> + The standard Zvkng extension for NIST algorithm suite with GCM
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvknha
> + description: |
> + The standard Zvknha extension for NIST suite: vector SHA-2 secure,
> + hash (SHA-256 only) instructions, as ratified in commit
> + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvknhb
> + description: |
> + The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
> + hash (SHA-256 and SHA-512) instructions, as ratified in commit
> + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvks
> + description:
> + The standard Zvks extension for ShangMi algorithm suite
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvksc
> + description:
> + The standard Zvksc extension for ShangMi algorithm suite with
> + carryless multiplication instructions, as ratified in commit 56ed795
> + ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvksed
> + description: |
> + The standard Zvksed extension for ShangMi suite: SM4 block cipher
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvksh
> + description: |
> + The standard Zvksh extension for ShangMi suite: SM3 secure hash
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvksg
> + description:
> + The standard Zvksg extension for ShangMi algorithm suite with GCM
> + instructions, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> + - const: zvkt
> + description:
> + The standard zvkt extension for vector data-independent execution
> + latency, as ratified in commit 56ed795 ("Update
> + riscv-crypto-spec-vector.adoc") of riscv-crypto.
> +
> additionalProperties: true
> ...
> --
> 2.42.0
>
Yo,
On Wed, Oct 11, 2023 at 01:14:32PM +0200, Cl?ment L?ger wrote:
> Add description of Zfh and Zfhmin ISA extensions[1] which can now be
> reported through hwprobe for userspace usage.
>
> [1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view
>
Same here about using Link: tags.
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> Signed-off-by: Cl?ment L?ger <[email protected]>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 4002c65145c9..4c923800d751 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -190,6 +190,19 @@ properties:
> instructions as ratified at commit 6d33919 ("Merge pull request #158
> from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
>
> + - const: zfh
> + description:
> + The standard Zfh extension for 16-bit half-precision binary
> + floating-point instructions, as ratified in commit 64074bc ("Update
> + version numbers for Zfh/Zfinx") of riscv-isa-manual.
> +
> + - const: zfhmin
> + description:
> + The standard Zfhmin extension which provides minimal support for
> + 16-bit half-precision binary floating-point instructions, as ratified
> + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
> + riscv-isa-manual.
> +
> - const: zicbom
> description:
> The standard Zicbom extension for base cache management operations as
> --
> 2.42.0
>
On Wed, Oct 11, 2023 at 01:14:35PM +0200, Cl?ment L?ger wrote:
> Add description for Zihintntl ISA extension[1] which can now be reported
> through hwprobe for userspace usage.
>
> [1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
Ditto. Who is even hosting this google drive anyway? I'd rather see
GitHub links to docs from the releases, but since youre pointing at the
ISA manual I suppose those do not really exist.
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
>
> Signed-off-by: Cl?ment L?ger <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 4c923800d751..70c2b0351357 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -247,6 +247,12 @@ properties:
> The standard Zihintpause extension for pause hints, as ratified in
> commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
>
> + - const: zihintntl
> + description:
> + The standard Zihintntl extension for non-temporal locality hints, as
> + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
> + riscv-isa-manual.
> +
> - const: zihpm
> description:
> The standard Zihpm extension for hardware performance counters, as
> --
> 2.42.0
>
On Wed, Oct 11, 2023 at 01:14:38PM +0200, Cl?ment L?ger wrote:
> Add description for Zvfh[min] ISA extension[1] which can now be
> reported through hwprobe for userspace usage.
>
> [1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view
And once more, the same.
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
>
> Signed-off-by: Cl?ment L?ger <[email protected]>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 70c2b0351357..ae7db420ab92 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -277,6 +277,18 @@ properties:
> instructions, as ratified in commit 56ed795 ("Update
> riscv-crypto-spec-vector.adoc") of riscv-crypto.
>
> + - const: zvfh
> + description:
> + The standard Zvfh extension for vectored half-precision
> + floating-point instructions, as ratified in commit e2ccd05
> + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
> +
> + - const: zvfhmin
> + description:
> + The standard Zvfhmin extension for vectored minimal half-precision
> + floating-point instructions, as ratified in commit e2ccd05
> + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
> +
> - const: zvkb
> description:
> The standard Zvkb extension for vector cryptography bit-manipulation
> --
> 2.42.0
>
Drew,
On Wed, Oct 11, 2023 at 01:14:26PM +0200, Cl?ment L?ger wrote:
> Factorize ISA extension reporting by using a macro rather than
> copy/pasting extension names. This will allow adding new extensions more
> easily.
>
> Signed-off-by: Cl?ment L?ger <[email protected]>
> ---
> arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++--------------
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> index 473159b5f303..5ce593ce07a4 100644
> --- a/arch/riscv/kernel/sys_riscv.c
> +++ b/arch/riscv/kernel/sys_riscv.c
> @@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> for_each_cpu(cpu, cpus) {
We were gonna add a comment here about when it is and is not safe to use
riscv_isa_extension_available() IIRC. Did that ever end up in a patch?
> struct riscv_isainfo *isainfo = &hart_isa[cpu];
>
> - if (riscv_isa_extension_available(isainfo->isa, ZBA))
> - pair->value |= RISCV_HWPROBE_EXT_ZBA;
> - else
> - missing |= RISCV_HWPROBE_EXT_ZBA;
> -
> - if (riscv_isa_extension_available(isainfo->isa, ZBB))
> - pair->value |= RISCV_HWPROBE_EXT_ZBB;
> - else
> - missing |= RISCV_HWPROBE_EXT_ZBB;
> -
> - if (riscv_isa_extension_available(isainfo->isa, ZBS))
> - pair->value |= RISCV_HWPROBE_EXT_ZBS;
> - else
> - missing |= RISCV_HWPROBE_EXT_ZBS;
> +#define CHECK_ISA_EXT(__ext) \
> + do { \
> + if (riscv_isa_extension_available(isainfo->isa, __ext)) \
> + pair->value |= RISCV_HWPROBE_EXT_##__ext; \
> + else \
> + missing |= RISCV_HWPROBE_EXT_##__ext; \
> + } while (false) \
> +
> + CHECK_ISA_EXT(ZBA);
> + CHECK_ISA_EXT(ZBB);
> + CHECK_ISA_EXT(ZBS);
> +#undef CHECK_ISA_EXT
> }
>
> /* Now turn off reporting features if any CPU is missing it. */
> --
> 2.42.0
>
On 12/10/2023 15:50, Conor Dooley wrote:
> On Wed, Oct 11, 2023 at 01:14:35PM +0200, Clément Léger wrote:
>> Add description for Zihintntl ISA extension[1] which can now be
>> reported through hwprobe for userspace usage.
>>
>> [1]
>> https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
>
>>
> Ditto. Who is even hosting this google drive anyway? I'd rather see
> GitHub links to docs from the releases, but since youre pointing at
> the ISA manual I suppose those do not really exist.
Acked, I'll fix all these as "Links:"
Regarding the pdf sources themselves, I actually used the links as
referred on the RISC-V wiki [1] which is the wiki mentioned from the
riscv.org website [2]. I do not like it but there does not seems to have
a proper specification release website...
Maybe pointing only to a specific commit on the github repo that
mentioned that the extension was ratified is better.
Thanks,
Clément
[1] https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
[2] https://riscv.org/technical/specifications/
> Acked-by: Conor Dooley <[email protected]>
>
> Thanks, Conor.
>>
>> Signed-off-by: Clément Léger <[email protected]> ---
>> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/riscv/extensions.yaml
>> b/Documentation/devicetree/bindings/riscv/extensions.yaml index
>> 4c923800d751..70c2b0351357 100644 ---
>> a/Documentation/devicetree/bindings/riscv/extensions.yaml +++
>> b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -247,6
>> +247,12 @@ properties: The standard Zihintpause extension for pause
>> hints, as ratified in commit d8ab5c7 ("Zihintpause is ratified") of
>> the riscv-isa-manual.
>>
>> + - const: zihintntl + description: +
>> The standard Zihintntl extension for non-temporal locality hints,
>> as + ratified in commit 0dc91f5 ("Zihintntl is
>> ratified") of the + riscv-isa-manual. + - const: zihpm
>> description: The standard Zihpm extension for hardware performance
>> counters, as -- 2.42.0
>>
On Thu, Oct 12, 2023 at 03:17:14PM +0200, Cl?ment L?ger wrote:
>
>
> On 11/10/2023 13:14, Cl?ment L?ger wrote:
> > Add probing of some Zv* ISA extensions that are mentioned in "RISC-V
> > Cryptography Extensions Volume II" [1]. These ISA extensions are the
> > following:
> >
> > - Zvbb: Vector Basic Bit-manipulation
> > - Zvbc: Vector Carryless Multiplication
> > - Zvkb: Vector Cryptography Bit-manipulation
> > - Zvkg: Vector GCM/GMAC.
> > - Zvkned: NIST Suite: Vector AES Block Cipher
> > - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
> > - Zvksed: ShangMi Suite: SM4 Block Cipher
> > - Zvksh: ShangMi Suite: SM3 Secure Hash
> > - Zvkn: NIST Algorithm Suite
> > - Zvknc: NIST Algorithm Suite with carryless multiply
> > - Zvkng: NIST Algorithm Suite with GCM.
> > - Zvks: ShangMi Algorithm Suite
> > - Zvksc: ShangMi Algorithm Suite with carryless multiplication
> > - Zvksg: ShangMi Algorithm Suite with GCM.
> > - Zvkt: Vector Data-Independent Execution Latency.
> >
> > [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
> >
> > Signed-off-by: Cl?ment L?ger <[email protected]>
> > ---
> > arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++
> > arch/riscv/kernel/cpufeature.c | 16 ++++++++++++++++
> > 2 files changed, 32 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index b7b58258f6c7..4e46981ac6c8 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -58,6 +58,22 @@
> > #define RISCV_ISA_EXT_ZICSR 40
> > #define RISCV_ISA_EXT_ZIFENCEI 41
> > #define RISCV_ISA_EXT_ZIHPM 42
> > +#define RISCV_ISA_EXT_ZVBB 43
> > +#define RISCV_ISA_EXT_ZVBC 44
> > +#define RISCV_ISA_EXT_ZVKB 45
> > +#define RISCV_ISA_EXT_ZVKG 46
> > +#define RISCV_ISA_EXT_ZVKN 47
> > +#define RISCV_ISA_EXT_ZVKNC 48
> > +#define RISCV_ISA_EXT_ZVKNED 49
> > +#define RISCV_ISA_EXT_ZVKNG 50
> > +#define RISCV_ISA_EXT_ZVKNHA 51
> > +#define RISCV_ISA_EXT_ZVKNHB 52
> > +#define RISCV_ISA_EXT_ZVKS 53
> > +#define RISCV_ISA_EXT_ZVKSC 54
> > +#define RISCV_ISA_EXT_ZVKSED 55
> > +#define RISCV_ISA_EXT_ZVKSH 56
> > +#define RISCV_ISA_EXT_ZVKSG 57
>
> About Zvks/Zvkn, these extensions are actually shorthand for a few other
> sub-extensions, it is still not clear if it should be parsed as is.
> There are multiple solutions:
>
> - Handle them as-is, simply enable the extension, if reported through
> hwprobe, userspace will be responsible to detect the sub-extensions
> (current approach)
I dislike this, since in-kernel users will have to check for "parent" &
"child" extensions.
> - "Unfold" the extension in order to enable all the sub-extensions and
> keep the main one (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb,
> Zvkt, Zvkn)
We threw together some code for this a few months ago after some
discussion with some of your Rivos colleagues. The initial version of it
was in this thread with Evan:
https://lore.kernel.org/all/20230703-mangle-panning-75909ebbe30c@spud/
and in a later iteration there was some more done by myself and Drew:
https://lore.kernel.org/all/20230713-bootleg-tray-c5bfe58b5673@wendy/
One of the versions ended up as the riscv-extensions-strings-scalar-crypto
branch in my k.org repo:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-extensions-strings-scalar-crypto
That crypto stuff has all gone quiet of late unfortunately. I wonder if
Samuel is still working on it.
> - "Unfold" but don't keep the extension "shorthand" in the ISA extension
> list (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb, Zvkt)
But I would also be fine with this one from a pure in-kernel PoV.
I think it's likely to be annoying for users though, since they won't be
able to poll for the "parent" unless we re-assemble the parents in
hwprobe etc (eugh).
- don't permit passing the "parents" at all, and only deal with the
"children". We can enforce this for DT, but not for ACPI, so probably
not a runner.
Thanks,
Conor.
>
> Thanks,
>
> Cl?ment
>
> > +#define RISCV_ISA_EXT_ZVKT 58
> >
> > #define RISCV_ISA_EXT_MAX 64
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 1cfbba65d11a..859d647f3ced 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -174,6 +174,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> > + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
> > + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> > + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
> > + __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
> > + __RISCV_ISA_EXT_DATA(zvknc, RISCV_ISA_EXT_ZVKNC),
> > + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
> > + __RISCV_ISA_EXT_DATA(zvkng, RISCV_ISA_EXT_ZVKNG),
> > + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
> > + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
> > + __RISCV_ISA_EXT_DATA(zvks, RISCV_ISA_EXT_ZVKS),
> > + __RISCV_ISA_EXT_DATA(zvksc, RISCV_ISA_EXT_ZVKSC),
> > + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
> > + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
> > + __RISCV_ISA_EXT_DATA(zvksg, RISCV_ISA_EXT_ZVKSG),
> > + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
> > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
On 12/10/2023 16:10, Conor Dooley wrote:
> On Thu, Oct 12, 2023 at 03:17:14PM +0200, Clément Léger wrote:
>>
>>
>> On 11/10/2023 13:14, Clément Léger wrote:
>>> Add probing of some Zv* ISA extensions that are mentioned in "RISC-V
>>> Cryptography Extensions Volume II" [1]. These ISA extensions are the
>>> following:
>>>
>>> - Zvbb: Vector Basic Bit-manipulation
>>> - Zvbc: Vector Carryless Multiplication
>>> - Zvkb: Vector Cryptography Bit-manipulation
>>> - Zvkg: Vector GCM/GMAC.
>>> - Zvkned: NIST Suite: Vector AES Block Cipher
>>> - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
>>> - Zvksed: ShangMi Suite: SM4 Block Cipher
>>> - Zvksh: ShangMi Suite: SM3 Secure Hash
>>> - Zvkn: NIST Algorithm Suite
>>> - Zvknc: NIST Algorithm Suite with carryless multiply
>>> - Zvkng: NIST Algorithm Suite with GCM.
>>> - Zvks: ShangMi Algorithm Suite
>>> - Zvksc: ShangMi Algorithm Suite with carryless multiplication
>>> - Zvksg: ShangMi Algorithm Suite with GCM.
>>> - Zvkt: Vector Data-Independent Execution Latency.
>>>
>>> [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
>>>
>>> Signed-off-by: Clément Léger <[email protected]>
>>> ---
>>> arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++
>>> arch/riscv/kernel/cpufeature.c | 16 ++++++++++++++++
>>> 2 files changed, 32 insertions(+)
>>>
>>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>>> index b7b58258f6c7..4e46981ac6c8 100644
>>> --- a/arch/riscv/include/asm/hwcap.h
>>> +++ b/arch/riscv/include/asm/hwcap.h
>>> @@ -58,6 +58,22 @@
>>> #define RISCV_ISA_EXT_ZICSR 40
>>> #define RISCV_ISA_EXT_ZIFENCEI 41
>>> #define RISCV_ISA_EXT_ZIHPM 42
>>> +#define RISCV_ISA_EXT_ZVBB 43
>>> +#define RISCV_ISA_EXT_ZVBC 44
>>> +#define RISCV_ISA_EXT_ZVKB 45
>>> +#define RISCV_ISA_EXT_ZVKG 46
>>> +#define RISCV_ISA_EXT_ZVKN 47
>>> +#define RISCV_ISA_EXT_ZVKNC 48
>>> +#define RISCV_ISA_EXT_ZVKNED 49
>>> +#define RISCV_ISA_EXT_ZVKNG 50
>>> +#define RISCV_ISA_EXT_ZVKNHA 51
>>> +#define RISCV_ISA_EXT_ZVKNHB 52
>>> +#define RISCV_ISA_EXT_ZVKS 53
>>> +#define RISCV_ISA_EXT_ZVKSC 54
>>> +#define RISCV_ISA_EXT_ZVKSED 55
>>> +#define RISCV_ISA_EXT_ZVKSH 56
>>> +#define RISCV_ISA_EXT_ZVKSG 57
>>
>> About Zvks/Zvkn, these extensions are actually shorthand for a few other
>> sub-extensions, it is still not clear if it should be parsed as is.
>> There are multiple solutions:
>>
>> - Handle them as-is, simply enable the extension, if reported through
>> hwprobe, userspace will be responsible to detect the sub-extensions
>> (current approach)
>
> I dislike this, since in-kernel users will have to check for "parent" &
> "child" extensions.
>
>> - "Unfold" the extension in order to enable all the sub-extensions and
>> keep the main one (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb,
>> Zvkt, Zvkn)
>
> We threw together some code for this a few months ago after some
> discussion with some of your Rivos colleagues. The initial version of it
> was in this thread with Evan:
> https://lore.kernel.org/all/20230703-mangle-panning-75909ebbe30c@spud/
> and in a later iteration there was some more done by myself and Drew:
> https://lore.kernel.org/all/20230713-bootleg-tray-c5bfe58b5673@wendy/
> One of the versions ended up as the riscv-extensions-strings-scalar-crypto
> branch in my k.org repo:
> https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-extensions-strings-scalar-crypto
>
Thanks for these information ! I think your version to handle extension
group is pretty clean. Are you waiting for anything in particular except
a Signed-off: from Evan to submit that patch ? If so, can I backport
this patch in my branch, gather Evan SoB and rebase my series on top of it ?
> That crypto stuff has all gone quiet of late unfortunately. I wonder if
> Samuel is still working on it.
I talked with Samuel and we agreed on the following plan: I'll actually
carry on the bitmanip ISA part and he will resubmit the Zkr with
archrandom part.
>
>> - "Unfold" but don't keep the extension "shorthand" in the ISA extension
>> list (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb, Zvkt)
>
> But I would also be fine with this one from a pure in-kernel PoV.
Which is the case with your version FWIU (ie, only the child extensions
are visible).
> I think it's likely to be annoying for users though, since they won't be
> able to poll for the "parent" unless we re-assemble the parents in
> hwprobe etc (eugh).
Indeed, and re-assembling the parent is IMHO duplication of the existing
information. Checking that the needed ISA extensions are present will be
simple enough (simple bitmask) so I'm not sure that re-assembling the
parents is necessary (But that's a personal statement and I'm pretty
sure others will like it to be provided directly).
Thanks,
Clément
>
> - don't permit passing the "parents" at all, and only deal with the
> "children". We can enforce this for DT, but not for ACPI, so probably
> not a runner>
> Thanks,
> Conor.
>
>>
>> Thanks,
>>
>> Clément
>>
>>> +#define RISCV_ISA_EXT_ZVKT 58
>>>
>>> #define RISCV_ISA_EXT_MAX 64
>>>
>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>>> index 1cfbba65d11a..859d647f3ced 100644
>>> --- a/arch/riscv/kernel/cpufeature.c
>>> +++ b/arch/riscv/kernel/cpufeature.c
>>> @@ -174,6 +174,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>>> __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
>>> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
>>> __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
>>> + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
>>> + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
>>> + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
>>> + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
>>> + __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
>>> + __RISCV_ISA_EXT_DATA(zvknc, RISCV_ISA_EXT_ZVKNC),
>>> + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
>>> + __RISCV_ISA_EXT_DATA(zvkng, RISCV_ISA_EXT_ZVKNG),
>>> + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
>>> + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
>>> + __RISCV_ISA_EXT_DATA(zvks, RISCV_ISA_EXT_ZVKS),
>>> + __RISCV_ISA_EXT_DATA(zvksc, RISCV_ISA_EXT_ZVKSC),
>>> + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
>>> + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
>>> + __RISCV_ISA_EXT_DATA(zvksg, RISCV_ISA_EXT_ZVKSG),
>>> + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
>>> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
>>> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
>>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
Hey,
On Thu, Oct 12, 2023 at 05:15:45PM +0200, Cl?ment L?ger wrote:
> On 12/10/2023 16:10, Conor Dooley wrote:
> > On Thu, Oct 12, 2023 at 03:17:14PM +0200, Cl?ment L?ger wrote:
> >> On 11/10/2023 13:14, Cl?ment L?ger wrote:
> >>> Add probing of some Zv* ISA extensions that are mentioned in "RISC-V
> >>> Cryptography Extensions Volume II" [1]. These ISA extensions are the
> >>> following:
> >>>
> >>> - Zvbb: Vector Basic Bit-manipulation
> >>> - Zvbc: Vector Carryless Multiplication
> >>> - Zvkb: Vector Cryptography Bit-manipulation
> >>> - Zvkg: Vector GCM/GMAC.
> >>> - Zvkned: NIST Suite: Vector AES Block Cipher
> >>> - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
> >>> - Zvksed: ShangMi Suite: SM4 Block Cipher
> >>> - Zvksh: ShangMi Suite: SM3 Secure Hash
> >>> - Zvkn: NIST Algorithm Suite
> >>> - Zvknc: NIST Algorithm Suite with carryless multiply
> >>> - Zvkng: NIST Algorithm Suite with GCM.
> >>> - Zvks: ShangMi Algorithm Suite
> >>> - Zvksc: ShangMi Algorithm Suite with carryless multiplication
> >>> - Zvksg: ShangMi Algorithm Suite with GCM.
> >>> - Zvkt: Vector Data-Independent Execution Latency.
> >>>
> >>> [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
> >>>
> >>> Signed-off-by: Cl?ment L?ger <[email protected]>
> >>> ---
> >>> arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++
> >>> arch/riscv/kernel/cpufeature.c | 16 ++++++++++++++++
> >>> 2 files changed, 32 insertions(+)
> >>>
> >>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> >>> index b7b58258f6c7..4e46981ac6c8 100644
> >>> --- a/arch/riscv/include/asm/hwcap.h
> >>> +++ b/arch/riscv/include/asm/hwcap.h
> >>> @@ -58,6 +58,22 @@
> >>> #define RISCV_ISA_EXT_ZICSR 40
> >>> #define RISCV_ISA_EXT_ZIFENCEI 41
> >>> #define RISCV_ISA_EXT_ZIHPM 42
> >>> +#define RISCV_ISA_EXT_ZVBB 43
> >>> +#define RISCV_ISA_EXT_ZVBC 44
> >>> +#define RISCV_ISA_EXT_ZVKB 45
> >>> +#define RISCV_ISA_EXT_ZVKG 46
> >>> +#define RISCV_ISA_EXT_ZVKN 47
> >>> +#define RISCV_ISA_EXT_ZVKNC 48
> >>> +#define RISCV_ISA_EXT_ZVKNED 49
> >>> +#define RISCV_ISA_EXT_ZVKNG 50
> >>> +#define RISCV_ISA_EXT_ZVKNHA 51
> >>> +#define RISCV_ISA_EXT_ZVKNHB 52
> >>> +#define RISCV_ISA_EXT_ZVKS 53
> >>> +#define RISCV_ISA_EXT_ZVKSC 54
> >>> +#define RISCV_ISA_EXT_ZVKSED 55
> >>> +#define RISCV_ISA_EXT_ZVKSH 56
> >>> +#define RISCV_ISA_EXT_ZVKSG 57
> >>
> >> About Zvks/Zvkn, these extensions are actually shorthand for a few other
> >> sub-extensions, it is still not clear if it should be parsed as is.
> >> There are multiple solutions:
> >>
> >> - Handle them as-is, simply enable the extension, if reported through
> >> hwprobe, userspace will be responsible to detect the sub-extensions
> >> (current approach)
> >
> > I dislike this, since in-kernel users will have to check for "parent" &
> > "child" extensions.
> >
> >> - "Unfold" the extension in order to enable all the sub-extensions and
> >> keep the main one (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb,
> >> Zvkt, Zvkn)
> >
> > We threw together some code for this a few months ago after some
> > discussion with some of your Rivos colleagues. The initial version of it
> > was in this thread with Evan:
> > https://lore.kernel.org/all/20230703-mangle-panning-75909ebbe30c@spud/
> > and in a later iteration there was some more done by myself and Drew:
> > https://lore.kernel.org/all/20230713-bootleg-tray-c5bfe58b5673@wendy/
> > One of the versions ended up as the riscv-extensions-strings-scalar-crypto
> > branch in my k.org repo:
> > https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-extensions-strings-scalar-crypto
> >
>
> Thanks for these information ! I think your version to handle extension
> group is pretty clean. Are you waiting for anything in particular except
> a Signed-off: from Evan to submit that patch ?
Lack of a user. I was hoping that it'd go alongside the crypto extension
stuff that needed it.
> If so, can I backport
> this patch in my branch, gather Evan SoB and rebase my series on top of it ?
For sure.
> > That crypto stuff has all gone quiet of late unfortunately. I wonder if
> > Samuel is still working on it.
>
> I talked with Samuel and we agreed on the following plan: I'll actually
> carry on the bitmanip ISA part and he will resubmit the Zkr with
> archrandom part.
:+1:
> >> - "Unfold" but don't keep the extension "shorthand" in the ISA extension
> >> list (for instance for Zvkn, enable Zvkned, Zvknhb, Zvkb, Zvkt)
> >
> > But I would also be fine with this one from a pure in-kernel PoV.
>
> Which is the case with your version FWIU (ie, only the child extensions
> are visible).
Yeah, I think I might've done it intentionally so that the same thing
appeared in /proc/cpuinfo whether the "parent" or all the "children"
were provided in DT.
(I wrote that stuff before hwprobe got merge I think)
I think users would probably appreciate being able to poll for the whole
extension, rather than the component parts. There's probably also some
thoughts expressed in the two threads I linked, IIRC Evan and I did
discuss some of the behaviour there. What to do if an extension later
grows a subset springs to mind.
Conor.
> > I think it's likely to be annoying for users though, since they won't be
> > able to poll for the "parent" unless we re-assemble the parents in
> > hwprobe etc (eugh).
>
> Indeed, and re-assembling the parent is IMHO duplication of the existing
> information. Checking that the needed ISA extensions are present will be
> simple enough (simple bitmask) so I'm not sure that re-assembling the
> parents is necessary (But that's a personal statement and I'm pretty
> sure others will like it to be provided directly).
>
> Thanks,
>
> Cl?ment
>
> >
> > - don't permit passing the "parents" at all, and only deal with the
> > "children". We can enforce this for DT, but not for ACPI, so probably
> > not a runner>
> > Thanks,
> > Conor.
> >
> >>
> >> Thanks,
> >>
> >> Cl?ment
> >>
> >>> +#define RISCV_ISA_EXT_ZVKT 58
> >>>
> >>> #define RISCV_ISA_EXT_MAX 64
> >>>
> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >>> index 1cfbba65d11a..859d647f3ced 100644
> >>> --- a/arch/riscv/kernel/cpufeature.c
> >>> +++ b/arch/riscv/kernel/cpufeature.c
> >>> @@ -174,6 +174,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >>> __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> >>> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> >>> __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> >>> + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
> >>> + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> >>> + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> >>> + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
> >>> + __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
> >>> + __RISCV_ISA_EXT_DATA(zvknc, RISCV_ISA_EXT_ZVKNC),
> >>> + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
> >>> + __RISCV_ISA_EXT_DATA(zvkng, RISCV_ISA_EXT_ZVKNG),
> >>> + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
> >>> + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
> >>> + __RISCV_ISA_EXT_DATA(zvks, RISCV_ISA_EXT_ZVKS),
> >>> + __RISCV_ISA_EXT_DATA(zvksc, RISCV_ISA_EXT_ZVKSC),
> >>> + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
> >>> + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
> >>> + __RISCV_ISA_EXT_DATA(zvksg, RISCV_ISA_EXT_ZVKSG),
> >>> + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
> >>> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> >>> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> >>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
On Thu, Oct 12, 2023 at 02:53:43PM +0100, Conor Dooley wrote:
> Drew,
>
> On Wed, Oct 11, 2023 at 01:14:26PM +0200, Cl?ment L?ger wrote:
> > Factorize ISA extension reporting by using a macro rather than
> > copy/pasting extension names. This will allow adding new extensions more
> > easily.
> >
> > Signed-off-by: Cl?ment L?ger <[email protected]>
> > ---
> > arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++--------------
> > 1 file changed, 12 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> > index 473159b5f303..5ce593ce07a4 100644
> > --- a/arch/riscv/kernel/sys_riscv.c
> > +++ b/arch/riscv/kernel/sys_riscv.c
> > @@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> > for_each_cpu(cpu, cpus) {
>
> We were gonna add a comment here about when it is and is not safe to use
> riscv_isa_extension_available() IIRC. Did that ever end up in a patch?
Yup, it's in [1]. But that series may be hung up on spec stuff, so maybe
it'd be better for Cl?ment to integrate it. And, it appears we definitely
need this macro, because it has now been suggested by three different
people :-) (I later saw Samuel was first[2], but I hadn't seen his before
submitting mine, otherwise I would have given him the credit.)
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
Thanks,
drew
>
> > struct riscv_isainfo *isainfo = &hart_isa[cpu];
> >
> > - if (riscv_isa_extension_available(isainfo->isa, ZBA))
> > - pair->value |= RISCV_HWPROBE_EXT_ZBA;
> > - else
> > - missing |= RISCV_HWPROBE_EXT_ZBA;
> > -
> > - if (riscv_isa_extension_available(isainfo->isa, ZBB))
> > - pair->value |= RISCV_HWPROBE_EXT_ZBB;
> > - else
> > - missing |= RISCV_HWPROBE_EXT_ZBB;
> > -
> > - if (riscv_isa_extension_available(isainfo->isa, ZBS))
> > - pair->value |= RISCV_HWPROBE_EXT_ZBS;
> > - else
> > - missing |= RISCV_HWPROBE_EXT_ZBS;
> > +#define CHECK_ISA_EXT(__ext) \
> > + do { \
> > + if (riscv_isa_extension_available(isainfo->isa, __ext)) \
> > + pair->value |= RISCV_HWPROBE_EXT_##__ext; \
> > + else \
> > + missing |= RISCV_HWPROBE_EXT_##__ext; \
> > + } while (false) \
> > +
> > + CHECK_ISA_EXT(ZBA);
> > + CHECK_ISA_EXT(ZBB);
> > + CHECK_ISA_EXT(ZBS);
> > +#undef CHECK_ISA_EXT
> > }
> >
> > /* Now turn off reporting features if any CPU is missing it. */
> > --
> > 2.42.0
> >