Add the quad spi controller node for the StarFive JH7110 SoC.
Co-developed-by: Ziv Xu <[email protected]>
Signed-off-by: Ziv Xu <[email protected]>
Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..983b683e2f27 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -126,6 +126,38 @@ &i2c6 {
status = "okay";
};
+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nor_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ cdns,read-delay = <5>;
+ spi-max-frequency = <12000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x20000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x300000>;
+ };
+ data@f00000 {
+ reg = <0xf00000 0x100000>;
+ };
+ };
+ };
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..fe33c5616565 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 {
status = "disabled";
};
+ qspi: spi@13010000 {
+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x13010000 0x0 0x10000>,
+ <0x0 0x21000000 0x0 0x400000>;
+ interrupts = <25>;
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
+ clock-names = "ref", "ahb", "apb";
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.34.1
On 04/07/2023 11:04, William Qiu wrote:
> Add the quad spi controller node for the StarFive JH7110 SoC.
>
> Co-developed-by: Ziv Xu <[email protected]>
> Signed-off-by: Ziv Xu <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> Reviewed-by: Hal Feng <[email protected]>
...
> + qspi: spi@13010000 {
> + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
> + reg = <0x0 0x13010000 0x0 0x10000>,
> + <0x0 0x21000000 0x0 0x400000>;
> + interrupts = <25>;
> + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
> + <&syscrg JH7110_SYSCLK_QSPI_AHB>,
> + <&syscrg JH7110_SYSCLK_QSPI_APB>;
> + clock-names = "ref", "ahb", "apb";
> + resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
> + <&syscrg JH7110_SYSRST_QSPI_AHB>,
> + <&syscrg JH7110_SYSRST_QSPI_REF>;
> + reset-names = "qspi", "qspi-ocp", "rstc_ref";
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
Bus nodes are usually disabled by default and enabled when needed for
specific boards.
Best regards,
Krzysztof
On 2023/7/4 17:43, Krzysztof Kozlowski wrote:
> On 04/07/2023 11:04, William Qiu wrote:
>> Add the quad spi controller node for the StarFive JH7110 SoC.
>>
>> Co-developed-by: Ziv Xu <[email protected]>
>> Signed-off-by: Ziv Xu <[email protected]>
>> Signed-off-by: William Qiu <[email protected]>
>> Reviewed-by: Hal Feng <[email protected]>
>
> ...
>
>> + qspi: spi@13010000 {
>> + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
>> + reg = <0x0 0x13010000 0x0 0x10000>,
>> + <0x0 0x21000000 0x0 0x400000>;
>> + interrupts = <25>;
>> + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
>> + <&syscrg JH7110_SYSCLK_QSPI_AHB>,
>> + <&syscrg JH7110_SYSCLK_QSPI_APB>;
>> + clock-names = "ref", "ahb", "apb";
>> + resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
>> + <&syscrg JH7110_SYSRST_QSPI_AHB>,
>> + <&syscrg JH7110_SYSRST_QSPI_REF>;
>> + reset-names = "qspi", "qspi-ocp", "rstc_ref";
>> + cdns,fifo-depth = <256>;
>> + cdns,fifo-width = <4>;
>> + cdns,trigger-address = <0x0>;
>
> Bus nodes are usually disabled by default and enabled when needed for
> specific boards.
>
Will add status.
Thanks for your comments.
Best regards,
William
> Best regards,
> Krzysztof
>
Hi,
On 2023-07-04 17:04, William Qiu wrote:
> Add the quad spi controller node for the StarFive JH7110 SoC.
>
> Co-developed-by: Ziv Xu <[email protected]>
> Signed-off-by: Ziv Xu <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> Reviewed-by: Hal Feng <[email protected]>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 2a6d81609284..983b683e2f27 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -126,6 +126,38 @@ &i2c6 {
> status = "okay";
> };
>
> +&qspi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nor_flash: flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + cdns,read-delay = <5>;
> + spi-max-frequency = <12000000>;
> + cdns,tshsl-ns = <1>;
> + cdns,tsd2d-ns = <1>;
> + cdns,tchsh-ns = <1>;
> + cdns,tslch-ns = <1>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + spl@0 {
> + reg = <0x0 0x20000>;
> + };
> + uboot@100000 {
> + reg = <0x100000 0x300000>;
> + };
> + data@f00000 {
> + reg = <0xf00000 0x100000>;
> + };
It appears that this uses the old layout for the SPI flash. The new
layout is described there:
https://doc-en.rvspace.org/VisionFive2/Boot_UG/JH7110_SDK/boot_address_allocation.html
Regards
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://aurel32.net
On 2023/7/18 1:13, Aurelien Jarno wrote:
> Hi,
>
> On 2023-07-04 17:04, William Qiu wrote:
>> Add the quad spi controller node for the StarFive JH7110 SoC.
>>
>> Co-developed-by: Ziv Xu <[email protected]>
>> Signed-off-by: Ziv Xu <[email protected]>
>> Signed-off-by: William Qiu <[email protected]>
>> Reviewed-by: Hal Feng <[email protected]>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..983b683e2f27 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -126,6 +126,38 @@ &i2c6 {
>> status = "okay";
>> };
>>
>> +&qspi {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + nor_flash: flash@0 {
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + cdns,read-delay = <5>;
>> + spi-max-frequency = <12000000>;
>> + cdns,tshsl-ns = <1>;
>> + cdns,tsd2d-ns = <1>;
>> + cdns,tchsh-ns = <1>;
>> + cdns,tslch-ns = <1>;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + spl@0 {
>> + reg = <0x0 0x20000>;
>> + };
>> + uboot@100000 {
>> + reg = <0x100000 0x300000>;
>> + };
>> + data@f00000 {
>> + reg = <0xf00000 0x100000>;
>> + };
>
> It appears that this uses the old layout for the SPI flash. The new
> layout is described there:
>
> https://doc-en.rvspace.org/VisionFive2/Boot_UG/JH7110_SDK/boot_address_allocation.html
>
> Regards
> Aurelien
>
I'll take a look, and use it then.
Thanks for your comments.
Best regards,
William