2016-04-20 17:40:22

by Luke Starrett

Subject: [PATCH v2 1/1] arm64: dts: NS2 secondary core enablement via PSCI

Declare PSCI-1.0 node and enable CPU_ON method via PSCI. Spin-table
memreserve has been removed as well as syscon based reset, as PSCI-1.0
expects reset implementation in firmware.

Signed-off-by: Luke Starrett <[email protected]>
---

Changes from v1:
- No code changes, adding missing reviewers to CC list

arch/arm64/boot/dts/broadcom/ns2.dtsi | 31 +++++++++----------------------
1 file changed, 9 insertions(+), 22 deletions(-)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 123cd9c..ec68ec1 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -33,8 +33,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>

-/memreserve/ 0x84b00000 0x00000008;
-
/ {
compatible = "brcm,ns2";
interrupt-parent = <&gic>;
@@ -49,8 +47,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 0>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x84b00000>;
+ enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};

@@ -58,8 +55,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 1>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x84b00000>;
+ enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};

@@ -67,8 +63,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 2>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x84b00000>;
+ enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};

@@ -76,8 +71,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 3>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x84b00000>;
+ enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};

@@ -86,6 +80,11 @@
};
};

+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
@@ -252,18 +251,6 @@
mmu-masters;
};

- crmu: crmu@65024000 {
- compatible = "syscon";
- reg = <0x65024000 0x100>;
- };
-
- reboot@65024000 {
- compatible ="syscon-reboot";
- regmap = <&crmu>;
- offset = <0x90>;
- mask = <0xfffffffd>;
- };
-
gic: interrupt-controller@65210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.1.0

2016-04-20 19:05:54

by Scott Branden

Subject: Re: [PATCH v2 1/1] arm64: dts: NS2 secondary core enablement via PSCI

Looks good while we are using PSCI-1.0

Acked-by: Scott Branden <[email protected]>

On 16-04-20 10:40 AM, Luke Starrett wrote:
> Declare PSCI-1.0 node and enable CPU_ON method via PSCI. Spin-table
> memreserve has been removed as well as syscon based reset, as PSCI-1.0
> expects reset implementation in firmware.
>
> Signed-off-by: Luke Starrett <[email protected]>
> ---
>
> Changes from v1:
> - No code changes, adding missing reviewers to CC list
>
> arch/arm64/boot/dts/broadcom/ns2.dtsi | 31 +++++++++----------------------
> 1 file changed, 9 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
> index 123cd9c..ec68ec1 100644
> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
> @@ -33,8 +33,6 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/bcm-ns2.h>
>
> -/memreserve/ 0x84b00000 0x00000008;
> -
> / {
> compatible = "brcm,ns2";
> interrupt-parent = <&gic>;
> @@ -49,8 +47,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0 0>;
> - enable-method = "spin-table";
> - cpu-release-addr = <0 0x84b00000>;
> + enable-method = "psci";
> next-level-cache = <&CLUSTER0_L2>;
> };
>
> @@ -58,8 +55,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0 1>;
> - enable-method = "spin-table";
> - cpu-release-addr = <0 0x84b00000>;
> + enable-method = "psci";
> next-level-cache = <&CLUSTER0_L2>;
> };
>
> @@ -67,8 +63,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0 2>;
> - enable-method = "spin-table";
> - cpu-release-addr = <0 0x84b00000>;
> + enable-method = "psci";
> next-level-cache = <&CLUSTER0_L2>;
> };
>
> @@ -76,8 +71,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a57", "arm,armv8";
> reg = <0 3>;
> - enable-method = "spin-table";
> - cpu-release-addr = <0 0x84b00000>;
> + enable-method = "psci";
> next-level-cache = <&CLUSTER0_L2>;
> };
>
> @@ -86,6 +80,11 @@
> };
> };
>
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
> @@ -252,18 +251,6 @@
> mmu-masters;
> };
>
> - crmu: crmu@65024000 {
> - compatible = "syscon";
> - reg = <0x65024000 0x100>;
> - };
> -
> - reboot@65024000 {
> - compatible ="syscon-reboot";
> - regmap = <&crmu>;
> - offset = <0x90>;
> - mask = <0xfffffffd>;
> - };
> -
> gic: interrupt-controller@65210000 {
> compatible = "arm,gic-400";
> #interrupt-cells = <3>;
>

2016-04-22 19:07:34

by Florian Fainelli

Subject: Re: [PATCH v2 1/1] arm64: dts: NS2 secondary core enablement via PSCI

On 20/04/16 10:40, Luke Starrett wrote:
> Declare PSCI-1.0 node and enable CPU_ON method via PSCI. Spin-table
> memreserve has been removed as well as syscon based reset, as PSCI-1.0
> expects reset implementation in firmware.
>
> Signed-off-by: Luke Starrett <[email protected]>

Applied with Scott's Ack, thanks Luke!
--
Florian