Hello JunYi Zhao
On 10/16/23 08:24, JunYi Zhao wrote:
> From: "junyi.zhao" <[email protected]>
>
> Support PWM for S4 soc.
> Now the PWM clock input is done in independent CLKCTRL registers.
> And no more in the PWM registers.
> PWM needs to obtain an external clock source.
>
> Signed-off-by: junyi.zhao <[email protected]>
> ---
> V2 -> V3:
> Rebase and Review the latest upstream code again.
> After reconstruction, stick to the previous code as much as possible.
> drivers/pwm/pwm-meson.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index 25519cddc2a9..fe9fd75747c4 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -99,6 +99,7 @@ struct meson_pwm_channel {
> struct meson_pwm_data {
> const char * const *parent_names;
> unsigned int num_parents;
> + unsigned int extern_clk;
may be bool extern_clk;
> };
>
> struct meson_pwm {
> @@ -396,6 +397,10 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
> .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
> };
>
> +static const struct meson_pwm_data pwm_s4_data = {
> + .extern_clk = true,
> +};
> +
> static const struct of_device_id meson_pwm_matches[] = {
> {
> .compatible = "amlogic,meson8b-pwm",
> @@ -429,6 +434,10 @@ static const struct of_device_id meson_pwm_matches[] = {
> .compatible = "amlogic,meson-g12a-ao-pwm-cd",
> .data = &pwm_g12a_ao_cd_data
> },
> + {
> + .compatible = "amlogic,s4-pwm",
> + .data = &pwm_s4_data,
> + },
> {},
> };
> MODULE_DEVICE_TABLE(of, meson_pwm_matches);
> @@ -451,6 +460,16 @@ static int meson_pwm_init_channels(struct meson_pwm *meson)
> struct clk_parent_data div_parent = {}, gate_parent = {};
> struct clk_init_data init = {};
>
> + if (meson->data->extern_clk) {
> + snprintf(name, sizeof(name), "clkin%u", i);
> + channel->clk = devm_clk_get(dev, name);
> + if (IS_ERR(channel->clk)) {
> + dev_err(meson->chip.dev, "can't get device clock\n");
> + return PTR_ERR(channel->clk);
> + }
> + continue;
> + }
> +
> snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
>
> init.name = name;
>
> base-commit: 4d2c646ac07cf4a35ef1c4a935a1a4fd6c6b1a36
--
Best regards
George
Hi George, thank u for your review.
I will change it.
On 2023/10/24 4:07, George Stark wrote:
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>
> Hello JunYi Zhao
>
> On 10/16/23 08:24, JunYi Zhao wrote:
>> From: "junyi.zhao" <[email protected]>
>>
>> Support PWM for S4 soc.
>> Now the PWM clock input is done in independent CLKCTRL registers.
>> And no more in the PWM registers.
>> PWM needs to obtain an external clock source.
>>
>> Signed-off-by: junyi.zhao <[email protected]>
>> ---
>> V2 -> V3:
>> Rebase and Review the latest upstream code again.
>> After reconstruction, stick to the previous code as much as possible.
>> drivers/pwm/pwm-meson.c | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
>> index 25519cddc2a9..fe9fd75747c4 100644
>> --- a/drivers/pwm/pwm-meson.c
>> +++ b/drivers/pwm/pwm-meson.c
>> @@ -99,6 +99,7 @@ struct meson_pwm_channel {
>> struct meson_pwm_data {
>> const char * const *parent_names;
>> unsigned int num_parents;
>> + unsigned int extern_clk;
> may be bool extern_clk;
>> };
>>
>> struct meson_pwm {
>> @@ -396,6 +397,10 @@ static const struct meson_pwm_data
>> pwm_g12a_ao_cd_data = {
>> .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
>> };
>>
>> +static const struct meson_pwm_data pwm_s4_data = {
>> + .extern_clk = true,
>> +};
>> +
>> static const struct of_device_id meson_pwm_matches[] = {
>> {
>> .compatible = "amlogic,meson8b-pwm",
>> @@ -429,6 +434,10 @@ static const struct of_device_id
>> meson_pwm_matches[] = {
>> .compatible = "amlogic,meson-g12a-ao-pwm-cd",
>> .data = &pwm_g12a_ao_cd_data
>> },
>> + {
>> + .compatible = "amlogic,s4-pwm",
>> + .data = &pwm_s4_data,
>> + },
>> {},
>> };
>> MODULE_DEVICE_TABLE(of, meson_pwm_matches);
>> @@ -451,6 +460,16 @@ static int meson_pwm_init_channels(struct
>> meson_pwm *meson)
>> struct clk_parent_data div_parent = {}, gate_parent = {};
>> struct clk_init_data init = {};
>>
>> + if (meson->data->extern_clk) {
>> + snprintf(name, sizeof(name), "clkin%u", i);
>> + channel->clk = devm_clk_get(dev, name);
>> + if (IS_ERR(channel->clk)) {
>> + dev_err(meson->chip.dev, "can't get
>> device clock\n");
>> + return PTR_ERR(channel->clk);
>> + }
>> + continue;
>> + }
>> +
>> snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
>>
>> init.name = name;
>>
>> base-commit: 4d2c646ac07cf4a35ef1c4a935a1a4fd6c6b1a36
>
> --
> Best regards
> George
On Mon 23 Oct 2023 at 23:07, George Stark <[email protected]> wrote:
> Hello JunYi Zhao
>
> On 10/16/23 08:24, JunYi Zhao wrote:
>> From: "junyi.zhao" <[email protected]>
>> Support PWM for S4 soc.
>> Now the PWM clock input is done in independent CLKCTRL registers.
>> And no more in the PWM registers.
>> PWM needs to obtain an external clock source.
>> Signed-off-by: junyi.zhao <[email protected]>
>> ---
>> V2 -> V3:
>> Rebase and Review the latest upstream code again.
>> After reconstruction, stick to the previous code as much as possible.
>> drivers/pwm/pwm-meson.c | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
>> index 25519cddc2a9..fe9fd75747c4 100644
>> --- a/drivers/pwm/pwm-meson.c
>> +++ b/drivers/pwm/pwm-meson.c
>> @@ -99,6 +99,7 @@ struct meson_pwm_channel {
>> struct meson_pwm_data {
>> const char * const *parent_names;
>> unsigned int num_parents;
>> + unsigned int extern_clk;
> may be bool extern_clk;
>> };
>> struct meson_pwm {
>> @@ -396,6 +397,10 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
>> .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
>> };
>> +static const struct meson_pwm_data pwm_s4_data = {
>> + .extern_clk = true,
>> +};
>> +
>> static const struct of_device_id meson_pwm_matches[] = {
>> {
>> .compatible = "amlogic,meson8b-pwm",
>> @@ -429,6 +434,10 @@ static const struct of_device_id meson_pwm_matches[] = {
>> .compatible = "amlogic,meson-g12a-ao-pwm-cd",
>> .data = &pwm_g12a_ao_cd_data
>> },
>> + {
>> + .compatible = "amlogic,s4-pwm",
>> + .data = &pwm_s4_data,
>> + },
>> {},
>> };
>> MODULE_DEVICE_TABLE(of, meson_pwm_matches);
>> @@ -451,6 +460,16 @@ static int meson_pwm_init_channels(struct meson_pwm *meson)
>> struct clk_parent_data div_parent = {}, gate_parent = {};
>> struct clk_init_data init = {};
>> + if (meson->data->extern_clk) {
Instead of hacking through the existing registration function, it be
much better to provide the clock registration function as on ops in dt data.
Also, as Neil pointed out on the v2 [1], the meaning of clkin0/1 is changed
on this SoC.
* On previous SoC, it was a reference to clock input the PWM block
should select from the hard-coded list it has (should fix that
someday)
* Now it is directly the input the PWM block must claim.
You need to update the bindings accordingly for the S4
[1]: https://lore.kernel.org/linux-amlogic/[email protected]
>> + snprintf(name, sizeof(name), "clkin%u", i);
>> + channel->clk = devm_clk_get(dev, name);
>> + if (IS_ERR(channel->clk)) {
>> + dev_err(meson->chip.dev, "can't get device clock\n");
>> + return PTR_ERR(channel->clk);
>> + }
>> + continue;
>> + }
>> +
>> snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
>> init.name = name;
>> base-commit: 4d2c646ac07cf4a35ef1c4a935a1a4fd6c6b1a36