The SC8280XP currently shows depressing results in memory benchmarks.
Fix this by introducing support for the platform in the OSM (and EPSS)
L3 driver and support for the platform in the bwmon binding.
Then add the necessary nodes and values throughout the sc8280xp and
sa8540p dtsi files to make the various devices on these platforms scale
both L3, memory bus and DDR.
Bjorn Andersson (10):
interconnect: qcom: osm-l3: Use platform-independent node ids
interconnect: qcom: osm-l3: Squash common descriptors
interconnect: qcom: osm-l3: Add per-core EPSS L3 support
interconnect: qcom: osm-l3: Simplify osm_l3_set()
dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3
compatibles
arm64: dts: qcom: Align with generic osm-l3/epss-l3
arm64: dts: qcom: sc8280xp: Add epss_l3 node
arm64: dts: qcom: sc8280xp: Set up L3 scaling
dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon
instances
arm64: dts: qcom: sc8280xp: Add bwmon instances
.../interconnect/qcom,msm8998-bwmon.yaml | 5 +
.../bindings/interconnect/qcom,osm-l3.yaml | 24 ++-
arch/arm64/boot/dts/qcom/sa8540p.dtsi | 39 +++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 152 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
drivers/interconnect/qcom/osm-l3.c | 126 ++++-----------
10 files changed, 252 insertions(+), 104 deletions(-)
--
2.17.1
Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
Signed-off-by: Bjorn Andersson <[email protected]>
Tested-by: Steev Klimaszewski <[email protected]>
---
Changes since v1:
- Fixed oneOf to be valid schema
- Fixed example to follow schema
.../bindings/interconnect/qcom,osm-l3.yaml | 24 ++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index bf538c0c5a81..aadae4424ba9 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -16,13 +16,21 @@ description:
properties:
compatible:
- enum:
- - qcom,sc7180-osm-l3
- - qcom,sc7280-epss-l3
- - qcom,sc8180x-osm-l3
- - qcom,sdm845-osm-l3
- - qcom,sm8150-osm-l3
- - qcom,sm8250-epss-l3
+ oneOf:
+ - items:
+ - enum:
+ - qcom,sc7180-osm-l3
+ - qcom,sc8180x-osm-l3
+ - qcom,sdm845-osm-l3
+ - qcom,sm8150-osm-l3
+ - const: qcom,osm-l3
+ - items:
+ - enum:
+ - qcom,sc7280-epss-l3
+ - qcom,sc8280xp-epss-l3
+ - qcom,sm8250-epss-l3
+ - qcom,sm8350-epss-l3
+ - const: qcom,epss-l3
reg:
maxItems: 1
@@ -56,7 +64,7 @@ examples:
#define RPMH_CXO_CLK 0
osm_l3: interconnect@17d41000 {
- compatible = "qcom,sdm845-osm-l3";
+ compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
reg = <0x17d41000 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
--
2.17.1
Add a device node for the EPSS L3 frequency domain.
Signed-off-by: Bjorn Andersson <[email protected]>
Tested-by: Steev Klimaszewski <[email protected]>
---
Changes since v1:
- None
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 6bc12e507d21..0e80cdcf6bcf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1782,6 +1782,16 @@
};
};
+ epss_l3: interconnect@18590000 {
+ compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
+ reg = <0 0x18590000 0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
--
2.17.1
On 11/11/2022 04:25, Bjorn Andersson wrote:
> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Tested-by: Steev Klimaszewski <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 11/11/22 08:55, Bjorn Andersson wrote:
> Add a device node for the EPSS L3 frequency domain.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Tested-by: Steev Klimaszewski <[email protected]>
Reviewed-by: Sibi Sankar <[email protected]>
> ---
>
> Changes since v1:
> - None
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 6bc12e507d21..0e80cdcf6bcf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1782,6 +1782,16 @@
> };
> };
>
> + epss_l3: interconnect@18590000 {
> + compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
> + reg = <0 0x18590000 0 0x1000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@18591000 {
> compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
> reg = <0 0x18591000 0 0x1000>,
On 11/11/22 08:55, Bjorn Andersson wrote:
> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Tested-by: Steev Klimaszewski <[email protected]>
> ---
>
> Changes since v1:
> - Fixed oneOf to be valid schema
> - Fixed example to follow schema
>
> .../bindings/interconnect/qcom,osm-l3.yaml | 24 ++++++++++++-------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index bf538c0c5a81..aadae4424ba9 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -16,13 +16,21 @@ description:
>
> properties:
> compatible:
> - enum:
> - - qcom,sc7180-osm-l3
> - - qcom,sc7280-epss-l3
> - - qcom,sc8180x-osm-l3
> - - qcom,sdm845-osm-l3
> - - qcom,sm8150-osm-l3
> - - qcom,sm8250-epss-l3
> + oneOf:
> + - items:
> + - enum:
> + - qcom,sc7180-osm-l3
> + - qcom,sc8180x-osm-l3
> + - qcom,sdm845-osm-l3
> + - qcom,sm8150-osm-l3
> + - const: qcom,osm-l3
> + - items:
> + - enum:
> + - qcom,sc7280-epss-l3
> + - qcom,sc8280xp-epss-l3
> + - qcom,sm8250-epss-l3
> + - qcom,sm8350-epss-l3
> + - const: qcom,epss-l3
isn't it incorrect to describe qcom,epss-l3 as a working
backup compatible for sc7280-epss-l3 and sm8250-epss-l3?
Shouldn't we just add another items list with those 2 as
enums?
>
> reg:
> maxItems: 1
> @@ -56,7 +64,7 @@ examples:
> #define RPMH_CXO_CLK 0
>
> osm_l3: interconnect@17d41000 {
> - compatible = "qcom,sdm845-osm-l3";
> + compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
> reg = <0x17d41000 0x1400>;
>
> clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
On Fri, Nov 11, 2022 at 04:02:42PM +0530, Sibi Sankar wrote:
>
>
> On 11/11/22 08:55, Bjorn Andersson wrote:
> > Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
> > introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
> >
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > Tested-by: Steev Klimaszewski <[email protected]>
> > ---
> >
> > Changes since v1:
> > - Fixed oneOf to be valid schema
> > - Fixed example to follow schema
> >
> > .../bindings/interconnect/qcom,osm-l3.yaml | 24 ++++++++++++-------
> > 1 file changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> > index bf538c0c5a81..aadae4424ba9 100644
> > --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> > +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> > @@ -16,13 +16,21 @@ description:
> > properties:
> > compatible:
> > - enum:
> > - - qcom,sc7180-osm-l3
> > - - qcom,sc7280-epss-l3
> > - - qcom,sc8180x-osm-l3
> > - - qcom,sdm845-osm-l3
> > - - qcom,sm8150-osm-l3
> > - - qcom,sm8250-epss-l3
> > + oneOf:
> > + - items:
> > + - enum:
> > + - qcom,sc7180-osm-l3
> > + - qcom,sc8180x-osm-l3
> > + - qcom,sdm845-osm-l3
> > + - qcom,sm8150-osm-l3
> > + - const: qcom,osm-l3
> > + - items:
> > + - enum:
> > + - qcom,sc7280-epss-l3
> > + - qcom,sc8280xp-epss-l3
> > + - qcom,sm8250-epss-l3
> > + - qcom,sm8350-epss-l3
> > + - const: qcom,epss-l3
>
> isn't it incorrect to describe qcom,epss-l3 as a working
> backup compatible for sc7280-epss-l3 and sm8250-epss-l3?
> Shouldn't we just add another items list with those 2 as
> enums?
>
I was about to agree, but the difference between the two sets are which
registers we use to request the speed.
And per our recent discussion, I was under the impression that this
would be a property of BIT(0) in 0xb0 being set, not which platform
we're running on.
If that's the case then they are indeed compatible and we should adjust
.ref_perf_state based on per-core DCVS being set or not.
So I do think this description is appropriate...
Regards,
Bjorn
> > reg:
> > maxItems: 1
> > @@ -56,7 +64,7 @@ examples:
> > #define RPMH_CXO_CLK 0
> > osm_l3: interconnect@17d41000 {
> > - compatible = "qcom,sdm845-osm-l3";
> > + compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
> > reg = <0x17d41000 0x1400>;
> > clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
On 11/11/22 23:38, Bjorn Andersson wrote:
> On Fri, Nov 11, 2022 at 04:02:42PM +0530, Sibi Sankar wrote:
>>
>>
>> On 11/11/22 08:55, Bjorn Andersson wrote:
>>> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
>>> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
>>>
>>> Signed-off-by: Bjorn Andersson <[email protected]>
>>> Tested-by: Steev Klimaszewski <[email protected]>
>>> ---
>>>
>>> Changes since v1:
>>> - Fixed oneOf to be valid schema
>>> - Fixed example to follow schema
>>>
>>> .../bindings/interconnect/qcom,osm-l3.yaml | 24 ++++++++++++-------
>>> 1 file changed, 16 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>>> index bf538c0c5a81..aadae4424ba9 100644
>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>>> @@ -16,13 +16,21 @@ description:
>>> properties:
>>> compatible:
>>> - enum:
>>> - - qcom,sc7180-osm-l3
>>> - - qcom,sc7280-epss-l3
>>> - - qcom,sc8180x-osm-l3
>>> - - qcom,sdm845-osm-l3
>>> - - qcom,sm8150-osm-l3
>>> - - qcom,sm8250-epss-l3
>>> + oneOf:
>>> + - items:
>>> + - enum:
>>> + - qcom,sc7180-osm-l3
>>> + - qcom,sc8180x-osm-l3
>>> + - qcom,sdm845-osm-l3
>>> + - qcom,sm8150-osm-l3
>>> + - const: qcom,osm-l3
>>> + - items:
>>> + - enum:
>>> + - qcom,sc7280-epss-l3
>>> + - qcom,sc8280xp-epss-l3
>>> + - qcom,sm8250-epss-l3
>>> + - qcom,sm8350-epss-l3
>>> + - const: qcom,epss-l3
>>
>> isn't it incorrect to describe qcom,epss-l3 as a working
>> backup compatible for sc7280-epss-l3 and sm8250-epss-l3?
>> Shouldn't we just add another items list with those 2 as
>> enums?
>>
>
> I was about to agree, but the difference between the two sets are which
> registers we use to request the speed.
>
> And per our recent discussion, I was under the impression that this
> would be a property of BIT(0) in 0xb0 being set, not which platform
> we're running on.
>
> If that's the case then they are indeed compatible and we should adjust
> .ref_perf_state based on per-core DCVS being set or not.
>
>
> So I do think this description is appropriate...
Reviewed-by: Sibi Sankar <[email protected]>
>
> Regards,
> Bjorn
>
>>> reg:
>>> maxItems: 1
>>> @@ -56,7 +64,7 @@ examples:
>>> #define RPMH_CXO_CLK 0
>>> osm_l3: interconnect@17d41000 {
>>> - compatible = "qcom,sdm845-osm-l3";
>>> + compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
>>> reg = <0x17d41000 0x1400>;
>>> clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
On 11.11.22 5:25, Bjorn Andersson wrote:
> The SC8280XP currently shows depressing results in memory benchmarks.
> Fix this by introducing support for the platform in the OSM (and EPSS)
> L3 driver and support for the platform in the bwmon binding.
>
> Then add the necessary nodes and values throughout the sc8280xp and
> sa8540p dtsi files to make the various devices on these platforms scale
> both L3, memory bus and DDR.
Good stuff! Thanks Bjorn!
I plan to merge everything except the dts patches, that should go
through the qcom tree.
BR,
Georgi
> Bjorn Andersson (10):
> interconnect: qcom: osm-l3: Use platform-independent node ids
> interconnect: qcom: osm-l3: Squash common descriptors
> interconnect: qcom: osm-l3: Add per-core EPSS L3 support
> interconnect: qcom: osm-l3: Simplify osm_l3_set()
> dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3
> compatibles
> arm64: dts: qcom: Align with generic osm-l3/epss-l3
> arm64: dts: qcom: sc8280xp: Add epss_l3 node
> arm64: dts: qcom: sc8280xp: Set up L3 scaling
> dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon
> instances
> arm64: dts: qcom: sc8280xp: Add bwmon instances
>
> .../interconnect/qcom,msm8998-bwmon.yaml | 5 +
> .../bindings/interconnect/qcom,osm-l3.yaml | 24 ++-
> arch/arm64/boot/dts/qcom/sa8540p.dtsi | 39 +++++
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 152 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
> drivers/interconnect/qcom/osm-l3.c | 126 ++++-----------
> 10 files changed, 252 insertions(+), 104 deletions(-)
>
On Thu, 10 Nov 2022 19:25:05 -0800, Bjorn Andersson wrote:
> The SC8280XP currently shows depressing results in memory benchmarks.
> Fix this by introducing support for the platform in the OSM (and EPSS)
> L3 driver and support for the platform in the bwmon binding.
>
> Then add the necessary nodes and values throughout the sc8280xp and
> sa8540p dtsi files to make the various devices on these platforms scale
> both L3, memory bus and DDR.
>
> [...]
Applied, thanks!
[06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3
commit: a0289a1040a557428a65d099dfdebe80f1a0d0eb
[07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node
commit: e4f68d6c32aec8f3c7cdb07d18278e9a068a7eb0
[08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling
commit: 33ba07ffd30a1da6f10995ef0a6ec51e17c84f31
[10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances
commit: 64ebe7fc473fb3a7d67b73a2faa0a10cb322cdce
Best regards,
--
Bjorn Andersson <[email protected]>