Snapdragon 8 Gen 1 Mobile Platform [1] (SM8450) is the latest Qualcomm SoC
announced today.
This series adds the DTS support including clocks, tlmm, smmu, regulators,
ufs, interconnects, pmics and cpufreq found in the SM8450 QRD board.
[1]: https://www.qualcomm.com/products/snapdragon-8-gen-1-mobile-platform
Changes in v2:
- add the acks recieved
- move gpio header include to soc dts
- fix the uart node name
- rework pinctrol nodes
- drop cpu clusters
- fix consistency in nodes for reserved mem and icc
- Squash some patches into qrd dts patches
Dmitry Baryshkov (2):
arm64: dts: qcom: sm8450: Add rpmhpd node
arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes
Vinod Koul (10):
arm64: dts: qcom: Add base SM8450 DTSI
arm64: dts: qcom: sm8450: Add tlmm nodes
arm64: dts: qcom: sm8450: Add reserved memory nodes
arm64: dts: qcom: sm8450: add smmu nodes
arm64: dts: qcom: Add base SM8450 QRD DTS
arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes
arm64: dts: qcom: sm8450: add ufs nodes
arm64: dts: qcom: sm8450-qrd: enable ufs nodes
arm64: dts: qcom: sm8450: add interconnect nodes
arm64: dts: qcom: sm8450: add spmi node
Vladimir Zapolskiy (1):
arm64: dts: qcom: sm8450: add cpufreq support
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 378 ++++++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 1125 +++++++++++++++++++++++
3 files changed, 1504 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8450-qrd.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8450.dtsi
--
2.31.1
This add based DTSI for SM8450 SoC and includes base description of
CPUs, GCC, RPMHCC, UART, interuupt-controller which helps to boot to
shell with console on boards with this SoC
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 476 +++++++++++++++++++++++++++
1 file changed, 476 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8450.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
new file mode 100644
index 000000000000..96fbf4be3f89
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sm8450.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <76800000>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo780";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <274>;
+ exit-latency-us = <480>;
+ min-residency-us = <3934>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <327>;
+ exit-latency-us = <1502>;
+ min-residency-us = <4488>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-l3-off";
+ arm,psci-suspend-param = <0x4100c344>;
+ entry-latency-us = <584>;
+ exit-latency-us = <2332>;
+ min-residency-us = <6118>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-power-collapse";
+ arm,psci-suspend-param = <0x4100c344>;
+ entry-latency-us = <2893>;
+ exit-latency-us = <4023>;
+ min-residency-us = <9987>;
+ local-timer-stop;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm8450", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sm8450";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
+ };
+
+ qupv3_id_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x009c0000 0x0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm8450-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
+ <94 609 31>, <125 63 1>, <126 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ intc: interrupt-controller@17100000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+ reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
+ <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0x0 0x17420000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17421000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17421000 0x0 0x1000>,
+ <0x0 0x17422000 0x0 0x1000>;
+ };
+
+ frame@17423000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17423000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17425000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17427000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17429000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x1742b000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x1742d000 0x0 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17a00000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>,
+ <0x0 0x17a30000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm8450-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+};
--
2.31.1
Add tlmm node found in SM8450 SoC and uart pin configuration
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 96fbf4be3f89..fb93d53d3433 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -343,6 +343,8 @@ uart7: serial@99c000 {
reg = <0 0x0099c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -366,6 +368,32 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm8450-tlmm";
+ reg = <0 0x0f100000 0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 211>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_rx: qup-uart7-rx {
+ pins = "gpio26";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart7_tx: qup-uart7-tx {
+ pins = "gpio27";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
intc: interrupt-controller@17100000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.31.1
Add the reserved memory nodes for SM8450. This is based on the downstream
documentation.
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 221 +++++++++++++++++++++++++++
1 file changed, 221 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index fb93d53d3433..d9439c6ebfa2 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -310,6 +310,227 @@ CLUSTER_PD: cpu-cluster0 {
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_dt_log_mem: memory@80600000 {
+ reg = <0x0 0x80600000 0x0 0x40000>;
+ no-map;
+ };
+
+ xbl_ramdump_mem: memory@80640000 {
+ reg = <0x0 0x80640000 0x0 0x180000>;
+ no-map;
+ };
+
+ xbl_sc_mem: memory@807c0000 {
+ reg = <0x0 0x807c0000 0x0 0x40000>;
+ no-map;
+ };
+
+ aop_image_mem: memory@80800000 {
+ reg = <0x0 0x80800000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: memory@80860000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: memory@80880000 {
+ reg = <0x0 0x80880000 0x0 0x20000>;
+ no-map;
+ };
+
+ tme_crash_dump_mem: memory@808a0000 {
+ reg = <0x0 0x808a0000 0x0 0x40000>;
+ no-map;
+ };
+
+ tme_log_mem: memory@808e0000 {
+ reg = <0x0 0x808e0000 0x0 0x4000>;
+ no-map;
+ };
+
+ uefi_log_mem: memory@808e4000 {
+ reg = <0x0 0x808e4000 0x0 0x10000>;
+ no-map;
+ };
+
+ /* secdata region can be reused by apps */
+ smem: memory@80900000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ cpucp_fw_mem: memory@80b00000 {
+ reg = <0x0 0x80b00000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap: memory@80c00000 {
+ reg = <0x0 0x80c00000 0x0 0x4600000>;
+ no-map;
+ };
+
+ camera_mem: memory@85200000 {
+ reg = <0x0 0x85200000 0x0 0x500000>;
+ no-map;
+ };
+
+ video_mem: memory@85700000 {
+ reg = <0x0 0x85700000 0x0 0x700000>;
+ no-map;
+ };
+
+ adsp_mem: memory@85e00000 {
+ reg = <0x0 0x85e00000 0x0 0x2100000>;
+ no-map;
+ };
+
+ slpi_mem: memory@88000000 {
+ reg = <0x0 0x88000000 0x0 0x1900000>;
+ no-map;
+ };
+
+ cdsp_mem: memory@89900000 {
+ reg = <0x0 0x89900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@8b900000 {
+ reg = <0x0 0x8b900000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: memory@8b910000 {
+ reg = <0x0 0x8b910000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: memory@8b91a000 {
+ reg = <0x0 0x8b91a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: memory@8ba00000 {
+ reg = <0x0 0x8ba00000 0x0 0x180000>;
+ no-map;
+ };
+
+ /* First part of the "SPU secure shared memory" region */
+ spu_tz_shared_mem: memory@8bb80000 {
+ reg = <0x0 0x8bb80000 0x0 0x60000>;
+ no-map;
+ };
+
+ /* Second part of the "SPU secure shared memory" region */
+ spu_modem_shared_mem: memory@8bbe0000 {
+ reg = <0x0 0x8bbe0000 0x0 0x20000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8bc00000 {
+ reg = <0x0 0x8bc00000 0x0 0x13200000>;
+ no-map;
+ };
+
+ cvp_mem: memory@9ee00000 {
+ reg = <0x0 0x9ee00000 0x0 0x700000>;
+ no-map;
+ };
+
+ global_sync_mem: memory@a6f00000 {
+ reg = <0x0 0xa6f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ /* uefi region can be reused by APPS */
+
+ /* Linux kernel image is loaded at 0xa0000000 */
+
+ oem_vm_mem: memory@bb000000 {
+ reg = <0x0 0xbb000000 0x0 0x5000000>;
+ no-map;
+ };
+
+ mte_mem: memory@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x20000000>;
+ no-map;
+ };
+
+ qheebsp_reserved_mem: memory@e0000000 {
+ reg = <0x0 0xe0000000 0x0 0x600000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: memory@e0600000 {
+ reg = <0x0 0xe0600000 0x0 0x400000>;
+ no-map;
+ };
+
+ hyp_reserved_mem: memory@e0a00000 {
+ reg = <0x0 0xe0a00000 0x0 0x100000>;
+ no-map;
+ };
+
+ trust_ui_vm_mem: memory@e0b00000 {
+ reg = <0x0 0xe0b00000 0x0 0x4af3000>;
+ no-map;
+ };
+
+ trust_ui_vm_qrtr: memory@e55f3000 {
+ reg = <0x0 0xe55f3000 0x0 0x9000>;
+ no-map;
+ };
+
+ trust_ui_vm_vblk0_ring: memory@e55fc000 {
+ reg = <0x0 0xe55fc000 0x0 0x4000>;
+ no-map;
+ };
+
+ trust_ui_vm_swiotlb: memory@e5600000 {
+ reg = <0x0 0xe5600000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: memory@e8800000 {
+ reg = <0x0 0xe8800000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: memory@e8900000 {
+ reg = <0x0 0xe8900000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: memory@e9b00000 {
+ reg = <0x0 0xe9b00000 0x0 0x500000>;
+ no-map;
+ };
+
+ trusted_apps_mem: memory@ea000000 {
+ reg = <0x0 0xea000000 0x0 0x3900000>;
+ no-map;
+ };
+
+ trusted_apps_ext_mem: memory@ed900000 {
+ reg = <0x0 0xed900000 0x0 0x3b00000>;
+ no-map;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
--
2.31.1
Add the apps smmu node as found in the SM8450 SoC
Signed-off-by: Vinod Koul <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 103 +++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d9439c6ebfa2..d29680c405bf 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -615,6 +615,109 @@ qup_uart7_tx: qup-uart7-tx {
};
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17100000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.31.1
Add the RPMH regulators found in QRD-SM8450 platform
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 322 ++++++++++++++++++++++++
1 file changed, 322 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index caa8408b7cd1..26d2b5aa8dff 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8450.dtsi"
#include "pm8350.dtsi"
#include "pm8350b.dtsi"
@@ -21,6 +22,327 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ pm8350-rpmh-regulators {
+ compatible = "qcom,pm8350-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-s11-supply = <&vph_pwr>;
+ vdd-s12-supply = <&vph_pwr>;
+
+ vdd-l1-l4-supply = <&vreg_s11b_0p95>;
+ vdd-l2-l7-supply = <&vreg_bob>;
+ vdd-l3-l5-supply = <&vreg_bob>;
+ vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>;
+ vdd-l8-supply = <&vreg_s2h_0p95>;
+
+ vreg_s10b_1p8: smps10 {
+ regulator-name = "vreg_s10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_s11b_0p95: smps11 {
+ regulator-name = "vreg_s11b_0p95";
+ regulator-min-microvolt = <848000>;
+ regulator-max-microvolt = <1104000>;
+ };
+
+ vreg_s12b_1p25: smps12 {
+ regulator-name = "vreg_s12b_1p25";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1400000>;
+ };
+
+ vreg_l1b_0p91: ldo1 {
+ regulator-name = "vreg_l1b_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p07: ldo2 {
+ regulator-name = "vreg_l2b_3p07";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p9: ldo3 {
+ regulator-name = "vreg_l3b_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_0p88: ldo5 {
+ regulator-name = "vreg_l5b_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <888000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p5: ldo7 {
+ regulator-name = "vreg_l7b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8350c-rpmh-regulators {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l12-supply = <&vreg_bob>;
+ vdd-l2-l8-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+ vdd-l6-l9-l11-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_s1c_1p86: smps1 {
+ regulator-name = "vreg_s1c_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2024000>;
+ };
+
+ vreg_s10c_1p05: smps10 {
+ regulator-name = "vreg_s10c_1p05";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_3p0: ldo3 {
+ regulator-name = "vreg_l3c_3p0";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8: ldo4 {
+ regulator-name = "vreg_l4c_1p8";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-name = "vreg_l5c_1p8";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_1p8: ldo6 {
+ regulator-name = "vreg_l6c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-name = "vreg_l7c_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p8: ldo12 {
+ regulator-name = "vreg_l12c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1968000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_3p0: ldo13 {
+ regulator-name = "vreg_l13c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8450-rpmh-regulators {
+ compatible = "qcom,pm8450-rpmh-regulators";
+ qcom,pmic-id = "h";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vdd-l2-supply = <&vreg_bob>;
+ vdd-l3-supply = <&vreg_bob>;
+ vdd-l4-supply = <&vreg_bob>;
+
+ vreg_s2h_0p95: smps2 {
+ regulator-name = "vreg_s2h_0p95";
+ regulator-min-microvolt = <848000>;
+ regulator-max-microvolt = <1104000>;
+ };
+
+ vreg_s3h_0p5: smps3 {
+ regulator-name = "vreg_s3h_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <500000>;
+ };
+
+ vreg_l2h_0p91: ldo2 {
+ regulator-name = "vreg_l2h_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3h_0p91: ldo3 {
+ regulator-name = "vreg_l3h_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ };
+
+ pmr735a-rpmh-regulators {
+ compatible = "qcom,pmr735a-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+
+ vdd-l1-l2-supply = <&vreg_s2e_0p85>;
+ vdd-l3-supply = <&vreg_s1e_1p25>;
+ vdd-l4-supply = <&vreg_s1c_1p86>;
+ vdd-l5-l6-supply = <&vreg_s1c_1p86>;
+ vdd-l7-bob-supply = <&vreg_bob>;
+
+ vreg_s1e_1p25: smps1 {
+ regulator-name = "vreg_s1e_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1296000>;
+ };
+
+ vreg_s2e_0p85: smps2 {
+ regulator-name = "vreg_s2e_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1040000>;
+ };
+
+ vreg_l1e_0p8: ldo1 {
+ regulator-name = "vreg_l1e_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l4e_1p7: ldo4 {
+ regulator-name = "vreg_l4e_1p7";
+ regulator-min-microvolt = <1776000>;
+ regulator-max-microvolt = <1776000>;
+ };
+
+ vreg_l5e_0p88: ldo5 {
+ regulator-name = "vreg_l5e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ };
+
+ vreg_l6e_1p2: ldo6 {
+ regulator-name = "vreg_l6e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
};
&qupv3_id_0 {
--
2.31.1
Add DTS for Qualcomm QRD platform which uses SM8450 SoC. This also
includes the pmic files and marks the tlmm reserved pins
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 36 +++++++++++++++++++++++++
2 files changed, 37 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8450-qrd.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6b816eb33309..9b37261484cf 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -107,3 +107,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
new file mode 100644
index 000000000000..caa8408b7cd1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include "sm8450.dtsi"
+#include "pm8350.dtsi"
+#include "pm8350b.dtsi"
+#include "pmr735b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8450 QRD";
+ compatible = "qcom,sm8450-qrd", "qcom,sm8450";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <28 4>, <36 4>;
+};
+
+&uart7 {
+ status = "okay";
+};
--
2.31.1
Add the UFS and QMP PHY node for SM8450 SoC
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 72 ++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d29680c405bf..9556d2fc46e0 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -815,6 +815,78 @@ rpmhcc: clock-controller {
clocks = <&xo_board>;
};
};
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0xe0 0x0>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm8450-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0xe10>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "ref", "ref_aux", "qref";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_0_CLKREF_EN>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: lanes@1d87400 {
+ reg = <0 0x01d87400 0 0x108>,
+ <0 0x01d87600 0 0x1e0>,
+ <0 0x01d87c00 0 0x1dc>,
+ <0 0x01d87800 0 0x108>,
+ <0 0x01d87a00 0 0x1e0>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ };
+ };
};
timer {
--
2.31.1
Enable the UFS and phy node and add the regulators used by them.
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index 26d2b5aa8dff..6cf584ebf1ed 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -356,3 +356,23 @@ &tlmm {
&uart7 {
status = "okay";
};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b_2p5>;
+ vcc-max-microamp = <1100000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <1200000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5b_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+ vdda-max-microamp = <173000>;
+ vdda-pll-max-microamp = <24900>;
+};
--
2.31.1
And the various interconnect nodes found in SM8450 SoC and use it for
UFS controller.
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 80 ++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 9556d2fc46e0..f75de777f6ea 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -573,6 +574,61 @@ uart7: serial@99c000 {
};
};
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm8450-config-noc";
+ reg = <0 0x01500000 0 0x1c000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect@1580000 {
+ compatible = "qcom,sm8450-mc-virt";
+ reg = <0 0x01580000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,sm8450-system-noc";
+ reg = <0 0x01680000 0 0x1e200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_noc: interconnect@16c0000 {
+ compatible = "qcom,sm8450-pcie-anoc";
+ reg = <0 0x016c0000 0 0xe280>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sm8450-aggre1-noc";
+ reg = <0 0x016e0000 0 0x1c080>;
+ #interconnect-cells = <1>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,sm8450-aggre2-noc";
+ reg = <0 0x01700000 0 0x31080>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ mmss_noc: interconnect@1740000 {
+ compatible = "qcom,sm8450-mmss-noc";
+ reg = <0 0x01740000 0 0x1f080>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -816,6 +872,13 @@ rpmhcc: clock-controller {
};
};
+ gem_noc: interconnect@19100000 {
+ compatible = "qcom,sm8450-gem-noc";
+ reg = <0 0x19100000 0 0xbb800>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -832,6 +895,9 @@ ufs_mem_hc: ufshc@1d84000 {
iommus = <&apps_smmu 0xe0 0x0>;
+ interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
clock-names =
"core_clk",
"bus_aggr_clk",
@@ -887,6 +953,20 @@ ufs_mem_phy_lanes: lanes@1d87400 {
#clock-cells = <0>;
};
};
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,sm8450-nsp-noc";
+ reg = <0 0x320c0000 0 0x10000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,sm8450-lpass-ag-noc";
+ reg = <0 0x3c40000 0 0x17200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
};
timer {
--
2.31.1
Add the spmi bus as found in the SM8450 SoC
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index f75de777f6ea..b80e34fd3fe1 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ spmi_bus: spmi@c42d000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x00003000>,
+ <0x0 0x0c500000 0x0 0x00400000>,
+ <0x0 0x0c440000 0x0 0x00080000>,
+ <0x0 0x0c4c0000 0x0 0x00010000>,
+ <0x0 0x0c42d000 0x0 0x00010000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sm8450-tlmm";
reg = <0 0x0f100000 0 0x300000>;
--
2.31.1
From: Dmitry Baryshkov <[email protected]>
This adds RPMH power domain found in SM8450 SoC
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b80e34fd3fe1..f303e12dbfb7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -888,6 +889,57 @@ rpmhcc: clock-controller {
clock-names = "xo";
clocks = <&xo_board>;
};
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sm8450-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
};
gem_noc: interconnect@19100000 {
--
2.31.1
From: Vladimir Zapolskiy <[email protected]>
The change adds a description of a SM8450 cpufreq-epss controller and
references to it from CPU nodes.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index f303e12dbfb7..94bc8b352547 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -62,6 +63,7 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -76,6 +78,7 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -90,6 +93,7 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -104,6 +108,7 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -118,6 +123,7 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -133,6 +139,7 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -147,6 +154,7 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -942,6 +950,21 @@ rpmhpd_opp_turbo_l1: opp10 {
};
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x17d91000 0 0x1000>,
+ <0 0x17d92000 0 0x1000>,
+ <0 0x17d93000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
+ #freq-domain-cells = <1>;
+ };
+
gem_noc: interconnect@19100000 {
compatible = "qcom,sm8450-gem-noc";
reg = <0 0x19100000 0 0xbb800>;
--
2.31.1
From: Dmitry Baryshkov <[email protected]>
Add device tree nodes for two i2c blocks: i2c13 and i2c14.
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 94bc8b352547..c214ab89b44c 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -583,6 +583,44 @@ uart7: serial@99c000 {
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
config_noc: interconnect@1500000 {
compatible = "qcom,sm8450-config-noc";
reg = <0 0x01500000 0 0x1c000>;
@@ -683,6 +721,20 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 211>;
wakeup-parent = <&pdc>;
+ qup_i2c13_data_clk: qup-i2c13-data-clk {
+ pins = "gpio48", "gpio49";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk {
+ pins = "gpio52", "gpio53";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
qup_uart7_rx: qup-uart7-rx {
pins = "gpio26";
function = "qup7";
--
2.31.1
On 09/12/2021 11:35, Vinod Koul wrote:
> And the various interconnect nodes found in SM8450 SoC and use it for
> UFS controller.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 80 ++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 09/12/2021 11:35, Vinod Koul wrote:
> From: Dmitry Baryshkov <[email protected]>
>
> Add device tree nodes for two i2c blocks: i2c13 and i2c14.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
Hi Vinod,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.16-rc4]
[cannot apply to next-20211208]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vinod-Koul/arm64-dts-qcom-Add-support-for-SM8450-SoC-and-QRD-board/20211209-183713
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r032-20211207 (https://download.01.org/0day-ci/archive/20211210/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/636d2456715b3aba9cf1fa47931c6e381ca62e00
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Vinod-Koul/arm64-dts-qcom-Add-support-for-SM8450-SoC-and-QRD-board/20211209-183713
git checkout 636d2456715b3aba9cf1fa47931c6e381ca62e00
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/qcom/sm8450-qrd.dts:8:
>> arch/arm64/boot/dts/qcom/sm8450.dtsi:7:10: fatal error: dt-bindings/clock/qcom,gcc-sm8450.h: No such file or directory
7 | #include <dt-bindings/clock/qcom,gcc-sm8450.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +7 arch/arm64/boot/dts/qcom/sm8450.dtsi
244741584ca1ceb Vinod Koul 2021-12-09 @7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
244741584ca1ceb Vinod Koul 2021-12-09 8 #include <dt-bindings/clock/qcom,rpmh.h>
244741584ca1ceb Vinod Koul 2021-12-09 9 #include <dt-bindings/gpio/gpio.h>
244741584ca1ceb Vinod Koul 2021-12-09 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
244741584ca1ceb Vinod Koul 2021-12-09 11
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Vinod,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.16-rc4]
[cannot apply to next-20211208]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vinod-Koul/arm64-dts-qcom-Add-support-for-SM8450-SoC-and-QRD-board/20211209-183713
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r022-20211207 (https://download.01.org/0day-ci/archive/20211210/[email protected]/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 097a1cb1d5ebb3a0ec4bcaed8ba3ff6a8e33c00a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/0day-ci/linux/commit/636d2456715b3aba9cf1fa47931c6e381ca62e00
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Vinod-Koul/arm64-dts-qcom-Add-support-for-SM8450-SoC-and-QRD-board/20211209-183713
git checkout 636d2456715b3aba9cf1fa47931c6e381ca62e00
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/qcom/sm8450-qrd.dts:8:
>> arch/arm64/boot/dts/qcom/sm8450.dtsi:7:10: fatal error: 'dt-bindings/clock/qcom,gcc-sm8450.h' file not found
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +7 arch/arm64/boot/dts/qcom/sm8450.dtsi
244741584ca1ceb Vinod Koul 2021-12-09 @7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
244741584ca1ceb Vinod Koul 2021-12-09 8 #include <dt-bindings/clock/qcom,rpmh.h>
244741584ca1ceb Vinod Koul 2021-12-09 9 #include <dt-bindings/gpio/gpio.h>
244741584ca1ceb Vinod Koul 2021-12-09 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
244741584ca1ceb Vinod Koul 2021-12-09 11
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Vinod,
On 9.12.21 12:35, Vinod Koul wrote:
> And the various interconnect nodes found in SM8450 SoC and use it for
> UFS controller.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 80 ++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 9556d2fc46e0..f75de777f6ea 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/clock/qcom,gcc-sm8450.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,sm8450.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> / {
> @@ -573,6 +574,61 @@ uart7: serial@99c000 {
> };
> };
>
> + config_noc: interconnect@1500000 {
> + compatible = "qcom,sm8450-config-noc";
> + reg = <0 0x01500000 0 0x1c000>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mc_virt: interconnect@1580000 {
> + compatible = "qcom,sm8450-mc-virt";
> + reg = <0 0x01580000 0 0x1000>;
Is there really a register space for this noc?
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + system_noc: interconnect@1680000 {
> + compatible = "qcom,sm8450-system-noc";
> + reg = <0 0x01680000 0 0x1e200>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + pcie_noc: interconnect@16c0000 {
> + compatible = "qcom,sm8450-pcie-anoc";
> + reg = <0 0x016c0000 0 0xe280>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre1_noc: interconnect@16e0000 {
> + compatible = "qcom,sm8450-aggre1-noc";
> + reg = <0 0x016e0000 0 0x1c080>;
> + #interconnect-cells = <1>;
> + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre2_noc: interconnect@1700000 {
> + compatible = "qcom,sm8450-aggre2-noc";
> + reg = <0 0x01700000 0 0x31080>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&rpmhcc RPMH_IPA_CLK>;
> + };
> +
> + mmss_noc: interconnect@1740000 {
> + compatible = "qcom,sm8450-mmss-noc";
> + reg = <0 0x01740000 0 0x1f080>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x40000>;
> @@ -816,6 +872,13 @@ rpmhcc: clock-controller {
> };
> };
>
> + gem_noc: interconnect@19100000 {
> + compatible = "qcom,sm8450-gem-noc";
> + reg = <0 0x19100000 0 0xbb800>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> @@ -832,6 +895,9 @@ ufs_mem_hc: ufshc@1d84000 {
>
> iommus = <&apps_smmu 0xe0 0x0>;
>
> + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
> + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
> + interconnect-names = "ufs-ddr", "cpu-ufs";
> clock-names =
> "core_clk",
> "bus_aggr_clk",
> @@ -887,6 +953,20 @@ ufs_mem_phy_lanes: lanes@1d87400 {
> #clock-cells = <0>;
> };
> };
> +
> + nsp_noc: interconnect@320c0000 {
> + compatible = "qcom,sm8450-nsp-noc";
> + reg = <0 0x320c0000 0 0x10000>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + lpass_ag_noc: interconnect@3c40000 {
Nit: This should move up, if we want to order them by node address.
> + compatible = "qcom,sm8450-lpass-ag-noc";
> + reg = <0 0x3c40000 0 0x17200>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> };
I don't see a DT node for clk_virt, are you planning to add this later?
Thanks,
Georgi
On 09/12/2021 05:35, Vinod Koul wrote:
> Add the spmi bus as found in the SM8450 SoC
>
> Signed-off-by: Vinod Koul <[email protected]>
> Reviewed-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index f75de777f6ea..b80e34fd3fe1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
> interrupt-controller;
> };
>
> + spmi_bus: spmi@c42d000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0 0x0c400000 0x0 0x00003000>,
> + <0x0 0x0c500000 0x0 0x00400000>,
> + <0x0 0x0c440000 0x0 0x00080000>,
> + <0x0 0x0c4c0000 0x0 0x00010000>,
> + <0x0 0x0c42d000 0x0 0x00010000>;
This is a patch from December 2021. Is there anything blocking it from
being merged?
The same applies to several other patches here.
Best regards,
Krzysztof
On 2022-10-24 16:56, Krzysztof Kozlowski wrote:
> On 09/12/2021 05:35, Vinod Koul wrote:
>> Add the spmi bus as found in the SM8450 SoC
>>
>> Signed-off-by: Vinod Koul <[email protected]>
>> Reviewed-by: Konrad Dybcio <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index f75de777f6ea..b80e34fd3fe1 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>> interrupt-controller;
>> };
>>
>> + spmi_bus: spmi@c42d000 {
>> + compatible = "qcom,spmi-pmic-arb";
>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>> + <0x0 0x0c500000 0x0 0x00400000>,
>> + <0x0 0x0c440000 0x0 0x00080000>,
>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>> + <0x0 0x0c42d000 0x0 0x00010000>;
>
> This is a patch from December 2021. Is there anything blocking it from
> being merged?
I think it depended on a series of changes to the driver, as 8450 has a
newer SPMI ver
Konrad
>
> The same applies to several other patches here.
>
> Best regards,
> Krzysztof
On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
> On 09/12/2021 05:35, Vinod Koul wrote:
>> Add the spmi bus as found in the SM8450 SoC
>>
>> Signed-off-by: Vinod Koul <[email protected]>
>> Reviewed-by: Konrad Dybcio <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index f75de777f6ea..b80e34fd3fe1 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>> interrupt-controller;
>> };
>>
>> + spmi_bus: spmi@c42d000 {
>> + compatible = "qcom,spmi-pmic-arb";
>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>> + <0x0 0x0c500000 0x0 0x00400000>,
>> + <0x0 0x0c440000 0x0 0x00080000>,
>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>> + <0x0 0x0c42d000 0x0 0x00010000>;
>
> This is a patch from December 2021. Is there anything blocking it from
> being merged?
>
> The same applies to several other patches here.
As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
for the PMIC on the SM8450 platform. Thus we also can not merge the DT
parts.
--
With best wishes
Dmitry
On 24/10/2022 12:45, Dmitry Baryshkov wrote:
> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
>> On 09/12/2021 05:35, Vinod Koul wrote:
>>> Add the spmi bus as found in the SM8450 SoC
>>>
>>> Signed-off-by: Vinod Koul <[email protected]>
>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> index f75de777f6ea..b80e34fd3fe1 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>>> interrupt-controller;
>>> };
>>>
>>> + spmi_bus: spmi@c42d000 {
>>> + compatible = "qcom,spmi-pmic-arb";
>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>>> + <0x0 0x0c500000 0x0 0x00400000>,
>>> + <0x0 0x0c440000 0x0 0x00080000>,
>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>>> + <0x0 0x0c42d000 0x0 0x00010000>;
>>
>> This is a patch from December 2021. Is there anything blocking it from
>> being merged?
>>
>> The same applies to several other patches here.
>
> As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
> for the PMIC on the SM8450 platform. Thus we also can not merge the DT
> parts.
Why we cannot merge DTS? How is DTS with new nodes depending on any
driver changes?
Just like I replied to Konrad - if that's true, bindings are simply
wrong and should be fixed.
Best regards,
Krzysztof
On 24/10/2022 19:46, Krzysztof Kozlowski wrote:
> On 24/10/2022 12:45, Dmitry Baryshkov wrote:
>> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
>>> On 09/12/2021 05:35, Vinod Koul wrote:
>>>> Add the spmi bus as found in the SM8450 SoC
>>>>
>>>> Signed-off-by: Vinod Koul <[email protected]>
>>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>>>> 1 file changed, 18 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>> index f75de777f6ea..b80e34fd3fe1 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>>>> interrupt-controller;
>>>> };
>>>>
>>>> + spmi_bus: spmi@c42d000 {
>>>> + compatible = "qcom,spmi-pmic-arb";
>>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>>>> + <0x0 0x0c500000 0x0 0x00400000>,
>>>> + <0x0 0x0c440000 0x0 0x00080000>,
>>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>>>> + <0x0 0x0c42d000 0x0 0x00010000>;
>>>
>>> This is a patch from December 2021. Is there anything blocking it from
>>> being merged?
>>>
>>> The same applies to several other patches here.
>>
>> As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
>> for the PMIC on the SM8450 platform. Thus we also can not merge the DT
>> parts.
>
> Why we cannot merge DTS? How is DTS with new nodes depending on any
> driver changes?
In this particular case, there was an open question, what should be the
bindings for the PMIC ARB v7.
>
> Just like I replied to Konrad - if that's true, bindings are simply
> wrong and should be fixed.
Maybe I missed the reply. Which email are you referring to?
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
On 24/10/2022 11:06, [email protected] wrote:
> On 2022-10-24 16:56, Krzysztof Kozlowski wrote:
>> On 09/12/2021 05:35, Vinod Koul wrote:
>>> Add the spmi bus as found in the SM8450 SoC
>>>
>>> Signed-off-by: Vinod Koul <[email protected]>
>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> index f75de777f6ea..b80e34fd3fe1 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>>> interrupt-controller;
>>> };
>>>
>>> + spmi_bus: spmi@c42d000 {
>>> + compatible = "qcom,spmi-pmic-arb";
>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>>> + <0x0 0x0c500000 0x0 0x00400000>,
>>> + <0x0 0x0c440000 0x0 0x00080000>,
>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>>> + <0x0 0x0c42d000 0x0 0x00010000>;
>>
>> This is a patch from December 2021. Is there anything blocking it from
>> being merged?
> I think it depended on a series of changes to the driver, as 8450 has a
> newer SPMI ver
>
If the new device node in DTS (for new hardware) depends on driver
changes, then something here is completely broken. Probably in the
bindings for Qualcomm SPMI PMIC.
I expect adding DTS independently of driver changes. It anyway goes
always via separate branches.
Best regards,
Krzysztof
On Mon, 24 Oct 2022 at 21:56, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 24/10/2022 12:48, Dmitry Baryshkov wrote:
> > On 24/10/2022 19:46, Krzysztof Kozlowski wrote:
> >> On 24/10/2022 12:45, Dmitry Baryshkov wrote:
> >>> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
> >>>> On 09/12/2021 05:35, Vinod Koul wrote:
> >>>>> Add the spmi bus as found in the SM8450 SoC
> >>>>>
> >>>>> Signed-off-by: Vinod Koul <[email protected]>
> >>>>> Reviewed-by: Konrad Dybcio <[email protected]>
> >>>>> ---
> >>>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
> >>>>> 1 file changed, 18 insertions(+)
> >>>>>
> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> >>>>> index f75de777f6ea..b80e34fd3fe1 100644
> >>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> >>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> >>>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
> >>>>> interrupt-controller;
> >>>>> };
> >>>>>
> >>>>> + spmi_bus: spmi@c42d000 {
> >>>>> + compatible = "qcom,spmi-pmic-arb";
> >>>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
> >>>>> + <0x0 0x0c500000 0x0 0x00400000>,
> >>>>> + <0x0 0x0c440000 0x0 0x00080000>,
> >>>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
> >>>>> + <0x0 0x0c42d000 0x0 0x00010000>;
> >>>>
> >>>> This is a patch from December 2021. Is there anything blocking it from
> >>>> being merged?
> >>>>
> >>>> The same applies to several other patches here.
> >>>
> >>> As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
> >>> for the PMIC on the SM8450 platform. Thus we also can not merge the DT
> >>> parts.
> >>
> >> Why we cannot merge DTS? How is DTS with new nodes depending on any
> >> driver changes?
> >
> > In this particular case, there was an open question, what should be the
> > bindings for the PMIC ARB v7.
>
> Ah, so it is about PMIC ARB v7 bindings? Then it's reasonable to wait
> with this one. I just had an impression that it's about driver changes...
Yes, it's about binding. Thus we have been waiting for quite some time.
>
> >
> >>
> >> Just like I replied to Konrad - if that's true, bindings are simply
> >> wrong and should be fixed.
> >
> > Maybe I missed the reply. Which email are you referring to?
>
> I meant about this one:
>
> https://lore.kernel.org/linux-arm-msm/[email protected]/T/#m50f4c72775492046f9b0a172e974cab83563af3c
Ack, for some reason I got it later than the previous one.
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
On 24/10/2022 12:48, Dmitry Baryshkov wrote:
> On 24/10/2022 19:46, Krzysztof Kozlowski wrote:
>> On 24/10/2022 12:45, Dmitry Baryshkov wrote:
>>> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
>>>> On 09/12/2021 05:35, Vinod Koul wrote:
>>>>> Add the spmi bus as found in the SM8450 SoC
>>>>>
>>>>> Signed-off-by: Vinod Koul <[email protected]>
>>>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>>>>> 1 file changed, 18 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>> index f75de777f6ea..b80e34fd3fe1 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>>>>> interrupt-controller;
>>>>> };
>>>>>
>>>>> + spmi_bus: spmi@c42d000 {
>>>>> + compatible = "qcom,spmi-pmic-arb";
>>>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>>>>> + <0x0 0x0c500000 0x0 0x00400000>,
>>>>> + <0x0 0x0c440000 0x0 0x00080000>,
>>>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>>>>> + <0x0 0x0c42d000 0x0 0x00010000>;
>>>>
>>>> This is a patch from December 2021. Is there anything blocking it from
>>>> being merged?
>>>>
>>>> The same applies to several other patches here.
>>>
>>> As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
>>> for the PMIC on the SM8450 platform. Thus we also can not merge the DT
>>> parts.
>>
>> Why we cannot merge DTS? How is DTS with new nodes depending on any
>> driver changes?
>
> In this particular case, there was an open question, what should be the
> bindings for the PMIC ARB v7.
Ah, so it is about PMIC ARB v7 bindings? Then it's reasonable to wait
with this one. I just had an impression that it's about driver changes...
>
>>
>> Just like I replied to Konrad - if that's true, bindings are simply
>> wrong and should be fixed.
>
> Maybe I missed the reply. Which email are you referring to?
I meant about this one:
https://lore.kernel.org/linux-arm-msm/[email protected]/T/#m50f4c72775492046f9b0a172e974cab83563af3c
Best regards,
Krzysztof
On 24-10-22, 21:58, Dmitry Baryshkov wrote:
> On Mon, 24 Oct 2022 at 21:56, Krzysztof Kozlowski
> <[email protected]> wrote:
> >
> > On 24/10/2022 12:48, Dmitry Baryshkov wrote:
> > > On 24/10/2022 19:46, Krzysztof Kozlowski wrote:
> > >> On 24/10/2022 12:45, Dmitry Baryshkov wrote:
> > >>> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
> > >>>> On 09/12/2021 05:35, Vinod Koul wrote:
> > >>>>> Add the spmi bus as found in the SM8450 SoC
> > >>>>>
> > >>>>> Signed-off-by: Vinod Koul <[email protected]>
> > >>>>> Reviewed-by: Konrad Dybcio <[email protected]>
> > >>>>> ---
> > >>>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
> > >>>>> 1 file changed, 18 insertions(+)
> > >>>>>
> > >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > >>>>> index f75de777f6ea..b80e34fd3fe1 100644
> > >>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > >>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > >>>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
> > >>>>> interrupt-controller;
> > >>>>> };
> > >>>>>
> > >>>>> + spmi_bus: spmi@c42d000 {
> > >>>>> + compatible = "qcom,spmi-pmic-arb";
> > >>>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
> > >>>>> + <0x0 0x0c500000 0x0 0x00400000>,
> > >>>>> + <0x0 0x0c440000 0x0 0x00080000>,
> > >>>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
> > >>>>> + <0x0 0x0c42d000 0x0 0x00010000>;
> > >>>>
> > >>>> This is a patch from December 2021. Is there anything blocking it from
> > >>>> being merged?
> > >>>>
> > >>>> The same applies to several other patches here.
> > >>>
> > >>> As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
> > >>> for the PMIC on the SM8450 platform. Thus we also can not merge the DT
> > >>> parts.
> > >>
> > >> Why we cannot merge DTS? How is DTS with new nodes depending on any
> > >> driver changes?
> > >
> > > In this particular case, there was an open question, what should be the
> > > bindings for the PMIC ARB v7.
> >
> > Ah, so it is about PMIC ARB v7 bindings? Then it's reasonable to wait
> > with this one. I just had an impression that it's about driver changes...
>
> Yes, it's about binding. Thus we have been waiting for quite some time.
Yes sadly Steven has stopped responding to emails or IRC.. I am not
sure whats going on!
Even the SPMI tree is not being actively maintained with only few
patches which were picked in last cycle since this year!
--
~Vinod
On 26/10/2022 07:33, Vinod Koul wrote:
> On 24-10-22, 21:58, Dmitry Baryshkov wrote:
>> On Mon, 24 Oct 2022 at 21:56, Krzysztof Kozlowski
>> <[email protected]> wrote:
>>>
>>> On 24/10/2022 12:48, Dmitry Baryshkov wrote:
>>>> On 24/10/2022 19:46, Krzysztof Kozlowski wrote:
>>>>> On 24/10/2022 12:45, Dmitry Baryshkov wrote:
>>>>>> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
>>>>>>> On 09/12/2021 05:35, Vinod Koul wrote:
>>>>>>>> Add the spmi bus as found in the SM8450 SoC
>>>>>>>>
>>>>>>>> Signed-off-by: Vinod Koul <[email protected]>
>>>>>>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>>>>>>> ---
>>>>>>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>>>>>>>> 1 file changed, 18 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>> index f75de777f6ea..b80e34fd3fe1 100644
>>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>>>>>>>> interrupt-controller;
>>>>>>>> };
>>>>>>>>
>>>>>>>> + spmi_bus: spmi@c42d000 {
>>>>>>>> + compatible = "qcom,spmi-pmic-arb";
>>>>>>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>>>>>>>> + <0x0 0x0c500000 0x0 0x00400000>,
>>>>>>>> + <0x0 0x0c440000 0x0 0x00080000>,
>>>>>>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>>>>>>>> + <0x0 0x0c42d000 0x0 0x00010000>;
>>>>>>>
>>>>>>> This is a patch from December 2021. Is there anything blocking it from
>>>>>>> being merged?
>>>>>>>
>>>>>>> The same applies to several other patches here.
>>>>>>
>>>>>> As far as I know, Stephen still didn't pick up the spmi-pmic-arb support
>>>>>> for the PMIC on the SM8450 platform. Thus we also can not merge the DT
>>>>>> parts.
>>>>>
>>>>> Why we cannot merge DTS? How is DTS with new nodes depending on any
>>>>> driver changes?
>>>>
>>>> In this particular case, there was an open question, what should be the
>>>> bindings for the PMIC ARB v7.
>>>
>>> Ah, so it is about PMIC ARB v7 bindings? Then it's reasonable to wait
>>> with this one. I just had an impression that it's about driver changes...
>>
>> Yes, it's about binding. Thus we have been waiting for quite some time.
>
> Yes sadly Steven has stopped responding to emails or IRC.. I am not
> sure whats going on!
>
> Even the SPMI tree is not being actively maintained with only few
> patches which were picked in last cycle since this year!
It's in -next now and 8450 boots and works fine. If the binding
situation has been resolved, I say merge this ASAP! :)
Konrad
>
On 17/11/2022 15:57, Konrad Dybcio wrote:
>
>
> On 26/10/2022 07:33, Vinod Koul wrote:
>> On 24-10-22, 21:58, Dmitry Baryshkov wrote:
>>> On Mon, 24 Oct 2022 at 21:56, Krzysztof Kozlowski
>>> <[email protected]> wrote:
>>>>
>>>> On 24/10/2022 12:48, Dmitry Baryshkov wrote:
>>>>> On 24/10/2022 19:46, Krzysztof Kozlowski wrote:
>>>>>> On 24/10/2022 12:45, Dmitry Baryshkov wrote:
>>>>>>> On 24/10/2022 17:56, Krzysztof Kozlowski wrote:
>>>>>>>> On 09/12/2021 05:35, Vinod Koul wrote:
>>>>>>>>> Add the spmi bus as found in the SM8450 SoC
>>>>>>>>>
>>>>>>>>> Signed-off-by: Vinod Koul <[email protected]>
>>>>>>>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>>>>>>>> ---
>>>>>>>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++
>>>>>>>>> 1 file changed, 18 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>>> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>>> index f75de777f6ea..b80e34fd3fe1 100644
>>>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>>>>>> @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 {
>>>>>>>>> interrupt-controller;
>>>>>>>>> };
>>>>>>>>>
>>>>>>>>> + spmi_bus: spmi@c42d000 {
>>>>>>>>> + compatible = "qcom,spmi-pmic-arb";
>>>>>>>>> + reg = <0x0 0x0c400000 0x0 0x00003000>,
>>>>>>>>> + <0x0 0x0c500000 0x0 0x00400000>,
>>>>>>>>> + <0x0 0x0c440000 0x0 0x00080000>,
>>>>>>>>> + <0x0 0x0c4c0000 0x0 0x00010000>,
>>>>>>>>> + <0x0 0x0c42d000 0x0 0x00010000>;
>>>>>>>>
>>>>>>>> This is a patch from December 2021. Is there anything blocking
>>>>>>>> it from
>>>>>>>> being merged?
>>>>>>>>
>>>>>>>> The same applies to several other patches here.
>>>>>>>
>>>>>>> As far as I know, Stephen still didn't pick up the spmi-pmic-arb
>>>>>>> support
>>>>>>> for the PMIC on the SM8450 platform. Thus we also can not merge
>>>>>>> the DT
>>>>>>> parts.
>>>>>>
>>>>>> Why we cannot merge DTS? How is DTS with new nodes depending on any
>>>>>> driver changes?
>>>>>
>>>>> In this particular case, there was an open question, what should be
>>>>> the
>>>>> bindings for the PMIC ARB v7.
>>>>
>>>> Ah, so it is about PMIC ARB v7 bindings? Then it's reasonable to wait
>>>> with this one. I just had an impression that it's about driver
>>>> changes...
>>>
>>> Yes, it's about binding. Thus we have been waiting for quite some time.
>>
>> Yes sadly Steven has stopped responding to emails or IRC.. I am not
>> sure whats going on!
>>
>> Even the SPMI tree is not being actively maintained with only few
>> patches which were picked in last cycle since this year!
> It's in -next now and 8450 boots and works fine. If the binding
> situation has been resolved, I say merge this ASAP! :)
>
> Konrad
With a small nit: it needs to be rebased, and should come between
aoss_qmp: and ipcc: address-wise (ipcc wasn't around a year ago in this
DT, it seems). Also most (all?) other nodes in the DT use reg = <0 [..]>
instead of reg = <0x0 [..]> so that could be fixed up as well.
Konrad
>>