On 2017/11/16 23:23, Sudeep Holla wrote:
>
>
> On 16/11/17 12:58, Tan Xiaojun wrote:
>> Since commit dfea747d2aba ("drivers: base: cacheinfo: support DT
>> overrides for cache properties"), we can set the correct cacheinfo
>> via DT. But the cache type can't be set in the same way.
>>
>> I found this may be a problem in recent tests. I tested L3 cache
>> node setting in DT in Hisilicon D03/D05 board. And I got cacheinfo
>> via sysfs below:
>
> I assume L3 is outer non-architected system cache.
>
Yes.
>>
>> $ cat /sys/devices/system/cpu/cpu*/cache/index3/
>> allocation_policy level power/
>> shared_cpu_map uevent write_policy
>> coherency_line_size number_of_sets shared_cpu_list
>> size ways_of_associativity
>>
>> This is incomplete, no type file to display type info. Because L3
>> cache is uncore, we can't get correct type info from system
>> register, and will get a default type "CACHE_TYPE_NOCACHE". Then
>> use "lscpu" will print an error like below:
>>
>> $ lscpu
>> lscpu: cannot open /sys/devices/system/cpu/cpu0/cache/index3/type:
>> No such file or directory
>>
>> So I think maybe we can set correct cache type via DT too.
>>
>> Signed-off-by: Tan Xiaojun <[email protected]>
>> ---
>> drivers/base/cacheinfo.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
>> index eb3af27..3e650dc 100644
>> --- a/drivers/base/cacheinfo.c
>> +++ b/drivers/base/cacheinfo.c
>> @@ -122,6 +122,15 @@ static inline int get_cacheinfo_idx(enum cache_type type)
>> return type;
>> }
>>
>> +static void cache_type(struct cacheinfo *this_leaf)
>> +{
>> + const __be32 *cache_type;
>> +
>> + cache_type = of_get_property(this_leaf->of_node, "type", NULL);
>
> NACK for this:
>
> 1. We don't have any DT binding for the "type"
> 2. Even if we had, we will never have such a binding that magical
> returns the enum used in Linux implementation. That's not how DT
> bindings are designed.
>
> Please refer ePAPR or Devicetree Specification Release 0.1 from
> devicetree.org, we have cache-unified boolean for type.
>
> Let me know if the below patch works for you, I will submit it
> preferably with your tested-by.
>
> Regards,
> Sudeep
>
OK. That's fine. I will test this.
By the way, Arm64 tend to use acpi way to boot now. Is there some
suitable solution for acpi?
Thanks.
Xiaojun.
> -->8
>
> diff --git i/drivers/base/cacheinfo.c w/drivers/base/cacheinfo.c
> index eb3af2739537..07532d83be0b 100644
> --- i/drivers/base/cacheinfo.c
> +++ w/drivers/base/cacheinfo.c
> @@ -186,6 +186,11 @@ static void cache_associativity(struct cacheinfo
> *this_leaf)
> this_leaf->ways_of_associativity = (size / nr_sets) /
> line_size;
> }
>
> +static bool cache_node_is_unified(struct cacheinfo *this_leaf)
> +{
> + return of_property_read_bool(this_leaf->of_node, "cache-unified");
> +}
> +
> static void cache_of_override_properties(unsigned int cpu)
> {
> int index;
> @@ -194,6 +199,14 @@ static void cache_of_override_properties(unsigned
> int cpu)
>
> for (index = 0; index < cache_leaves(cpu); index++) {
> this_leaf = this_cpu_ci->info_list + index;
> + /*
> + * init_cache_level must setup the cache level correctly
> + * overriding the architecturally specified levels, so
> + * if type is NONE at this stage, it should be unified
> + */
> + if (this_leaf->type == CACHE_TYPE_NOCACHE &&
> + cache_node_is_unified(this_leaf))
> + this_leaf->type = CACHE_TYPE_UNIFIED;
> cache_size(this_leaf);
> cache_get_line_size(this_leaf);
> cache_nr_sets(this_leaf);
>
>
> .
>
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