Hi guys,
> -----Original Message-----
> From: James Morse <[email protected]>
> Sent: Wednesday, February 27, 2019 3:44 AM
> To: [email protected]; [email protected]
> Cc: [email protected]; Catalin Marinas
> <[email protected]>; Mark Rutland <[email protected]>; Will
> Deacon <[email protected]>; Zhang, Lei <[email protected]>
> Subject: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum
> 010001
>
> +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> +#define MIDR_FUJITSU_ERRATUM_010001
> MIDR_FUJITSU_A64FX
> +#define MIDR_FUJITSU_ERRATUM_010001_MASK
> (~MIDR_VARIANT(1))
This workaround for the erratum should be applied for both A64FX v1r0 and
v0r0, however, the patch v5 is only enabled on A64FX v0r0(MIDR.Variant == 0
&& MIDR.Revision == 0).
This issue is caused by the macro MIDR_FUJITSU_ERRATUM_010001_MASK.
I have tested on both A64FX v1r0 and v0r0. This new patch will effect
only for A64FX.
--
Changed to be applied for not only A64FX v0r0 but also v1r0.
Signed-off-by: Zhang Lei <[email protected]>
---
arch/arm64/include/asm/cputype.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 2afb133..1fb47b5 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -129,7 +129,7 @@
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
-#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_VARIANT(1))
+#define MIDR_FUJITSU_ERRATUM_010001_MASK (~(0x1 << MIDR_VARIANT_SHIFT))
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
#ifndef __ASSEMBLY__
--
1.8.3.1
Best Regards,
Takayuki Okamoto