2023-09-16 05:29:39

by charles.kearney

Subject: [PATCH v1 1/1] ARM: dts: hpe: BUG: Correct GXP register ranges

From: Charles Kearney <[email protected]>

Bug fix to correct memory ranges on GXP to include host registers. This
corrects a issue where the host interrupt controller is not available.

Signed-off-by: Charles Kearney <[email protected]>
---
arch/arm/boot/dts/hpe/hpe-gxp.dtsi | 39 +++++++++++++++---------------
1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/hpe/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi
index cf735b3c4f35..18230a4754a6 100644
--- a/arch/arm/boot/dts/hpe/hpe-gxp.dtsi
+++ b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree file for HPE GXP
+ * Device Tree for HPE
*/

/dts-v1/;
@@ -52,73 +52,74 @@ L2: cache-controller@b0040000 {
cache-level = <2>;
};

- ahb@c0000000 {
+ ahb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0xc0000000 0x30000000>;
dma-ranges;
+ ranges = <0x0 0x80000000 0x20000000>,
+ <0x40000000 0xc0000000 0x3fff0000>;

- vic0: interrupt-controller@eff0000 {
+ vic0: interrupt-controller@4eff0000 {
compatible = "arm,pl192-vic";
- reg = <0xeff0000 0x1000>;
+ reg = <0x4eff0000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};

- vic1: interrupt-controller@80f00000 {
+ vic1: interrupt-controller@f00000 {
compatible = "arm,pl192-vic";
- reg = <0x80f00000 0x1000>;
+ reg = <0xf00000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};

- uarta: serial@e0 {
+ uarta: serial@400000e0 {
compatible = "ns16550a";
- reg = <0xe0 0x8>;
+ reg = <0x400000e0 0x8>;
interrupts = <17>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};

- uartb: serial@e8 {
+ uartb: serial@400000e8 {
compatible = "ns16550a";
- reg = <0xe8 0x8>;
+ reg = <0x400000e8 0x8>;
interrupts = <18>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};

- uartc: serial@f0 {
+ uartc: serial@400000f0 {
compatible = "ns16550a";
- reg = <0xf0 0x8>;
+ reg = <0x400000f0 0x8>;
interrupts = <19>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};

- usb0: usb@efe0000 {
+ usb0: usb@4efe0000 {
compatible = "hpe,gxp-ehci", "generic-ehci";
- reg = <0xefe0000 0x100>;
+ reg = <0x4efe0000 0x100>;
interrupts = <7>;
interrupt-parent = <&vic0>;
};

- st: timer@80 {
+ st: timer@40000080 {
compatible = "hpe,gxp-timer";
- reg = <0x80 0x16>;
+ reg = <0x40000080 0x16>;
interrupts = <0>;
interrupt-parent = <&vic0>;
clocks = <&iopclk>;
clock-names = "iop";
};

- usb1: usb@efe0100 {
+ usb1: usb@4efe0100 {
compatible = "hpe,gxp-ohci", "generic-ohci";
- reg = <0xefe0100 0x110>;
+ reg = <0x4efe0100 0x110>;
interrupts = <6>;
interrupt-parent = <&vic0>;
};
--
2.25.1

2023-09-17 13:41:18

by Krzysztof Kozlowski

Subject: Re: [PATCH v1 1/1] ARM: dts: hpe: BUG: Correct GXP register ranges

On 15/09/2023 18:54, [email protected] wrote:
> From: Charles Kearney <[email protected]>
>
> Bug fix to correct memory ranges on GXP to include host registers. This
> corrects a issue where the host interrupt controller is not available.

Then you miss Fixes tag. Maybe also Cc-stable tag.

>
> Signed-off-by: Charles Kearney <[email protected]>
> ---
> arch/arm/boot/dts/hpe/hpe-gxp.dtsi | 39 +++++++++++++++---------------
> 1 file changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/boot/dts/hpe/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi
> index cf735b3c4f35..18230a4754a6 100644
> --- a/arch/arm/boot/dts/hpe/hpe-gxp.dtsi
> +++ b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Device Tree file for HPE GXP
> + * Device Tree for HPE

How is this related to bug?

> */
>
> /dts-v1/;
> @@ -52,73 +52,74 @@ L2: cache-controller@b0040000 {
> cache-level = <2>;
> };
>
> - ahb@c0000000 {
> + ahb@80000000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> - ranges = <0x0 0xc0000000 0x30000000>;
> dma-ranges;
> + ranges = <0x0 0x80000000 0x20000000>,
> + <0x40000000 0xc0000000 0x3fff0000>;

Missing proper alignment.


Best regards,
Krzysztof