2022-09-08 15:09:46

by Zong Li

Subject: [PATCH v3 3/6] soc: sifive: ccache: determine the cache level from dts

Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li <[email protected]>
Signed-off-by: Greentime Hu <[email protected]>
---
drivers/soc/sifive/sifive_ccache.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 949b824e89ad..690c19489317 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -38,6 +38,7 @@
static void __iomem *ccache_base;
static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
static struct riscv_cacheinfo_ops ccache_cache_ops;
+static int level;

enum {
DIR_CORR = 0,
@@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
*this_leaf)
{
/* We want to use private group for composable cache only */
- if (this_leaf->level == 2)
+ if (this_leaf->level == level)
return &priv_attr_group;
else
return NULL;
@@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void)
if (!ccache_base)
return -ENOMEM;

+ if (of_property_read_u32(np, "cache-level", &level))
+ return -ENODEV;
+
intr_num = of_property_count_u32_elems(np, "interrupts");
if (!intr_num) {
pr_err("CCACHE: no interrupts property\n");
--
2.17.1

2022-09-08 19:37:46

by Conor Dooley

Subject: Re: [PATCH v3 3/6] soc: sifive: ccache: determine the cache level from dts

On 08/09/2022 15:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Composable cache could be L2 or L3 cache, use 'cache-level' property of
> device node to determine the level.
>
> Signed-off-by: Zong Li <[email protected]>
> Signed-off-by: Greentime Hu <[email protected]>
> ---
> drivers/soc/sifive/sifive_ccache.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 949b824e89ad..690c19489317 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -38,6 +38,7 @@
> static void __iomem *ccache_base;
> static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> static struct riscv_cacheinfo_ops ccache_cache_ops;
> +static int level;
>
> enum {
> DIR_CORR = 0,
> @@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
> *this_leaf)
> {
> /* We want to use private group for composable cache only */
> - if (this_leaf->level == 2)
> + if (this_leaf->level == level)
> return &priv_attr_group;
> else
> return NULL;
> @@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void)
> if (!ccache_base)
> return -ENOMEM;
>
> + if (of_property_read_u32(np, "cache-level", &level))
> + return -ENODEV;

I think ENOENT or EINVAL are more comment patterns here?

Either way,
Reviewed-by: Conor Dooley <[email protected]>

> +
> intr_num = of_property_count_u32_elems(np, "interrupts");
> if (!intr_num) {
> pr_err("CCACHE: no interrupts property\n");
> --
> 2.17.1
>

2022-09-12 06:57:27

by Zong Li

Subject: Re: [PATCH v3 3/6] soc: sifive: ccache: determine the cache level from dts

On Fri, Sep 9, 2022 at 2:28 AM <[email protected]> wrote:
>
> On 08/09/2022 15:44, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Composable cache could be L2 or L3 cache, use 'cache-level' property of
> > device node to determine the level.
> >
> > Signed-off-by: Zong Li <[email protected]>
> > Signed-off-by: Greentime Hu <[email protected]>
> > ---
> > drivers/soc/sifive/sifive_ccache.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 949b824e89ad..690c19489317 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -38,6 +38,7 @@
> > static void __iomem *ccache_base;
> > static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> > static struct riscv_cacheinfo_ops ccache_cache_ops;
> > +static int level;
> >
> > enum {
> > DIR_CORR = 0,
> > @@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
> > *this_leaf)
> > {
> > /* We want to use private group for composable cache only */
> > - if (this_leaf->level == 2)
> > + if (this_leaf->level == level)
> > return &priv_attr_group;
> > else
> > return NULL;
> > @@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void)
> > if (!ccache_base)
> > return -ENOMEM;
> >
> > + if (of_property_read_u32(np, "cache-level", &level))
> > + return -ENODEV;
>
> I think ENOENT or EINVAL are more comment patterns here?
>
> Either way,
> Reviewed-by: Conor Dooley <[email protected]>
>

I will fix it in V4 patch. Thanks

> > +
> > intr_num = of_property_count_u32_elems(np, "interrupts");
> > if (!intr_num) {
> > pr_err("CCACHE: no interrupts property\n");
> > --
> > 2.17.1
> >
>