This patch-set introduces UFS (Universal Flash Storage) host controller support
for Samsung family SoC. Mostly, it consists of UFS PHY and host specific driver.
- Changes since v2:
* fixed build warning by kbuild test robot
* Added Reported-by tags
- Changes since v1:
* fixed make dt_binding_check error as pointed by Rob
* Addressed Krzysztof's review comments
* Added Reviewed-by tags
patch 1/5: define devicetree bindings for UFS PHY
patch 2/5: Adds UFS PHY driver
patch 3/5: define devicetree bindings for UFS HCI
patch 4/5: Adds Samsung UFS HCI driver
patch 5/5: Enabled UFS on exynos7 platform
Note: This series is based on Linux-5.6-rc6 (commit: fb33c6510d55)
Alim Akhtar (5):
dt-bindings: phy: Document Samsung UFS PHY bindings
phy: samsung-ufs: add UFS PHY driver for samsung SoC
Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
controller
scsi: ufs-exynos: add UFS host support for Exynos SoCs
arm64: dts: Add node for ufs exynos7
.../bindings/phy/samsung,ufs-phy.yaml | 62 +
.../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
.../boot/dts/exynos/exynos7-espresso.dts | 16 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 44 +-
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 85 +
drivers/phy/samsung/phy-samsung-ufs.c | 311 ++++
drivers/phy/samsung/phy-samsung-ufs.h | 100 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-exynos.c | 1399 +++++++++++++++++
drivers/scsi/ufs/ufs-exynos.h | 268 ++++
drivers/scsi/ufs/unipro.h | 41 +
include/linux/phy/phy-samsung-ufs.h | 70 +
15 files changed, 2521 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
create mode 100644 include/linux/phy/phy-samsung-ufs.h
--
2.17.1
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Reviewed-by: Kiwoong Kim <[email protected]>
Signed-off-by: Seungwon Jeon <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 85 +++++++
drivers/phy/samsung/phy-samsung-ufs.c | 311 ++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.h | 100 +++++++++
include/linux/phy/phy-samsung-ufs.h | 70 ++++++
6 files changed, 576 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
create mode 100644 include/linux/phy/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 9e483d1fdaf2..fc1e3c17f842 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index 000000000000..da981c1ac040
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = exynos7_pre_init_cfg,
+ [CFG_POST_INIT] = exynos7_post_init_cfg,
+ [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
+ [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
+};
+
+static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
+ .cfg = exynos7_ufs_phy_cfgs,
+ .isol = {
+ .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
+ .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
+ .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
+ },
+};
+
+#endif /* _PHY_EXYNOS7_UFS_H_ */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
new file mode 100644
index 000000000000..2d5db24de49b
--- /dev/null
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver for Samsung SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <[email protected]>
+ * Author: Alim Akhtar <[email protected]>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-samsung-ufs.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "phy-samsung-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
+ const struct samsung_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ const unsigned int timeout_us = 100000;
+ const unsigned int sleep_us = 10;
+ u32 val;
+ int err;
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
+ val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy pll lock acquisition %d\n", err);
+ goto out;
+ }
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy cdr lock acquisition %d\n", err);
+ goto out;
+ }
+
+out:
+ return err;
+}
+
+int samsung_ufs_phy_calibrate(struct phy *phy)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct samsung_ufs_phy_cfg *cfg;
+ int i;
+ int err = 0;
+
+ if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
+ ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n",
+ ufs_phy->ufs_phy_state);
+ return -EINVAL;
+ }
+
+ if (ufs_phy->is_pre_init)
+ ufs_phy->is_pre_init = false;
+ if (ufs_phy->is_post_init) {
+ ufs_phy->is_post_init = false;
+ ufs_phy->ufs_phy_state = CFG_POST_INIT;
+ }
+ if (ufs_phy->is_pre_pmc) {
+ ufs_phy->is_pre_pmc = false;
+ ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
+ }
+ if (ufs_phy->is_post_pmc) {
+ ufs_phy->is_post_pmc = false;
+ ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
+ }
+
+ switch (ufs_phy->ufs_phy_state) {
+ case CFG_PRE_INIT:
+ ufs_phy->is_post_init = true;
+ break;
+ case CFG_POST_INIT:
+ ufs_phy->is_pre_pmc = true;
+ break;
+ case CFG_PRE_PWR_HS:
+ ufs_phy->is_post_pmc = true;
+ break;
+ case CFG_POST_PWR_HS:
+ break;
+ default:
+ dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
+ }
+
+ cfg = cfgs[ufs_phy->ufs_phy_state];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ samsung_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+ if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
+ err = samsung_ufs_phy_wait_for_lock_acq(phy);
+out:
+ return err;
+}
+
+static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(phy->dev, "ref_clk");
+ if (IS_ERR(child))
+ dev_err(phy->dev, "failed to get ref_clk clock\n");
+ else
+ phy->ref_clk = child;
+
+ parent = devm_clk_get(phy->dev, "ref_clk_parent");
+ if (IS_ERR(parent))
+ dev_err(phy->dev, "failed to get ref_clk_parent clock\n");
+ else
+ phy->ref_clk_parent = parent;
+
+ return clk_set_parent(child, parent);
+}
+
+static int samsung_ufs_phy_init(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+
+ _phy->lane_cnt = phy->attrs.bus_width;
+ _phy->ufs_phy_state = CFG_PRE_INIT;
+
+ _phy->is_pre_init = true;
+ _phy->is_post_init = false;
+ _phy->is_pre_pmc = false;
+ _phy->is_post_pmc = false;
+
+ samsung_ufs_phy_clks_init(_phy);
+
+ samsung_ufs_phy_calibrate(phy);
+
+ return 0;
+}
+
+static int samsung_ufs_phy_power_on(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+ int ret;
+
+ ret = clk_prepare_enable(_phy->ref_clk);
+ if (ret) {
+ dev_err(_phy->dev, "%s: ref_clk enable failed %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ samsung_ufs_phy_ctrl_isol(_phy, false);
+ return 0;
+}
+
+static int samsung_ufs_phy_power_off(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+
+ samsung_ufs_phy_ctrl_isol(_phy, true);
+ clk_disable_unprepare(_phy->ref_clk);
+ return 0;
+}
+
+static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
+ enum phy_mode mode, int submode)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(generic_phy);
+
+ _phy->mode = PHY_MODE_INVALID;
+
+ if (mode > 0)
+ _phy->mode = mode;
+
+ return 0;
+}
+
+static struct phy_ops samsung_ufs_phy_ops = {
+ .init = samsung_ufs_phy_init,
+ .power_on = samsung_ufs_phy_power_on,
+ .power_off = samsung_ufs_phy_power_off,
+ .calibrate = samsung_ufs_phy_calibrate,
+ .set_mode = samsung_ufs_phy_set_mode,
+}
+;
+static const struct of_device_id samsung_ufs_phy_match[];
+
+static int samsung_ufs_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ const struct of_device_id *match;
+ struct samsung_ufs_phy *phy;
+ struct phy *gen_phy;
+ struct phy_provider *phy_provider;
+ const struct samsung_ufs_phy_drvdata *drvdata;
+ int err = 0;
+
+ match = of_match_node(samsung_ufs_phy_match, dev->of_node);
+ if (!match) {
+ err = -EINVAL;
+ dev_err(dev, "failed to get match_node\n");
+ goto out;
+ }
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy-pma");
+ phy->reg_pma = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->reg_pma)) {
+ err = PTR_ERR(phy->reg_pma);
+ goto out;
+ }
+
+ phy->reg_pmu = syscon_regmap_lookup_by_phandle(
+ dev->of_node, "samsung,pmu-syscon");
+ if (IS_ERR(phy->reg_pmu)) {
+ err = PTR_ERR(phy->reg_pmu);
+ dev_err(dev, "failed syscon remap for pmu\n");
+ goto out;
+ }
+
+ gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
+ if (IS_ERR(gen_phy)) {
+ err = PTR_ERR(gen_phy);
+ dev_err(dev, "failed to create PHY for ufs-phy\n");
+ goto out;
+ }
+
+ drvdata = match->data;
+ phy->dev = dev;
+ phy->drvdata = drvdata;
+ phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
+ phy->isol = &drvdata->isol;
+ phy->lane_cnt = PHY_DEF_LANE_CNT;
+
+ phy_set_drvdata(gen_phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ err = PTR_ERR(phy_provider);
+ dev_err(dev, "failed to register phy-provider\n");
+ goto out;
+ }
+out:
+ return err;
+}
+
+static const struct of_device_id samsung_ufs_phy_match[] = {
+ {
+ .compatible = "samsung,exynos7-ufs-phy",
+ .data = &exynos7_ufs_phy,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
+
+static struct platform_driver samsung_ufs_phy_driver = {
+ .probe = samsung_ufs_phy_probe,
+ .driver = {
+ .name = "samsung-ufs-phy",
+ .of_match_table = samsung_ufs_phy_match,
+ },
+};
+module_platform_driver(samsung_ufs_phy_driver);
+MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
+MODULE_AUTHOR("Seungwon Jeon <[email protected]>");
+MODULE_AUTHOR("Alim Akhtar <[email protected]>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
new file mode 100644
index 000000000000..d0ae2b416b2b
--- /dev/null
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <[email protected]>
+ * Author: Alim Akhtar <[email protected]>
+ *
+ */
+#ifndef _PHY_SAMSUNG_UFS_
+#define _PHY_SAMSUNG_UFS_
+
+#define PHY_COMN_BLK 1
+#define PHY_TRSV_BLK 2
+#define END_UFS_PHY_CFG { 0 }
+#define PHY_TRSV_CH_OFFSET 0x30
+#define PHY_APB_ADDR(off) ((off) << 2)
+
+#define PHY_COMN_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = 0, \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_COMN_BLK, \
+}
+
+#define PHY_TRSV_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_TRSV_BLK, \
+}
+
+/* UFS PHY registers */
+#define PHY_PLL_LOCK_STATUS 0x1e
+#define PHY_CDR_LOCK_STATUS 0x5e
+
+#define PHY_PLL_LOCK_BIT BIT(5)
+#define PHY_CDR_LOCK_BIT BIT(4)
+
+/* PHY calibration point/state */
+enum {
+ CFG_PRE_INIT,
+ CFG_POST_INIT,
+ CFG_PRE_PWR_HS,
+ CFG_POST_PWR_HS,
+ CFG_TAG_MAX,
+};
+
+struct samsung_ufs_phy_cfg {
+ u32 off_0;
+ u32 off_1;
+ u32 val;
+ u8 desc;
+ u8 id;
+};
+
+struct samsung_ufs_phy_drvdata {
+ const struct samsung_ufs_phy_cfg **cfg;
+ struct pmu_isol {
+ u32 offset;
+ u32 mask;
+ u32 en;
+ } isol;
+};
+
+struct samsung_ufs_phy {
+ struct device *dev;
+ void __iomem *reg_pma;
+ struct regmap *reg_pmu;
+ struct clk *ref_clk;
+ struct clk *ref_clk_parent;
+ const struct samsung_ufs_phy_drvdata *drvdata;
+ struct samsung_ufs_phy_cfg **cfg;
+ const struct pmu_isol *isol;
+ u8 lane_cnt;
+ int ufs_phy_state;
+ enum phy_mode mode;
+ bool is_pre_init;
+ bool is_post_init;
+ bool is_pre_pmc;
+ bool is_post_pmc;
+};
+
+static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
+{
+ return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
+}
+
+static inline void samsung_ufs_phy_ctrl_isol(
+ struct samsung_ufs_phy *phy, u32 isol)
+{
+ regmap_update_bits(phy->reg_pmu, phy->isol->offset,
+ phy->isol->mask, isol ? 0 : phy->isol->en);
+}
+
+#include "phy-exynos7-ufs.h"
+
+#endif /* _PHY_SAMSUNG_UFS_ */
diff --git a/include/linux/phy/phy-samsung-ufs.h b/include/linux/phy/phy-samsung-ufs.h
new file mode 100644
index 000000000000..1def56207f5d
--- /dev/null
+++ b/include/linux/phy/phy-samsung-ufs.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * phy-samsung-ufs.h - Header file for the UFS PHY of Samsung SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <[email protected]>
+ * Author: Alim Akhtar <[email protected]>
+ *
+ */
+
+#ifndef _PHY_EXYNOS_UFS_H_
+#define _PHY_EXYNOS_UFS_H_
+
+#include "phy.h"
+
+/* description for PHY calibration */
+enum {
+ /* applicable to any */
+ PWR_DESC_ANY = 0,
+ /* mode */
+ PWR_DESC_PWM = 1,
+ PWR_DESC_HS = 2,
+ /* series */
+ PWR_DESC_SER_A = 1,
+ PWR_DESC_SER_B = 2,
+ /* gear */
+ PWR_DESC_G1 = 1,
+ PWR_DESC_G2 = 2,
+ PWR_DESC_G3 = 3,
+ PWR_DESC_G4 = 4,
+ PWR_DESC_G5 = 5,
+ PWR_DESC_G6 = 6,
+ PWR_DESC_G7 = 7,
+ /* field mask */
+ MD_MASK = 0x3,
+ SR_MASK = 0x3,
+ GR_MASK = 0x7,
+};
+
+#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
+#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | PWR_DESC_HS)
+#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
+#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
+#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
+#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
+#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_HS)
+#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_PWM)
+#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_ANY)
+#define IS_PWR_MODE_HS(d) (((d) & MD_MASK) == PWR_DESC_HS)
+#define IS_PWR_MODE_PWM(d) (((d) & MD_MASK) == PWR_DESC_PWM)
+#define IS_PWR_MODE_ANY(d) ((d) == PWR_MODE_ANY)
+#define IS_PWR_MODE_HS_ANY(d) ((d) == PWR_MODE_HS_ANY)
+#define COMP_PWR_MODE(a, b) ((a) == (b))
+#define COMP_PWR_MODE_GEAR(a, b) ((((a) >> 4) & GR_MASK) == \
+ (((b) >> 4) & GR_MASK))
+#define COMP_PWR_MODE_SER(a, b) ((((a) >> 2) & SR_MASK) == \
+ (((b) >> 2) & SR_MASK))
+#define COMP_PWR_MODE_MD(a, b) (((a) & MD_MASK) == ((b) & MD_MASK))
+
+#endif /* _PHY_EXYNOS_UFS_H_ */
--
2.17.1
On Thu, 2020-03-19 at 20:30 +0530, Alim Akhtar wrote:
> This patch-set introduces UFS (Universal Flash Storage) host controller support
> for Samsung family SoC. Mostly, it consists of UFS PHY and host specific driver.
>
> - Changes since v2:
> * fixed build warning by kbuild test robot
> * Added Reported-by tags
>
> - Changes since v1:
> * fixed make dt_binding_check error as pointed by Rob
> * Addressed Krzysztof's review comments
> * Added Reviewed-by tags
>
>
> patch 1/5: define devicetree bindings for UFS PHY
> patch 2/5: Adds UFS PHY driver
> patch 3/5: define devicetree bindings for UFS HCI
> patch 4/5: Adds Samsung UFS HCI driver
> patch 5/5: Enabled UFS on exynos7 platform
Hi
Is this compatible with Exynos7420? Looking at u-boot source code,
there is Espresso7420 - isn't it the same device? Also this driver
looks very similar to the one from vendor kernel sources (for my
device).
I did tried to run this on my Exynos7420 based device (Samsung S6 Edge
phone) with 5.6-rc6, to get any storage working (since it doesn't have sdcard slot).
At first i got error in exynos_ufs_config_smu. Looking at vendor
sources, on my device only secureos is able to write to those registers
so i fixed it by using smc calls and driver probes fine. Will this be
also supported by driver (maybe in future)?
But now got another error
[ 1.610464] exynos-ufshc 15570000.ufs: ufshcd_intr: Unhandled
interrupt 0x00000000
[ 1.610629] host_regs: 00000000: 0383ff0f 00000000 00000200 00000000
[ 1.610747] host_regs: 00000010: 00000101 00007fce 00000000 00000000
[ 1.610863] host_regs: 00000020: 00000000 00030e75 00000000 00000000
[ 1.614727] host_regs: 00000030: 0000000f 00000000 00000000 00000000
[ 1.621061] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 1.627396] host_regs: 00000050: f8c37000 00000000 00000001 00000000
[ 1.633730] host_regs: 00000060: 00000001 00000000 00000000 00000000
[ 1.640065] host_regs: 00000070: f9644000 00000000 00000000 00000000
[ 1.646400] host_regs: 00000080: 00000001 00000000 00000000 00000000
[ 1.652734] host_regs: 00000090: 00000002 95290000 00000000 00000000
[ 1.747649] exynos-ufshc 15570000.ufs: ufshcd_intr: Unhandled
interrupt 0x00000000
[ 1.747807] host_regs: 00000000: 0383ff0f 00000000 00000200 00000000
[ 1.747924] host_regs: 00000010: 00000101 00007fce 00000000 00000000
[ 1.748041] host_regs: 00000020: 00000000 00030e75 00000000 00000000
[ 1.751909] host_regs: 00000030: 0000000f 00000000 00000000 00000000
[ 1.758244] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 1.764578] host_regs: 00000050: f8c37000 00000000 00000001 00000000
[ 1.770913] host_regs: 00000060: 00000001 00000000 00000000 00000000
[ 1.777248] host_regs: 00000070: f9644000 00000000 00000000 00000000
[ 1.783582] host_regs: 00000080: 00000001 00000000 00000000 00000000
[ 1.789917] host_regs: 00000090: 00000002 95290000 00000000 00000000
[ 1.884841] exynos-ufshc 15570000.ufs: ufshcd_intr: Unhandled
interrupt 0x00000000
[ 1.884999] host_regs: 00000000: 0383ff0f 00000000 00000200 00000000
[ 1.885116] host_regs: 00000010: 00000101 00007fce 00000000 00000000
[ 1.885233] host_regs: 00000020: 00000000 00030e75 00000000 00000000
[ 1.889100] host_regs: 00000030: 0000000f 00000000 00000000 00000000
[ 1.895435] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 1.901770] host_regs: 00000050: f8c37000 00000000 00000001 00000000
[ 1.908104] host_regs: 00000060: 00000001 00000000 00000000 00000000
[ 1.914439] host_regs: 00000070: f9644000 00000000 00000000 00000000
[ 1.920773] host_regs: 00000080: 00000001 00000000 00000000 00000000
[ 1.927108] host_regs: 00000090: 00000002 95290000 00000000 00000000
[ 2.998155] exynos-ufshc 15570000.ufs: ufshcd_query_flag: Sending
flag query for idn 1 failed, err = -11
[ 4.502138] exynos-ufshc 15570000.ufs: ufshcd_query_flag: Sending
flag query for idn 1 failed, err = -11
[ 6.006137] exynos-ufshc 15570000.ufs: ufshcd_query_flag: Sending
flag query for idn 1 failed, err = -11
[ 6.006311] exynos-ufshc 15570000.ufs: ufshcd_query_flag_retry:
query attribute, opcode 5, idn 1, failed with error -11 after 3 retires
[ 6.006545] exynos-ufshc 15570000.ufs: ufshcd_complete_dev_init
reading fDeviceInit flag failed with error -11
Do You have any idea what could be wrong?
Thanks
>
> Note: This series is based on Linux-5.6-rc6 (commit: fb33c6510d55)
>
>
> Alim Akhtar (5):
> dt-bindings: phy: Document Samsung UFS PHY bindings
> phy: samsung-ufs: add UFS PHY driver for samsung SoC
> Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
> controller
> scsi: ufs-exynos: add UFS host support for Exynos SoCs
> arm64: dts: Add node for ufs exynos7
>
> .../bindings/phy/samsung,ufs-phy.yaml | 62 +
> .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
> .../boot/dts/exynos/exynos7-espresso.dts | 16 +
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 44 +-
> drivers/phy/samsung/Kconfig | 9 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos7-ufs.h | 85 +
> drivers/phy/samsung/phy-samsung-ufs.c | 311 ++++
> drivers/phy/samsung/phy-samsung-ufs.h | 100 ++
> drivers/scsi/ufs/Kconfig | 12 +
> drivers/scsi/ufs/Makefile | 1 +
> drivers/scsi/ufs/ufs-exynos.c | 1399 +++++++++++++++++
> drivers/scsi/ufs/ufs-exynos.h | 268 ++++
> drivers/scsi/ufs/unipro.h | 41 +
> include/linux/phy/phy-samsung-ufs.h | 70 +
> 15 files changed, 2521 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos.h
> create mode 100644 include/linux/phy/phy-samsung-ufs.h
>
Hi Alim,
On 3/19/2020 8:30 PM, Alim Akhtar wrote:
> This patch introduces Samsung UFS PHY driver. This driver
> supports to deal with phy calibration and power control
> according to UFS host driver's behavior.
>
> Reviewed-by: Kiwoong Kim <[email protected]>
> Signed-off-by: Seungwon Jeon <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> Cc: Kishon Vijay Abraham I <[email protected]>
> ---
> drivers/phy/samsung/Kconfig | 9 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos7-ufs.h | 85 +++++++
> drivers/phy/samsung/phy-samsung-ufs.c | 311 ++++++++++++++++++++++++++
> drivers/phy/samsung/phy-samsung-ufs.h | 100 +++++++++
> include/linux/phy/phy-samsung-ufs.h | 70 ++++++
Why is this added in include directory? will it be used by controller driver?
Thanks
Kishon
> 6 files changed, 576 insertions(+)
> create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
> create mode 100644 include/linux/phy/phy-samsung-ufs.h
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index 9e483d1fdaf2..fc1e3c17f842 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
> Enable PCIe PHY support for Exynos SoC series.
> This driver provides PHY interface for Exynos PCIe controller.
>
> +config PHY_SAMSUNG_UFS
> + tristate "SAMSUNG SoC series UFS PHY driver"
> + depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable this to support the Samsung UFS PHY driver for
> + Samsung SoCs. This driver provides the interface for UFS
> + host controller to do PHY related programming.
> +
> config PHY_SAMSUNG_USB2
> tristate "Samsung USB 2.0 PHY driver"
> depends on HAS_IOMEM
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index db9b1aa0de6e..3959100fe8a2 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> +obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
> obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
> phy-exynos-usb2-y += phy-samsung-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h b/drivers/phy/samsung/phy-exynos7-ufs.h
> new file mode 100644
> index 000000000000..da981c1ac040
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.h
> @@ -0,0 +1,85 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UFS PHY driver data for Samsung EXYNOS7 SoC
> + *
> + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> + */
> +#ifndef _PHY_EXYNOS7_UFS_H_
> +#define _PHY_EXYNOS7_UFS_H_
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> +
> +/* Calibration for phy initialization */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
> + END_UFS_PHY_CFG
> +};
> +
> +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> + END_UFS_PHY_CFG
> +};
> +
> +/* Calibration for HS mode series A/B */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
> + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
> + /* Setting order: 1st(0x16, 2nd(0x15) */
> + PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
> + PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
> + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
> + PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
> + PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
> + PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
> + END_UFS_PHY_CFG
> +};
> +
> +/* Calibration for HS mode series A/B atfer PMC */
> +static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
> + PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
> + END_UFS_PHY_CFG
> +};
> +
> +static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
> + [CFG_PRE_INIT] = exynos7_pre_init_cfg,
> + [CFG_POST_INIT] = exynos7_post_init_cfg,
> + [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
> + [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
> +};
> +
> +static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
> + .cfg = exynos7_ufs_phy_cfgs,
> + .isol = {
> + .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
> + .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
> + .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
> + },
> +};
> +
> +#endif /* _PHY_EXYNOS7_UFS_H_ */
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> new file mode 100644
> index 000000000000..2d5db24de49b
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -0,0 +1,311 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * UFS PHY driver for Samsung SoC
> + *
> + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> + * Author: Seungwon Jeon <[email protected]>
> + * Author: Alim Akhtar <[email protected]>
> + *
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/phy-samsung-ufs.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define for_each_phy_lane(phy, i) \
> + for (i = 0; i < (phy)->lane_cnt; i++)
> +#define for_each_phy_cfg(cfg) \
> + for (; (cfg)->id; (cfg)++)
> +
> +#define PHY_DEF_LANE_CNT 1
> +
> +static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> + const struct samsung_ufs_phy_cfg *cfg, u8 lane)
> +{
> + enum {LANE_0, LANE_1}; /* lane index */
> +
> + switch (lane) {
> + case LANE_0:
> + writel(cfg->val, (phy)->reg_pma + cfg->off_0);
> + break;
> + case LANE_1:
> + if (cfg->id == PHY_TRSV_BLK)
> + writel(cfg->val, (phy)->reg_pma + cfg->off_1);
> + break;
> + }
> +}
> +
> +int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
> +{
> + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> + const unsigned int timeout_us = 100000;
> + const unsigned int sleep_us = 10;
> + u32 val;
> + int err;
> +
> + err = readl_poll_timeout(
> + ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
> + val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
> + if (err) {
> + dev_err(ufs_phy->dev,
> + "failed to get phy pll lock acquisition %d\n", err);
> + goto out;
> + }
> +
> + err = readl_poll_timeout(
> + ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
> + val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
> + if (err) {
> + dev_err(ufs_phy->dev,
> + "failed to get phy cdr lock acquisition %d\n", err);
> + goto out;
> + }
> +
> +out:
> + return err;
> +}
> +
> +int samsung_ufs_phy_calibrate(struct phy *phy)
> +{
> + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> + struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
> + const struct samsung_ufs_phy_cfg *cfg;
> + int i;
> + int err = 0;
> +
> + if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
> + ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
> + dev_err(ufs_phy->dev, "invalid phy config index %d\n",
> + ufs_phy->ufs_phy_state);
> + return -EINVAL;
> + }
> +
> + if (ufs_phy->is_pre_init)
> + ufs_phy->is_pre_init = false;
> + if (ufs_phy->is_post_init) {
> + ufs_phy->is_post_init = false;
> + ufs_phy->ufs_phy_state = CFG_POST_INIT;
> + }
> + if (ufs_phy->is_pre_pmc) {
> + ufs_phy->is_pre_pmc = false;
> + ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
> + }
> + if (ufs_phy->is_post_pmc) {
> + ufs_phy->is_post_pmc = false;
> + ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
> + }
> +
> + switch (ufs_phy->ufs_phy_state) {
> + case CFG_PRE_INIT:
> + ufs_phy->is_post_init = true;
> + break;
> + case CFG_POST_INIT:
> + ufs_phy->is_pre_pmc = true;
> + break;
> + case CFG_PRE_PWR_HS:
> + ufs_phy->is_post_pmc = true;
> + break;
> + case CFG_POST_PWR_HS:
> + break;
> + default:
> + dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
> + }
> +
> + cfg = cfgs[ufs_phy->ufs_phy_state];
> + if (!cfg)
> + goto out;
> +
> + for_each_phy_cfg(cfg) {
> + for_each_phy_lane(ufs_phy, i) {
> + samsung_ufs_phy_config(ufs_phy, cfg, i);
> + }
> + }
> +
> + if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
> + err = samsung_ufs_phy_wait_for_lock_acq(phy);
> +out:
> + return err;
> +}
> +
> +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
> +{
> + struct clk *child, *parent;
> +
> + child = devm_clk_get(phy->dev, "ref_clk");
> + if (IS_ERR(child))
> + dev_err(phy->dev, "failed to get ref_clk clock\n");
> + else
> + phy->ref_clk = child;
> +
> + parent = devm_clk_get(phy->dev, "ref_clk_parent");
> + if (IS_ERR(parent))
> + dev_err(phy->dev, "failed to get ref_clk_parent clock\n");
> + else
> + phy->ref_clk_parent = parent;
> +
> + return clk_set_parent(child, parent);
> +}
> +
> +static int samsung_ufs_phy_init(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> +
> + _phy->lane_cnt = phy->attrs.bus_width;
> + _phy->ufs_phy_state = CFG_PRE_INIT;
> +
> + _phy->is_pre_init = true;
> + _phy->is_post_init = false;
> + _phy->is_pre_pmc = false;
> + _phy->is_post_pmc = false;
> +
> + samsung_ufs_phy_clks_init(_phy);
> +
> + samsung_ufs_phy_calibrate(phy);
> +
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_power_on(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> + int ret;
> +
> + ret = clk_prepare_enable(_phy->ref_clk);
> + if (ret) {
> + dev_err(_phy->dev, "%s: ref_clk enable failed %d\n",
> + __func__, ret);
> + return ret;
> + }
> +
> + samsung_ufs_phy_ctrl_isol(_phy, false);
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_power_off(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> +
> + samsung_ufs_phy_ctrl_isol(_phy, true);
> + clk_disable_unprepare(_phy->ref_clk);
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
> + enum phy_mode mode, int submode)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(generic_phy);
> +
> + _phy->mode = PHY_MODE_INVALID;
> +
> + if (mode > 0)
> + _phy->mode = mode;
> +
> + return 0;
> +}
> +
> +static struct phy_ops samsung_ufs_phy_ops = {
> + .init = samsung_ufs_phy_init,
> + .power_on = samsung_ufs_phy_power_on,
> + .power_off = samsung_ufs_phy_power_off,
> + .calibrate = samsung_ufs_phy_calibrate,
> + .set_mode = samsung_ufs_phy_set_mode,
> +}
> +;
> +static const struct of_device_id samsung_ufs_phy_match[];
> +
> +static int samsung_ufs_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + const struct of_device_id *match;
> + struct samsung_ufs_phy *phy;
> + struct phy *gen_phy;
> + struct phy_provider *phy_provider;
> + const struct samsung_ufs_phy_drvdata *drvdata;
> + int err = 0;
> +
> + match = of_match_node(samsung_ufs_phy_match, dev->of_node);
> + if (!match) {
> + err = -EINVAL;
> + dev_err(dev, "failed to get match_node\n");
> + goto out;
> + }
> +
> + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> + if (!phy) {
> + err = -ENOMEM;
> + goto out;
> + }
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy-pma");
> + phy->reg_pma = devm_ioremap_resource(dev, res);
> + if (IS_ERR(phy->reg_pma)) {
> + err = PTR_ERR(phy->reg_pma);
> + goto out;
> + }
> +
> + phy->reg_pmu = syscon_regmap_lookup_by_phandle(
> + dev->of_node, "samsung,pmu-syscon");
> + if (IS_ERR(phy->reg_pmu)) {
> + err = PTR_ERR(phy->reg_pmu);
> + dev_err(dev, "failed syscon remap for pmu\n");
> + goto out;
> + }
> +
> + gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
> + if (IS_ERR(gen_phy)) {
> + err = PTR_ERR(gen_phy);
> + dev_err(dev, "failed to create PHY for ufs-phy\n");
> + goto out;
> + }
> +
> + drvdata = match->data;
> + phy->dev = dev;
> + phy->drvdata = drvdata;
> + phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
> + phy->isol = &drvdata->isol;
> + phy->lane_cnt = PHY_DEF_LANE_CNT;
> +
> + phy_set_drvdata(gen_phy, phy);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + err = PTR_ERR(phy_provider);
> + dev_err(dev, "failed to register phy-provider\n");
> + goto out;
> + }
> +out:
> + return err;
> +}
> +
> +static const struct of_device_id samsung_ufs_phy_match[] = {
> + {
> + .compatible = "samsung,exynos7-ufs-phy",
> + .data = &exynos7_ufs_phy,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
> +
> +static struct platform_driver samsung_ufs_phy_driver = {
> + .probe = samsung_ufs_phy_probe,
> + .driver = {
> + .name = "samsung-ufs-phy",
> + .of_match_table = samsung_ufs_phy_match,
> + },
> +};
> +module_platform_driver(samsung_ufs_phy_driver);
> +MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
> +MODULE_AUTHOR("Seungwon Jeon <[email protected]>");
> +MODULE_AUTHOR("Alim Akhtar <[email protected]>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
> new file mode 100644
> index 000000000000..d0ae2b416b2b
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-samsung-ufs.h
> @@ -0,0 +1,100 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UFS PHY driver for Samsung EXYNOS SoC
> + *
> + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> + * Author: Seungwon Jeon <[email protected]>
> + * Author: Alim Akhtar <[email protected]>
> + *
> + */
> +#ifndef _PHY_SAMSUNG_UFS_
> +#define _PHY_SAMSUNG_UFS_
> +
> +#define PHY_COMN_BLK 1
> +#define PHY_TRSV_BLK 2
> +#define END_UFS_PHY_CFG { 0 }
> +#define PHY_TRSV_CH_OFFSET 0x30
> +#define PHY_APB_ADDR(off) ((off) << 2)
> +
> +#define PHY_COMN_REG_CFG(o, v, d) { \
> + .off_0 = PHY_APB_ADDR((o)), \
> + .off_1 = 0, \
> + .val = (v), \
> + .desc = (d), \
> + .id = PHY_COMN_BLK, \
> +}
> +
> +#define PHY_TRSV_REG_CFG(o, v, d) { \
> + .off_0 = PHY_APB_ADDR((o)), \
> + .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
> + .val = (v), \
> + .desc = (d), \
> + .id = PHY_TRSV_BLK, \
> +}
> +
> +/* UFS PHY registers */
> +#define PHY_PLL_LOCK_STATUS 0x1e
> +#define PHY_CDR_LOCK_STATUS 0x5e
> +
> +#define PHY_PLL_LOCK_BIT BIT(5)
> +#define PHY_CDR_LOCK_BIT BIT(4)
> +
> +/* PHY calibration point/state */
> +enum {
> + CFG_PRE_INIT,
> + CFG_POST_INIT,
> + CFG_PRE_PWR_HS,
> + CFG_POST_PWR_HS,
> + CFG_TAG_MAX,
> +};
> +
> +struct samsung_ufs_phy_cfg {
> + u32 off_0;
> + u32 off_1;
> + u32 val;
> + u8 desc;
> + u8 id;
> +};
> +
> +struct samsung_ufs_phy_drvdata {
> + const struct samsung_ufs_phy_cfg **cfg;
> + struct pmu_isol {
> + u32 offset;
> + u32 mask;
> + u32 en;
> + } isol;
> +};
> +
> +struct samsung_ufs_phy {
> + struct device *dev;
> + void __iomem *reg_pma;
> + struct regmap *reg_pmu;
> + struct clk *ref_clk;
> + struct clk *ref_clk_parent;
> + const struct samsung_ufs_phy_drvdata *drvdata;
> + struct samsung_ufs_phy_cfg **cfg;
> + const struct pmu_isol *isol;
> + u8 lane_cnt;
> + int ufs_phy_state;
> + enum phy_mode mode;
> + bool is_pre_init;
> + bool is_post_init;
> + bool is_pre_pmc;
> + bool is_post_pmc;
> +};
> +
> +static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
> +{
> + return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
> +}
> +
> +static inline void samsung_ufs_phy_ctrl_isol(
> + struct samsung_ufs_phy *phy, u32 isol)
> +{
> + regmap_update_bits(phy->reg_pmu, phy->isol->offset,
> + phy->isol->mask, isol ? 0 : phy->isol->en);
> +}
> +
> +#include "phy-exynos7-ufs.h"
> +
> +#endif /* _PHY_SAMSUNG_UFS_ */
> diff --git a/include/linux/phy/phy-samsung-ufs.h b/include/linux/phy/phy-samsung-ufs.h
> new file mode 100644
> index 000000000000..1def56207f5d
> --- /dev/null
> +++ b/include/linux/phy/phy-samsung-ufs.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * phy-samsung-ufs.h - Header file for the UFS PHY of Samsung SoC
> + *
> + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> + * Author: Seungwon Jeon <[email protected]>
> + * Author: Alim Akhtar <[email protected]>
> + *
> + */
> +
> +#ifndef _PHY_EXYNOS_UFS_H_
> +#define _PHY_EXYNOS_UFS_H_
> +
> +#include "phy.h"
> +
> +/* description for PHY calibration */
> +enum {
> + /* applicable to any */
> + PWR_DESC_ANY = 0,
> + /* mode */
> + PWR_DESC_PWM = 1,
> + PWR_DESC_HS = 2,
> + /* series */
> + PWR_DESC_SER_A = 1,
> + PWR_DESC_SER_B = 2,
> + /* gear */
> + PWR_DESC_G1 = 1,
> + PWR_DESC_G2 = 2,
> + PWR_DESC_G3 = 3,
> + PWR_DESC_G4 = 4,
> + PWR_DESC_G5 = 5,
> + PWR_DESC_G6 = 6,
> + PWR_DESC_G7 = 7,
> + /* field mask */
> + MD_MASK = 0x3,
> + SR_MASK = 0x3,
> + GR_MASK = 0x7,
> +};
> +
> +#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
> + (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
> +#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
> + (((s) & SR_MASK) << 2) | PWR_DESC_HS)
> +#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
> +#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
> +#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
> +#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
> +#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
> +#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
> +#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
> +#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
> +#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
> +#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
> + PWR_DESC_ANY, PWR_DESC_HS)
> +#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
> + PWR_DESC_ANY, PWR_DESC_PWM)
> +#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
> + PWR_DESC_ANY, PWR_DESC_ANY)
> +#define IS_PWR_MODE_HS(d) (((d) & MD_MASK) == PWR_DESC_HS)
> +#define IS_PWR_MODE_PWM(d) (((d) & MD_MASK) == PWR_DESC_PWM)
> +#define IS_PWR_MODE_ANY(d) ((d) == PWR_MODE_ANY)
> +#define IS_PWR_MODE_HS_ANY(d) ((d) == PWR_MODE_HS_ANY)
> +#define COMP_PWR_MODE(a, b) ((a) == (b))
> +#define COMP_PWR_MODE_GEAR(a, b) ((((a) >> 4) & GR_MASK) == \
> + (((b) >> 4) & GR_MASK))
> +#define COMP_PWR_MODE_SER(a, b) ((((a) >> 2) & SR_MASK) == \
> + (((b) >> 2) & SR_MASK))
> +#define COMP_PWR_MODE_MD(a, b) (((a) & MD_MASK) == ((b) & MD_MASK))
> +
> +#endif /* _PHY_EXYNOS_UFS_H_ */
>
Hi Kishon
> -----Original Message-----
> From: Kishon Vijay Abraham I <[email protected]>
> Sent: 20 March 2020 11:10
> To: Alim Akhtar <[email protected]>; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]
> Subject: Re: [PATCH v3 2/5] phy: samsung-ufs: add UFS PHY driver for samsung
> SoC
>
> Hi Alim,
>
> On 3/19/2020 8:30 PM, Alim Akhtar wrote:
> > This patch introduces Samsung UFS PHY driver. This driver supports to
> > deal with phy calibration and power control according to UFS host
> > driver's behavior.
> >
> > Reviewed-by: Kiwoong Kim <[email protected]>
> > Signed-off-by: Seungwon Jeon <[email protected]>
> > Signed-off-by: Alim Akhtar <[email protected]>
> > Cc: Kishon Vijay Abraham I <[email protected]>
> > ---
> > drivers/phy/samsung/Kconfig | 9 +
> > drivers/phy/samsung/Makefile | 1 +
> > drivers/phy/samsung/phy-exynos7-ufs.h | 85 +++++++
> > drivers/phy/samsung/phy-samsung-ufs.c | 311
> ++++++++++++++++++++++++++
> > drivers/phy/samsung/phy-samsung-ufs.h | 100 +++++++++
> > include/linux/phy/phy-samsung-ufs.h | 70 ++++++
>
> Why is this added in include directory? will it be used by controller driver?
>
Thanks for point this out, as of today it is not used in ufs controller driver. Will move this to driver directory.
> Thanks
> Kishon
> > 6 files changed, 576 insertions(+)
> > create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
> > create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
> > create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
> > create mode 100644 include/linux/phy/phy-samsung-ufs.h
> >
> > diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> > index 9e483d1fdaf2..fc1e3c17f842 100644
> > --- a/drivers/phy/samsung/Kconfig
> > +++ b/drivers/phy/samsung/Kconfig
> > @@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
> > Enable PCIe PHY support for Exynos SoC series.
> > This driver provides PHY interface for Exynos PCIe controller.
> >
> > +config PHY_SAMSUNG_UFS
> > + tristate "SAMSUNG SoC series UFS PHY driver"
> > + depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
> > + select GENERIC_PHY
> > + help
> > + Enable this to support the Samsung UFS PHY driver for
> > + Samsung SoCs. This driver provides the interface for UFS
> > + host controller to do PHY related programming.
> > +
> > config PHY_SAMSUNG_USB2
> > tristate "Samsung USB 2.0 PHY driver"
> > depends on HAS_IOMEM
> > diff --git a/drivers/phy/samsung/Makefile
> > b/drivers/phy/samsung/Makefile index db9b1aa0de6e..3959100fe8a2 100644
> > --- a/drivers/phy/samsung/Makefile
> > +++ b/drivers/phy/samsung/Makefile
> > @@ -2,6 +2,7 @@
> > obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
> > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> > obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> > +obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
> > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
> > phy-exynos-usb2-y += phy-samsung-usb2.o
> > phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-
> usb2.o
> > diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
> > b/drivers/phy/samsung/phy-exynos7-ufs.h
> > new file mode 100644
> > index 000000000000..da981c1ac040
> > --- /dev/null
> > +++ b/drivers/phy/samsung/phy-exynos7-ufs.h
> > @@ -0,0 +1,85 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * UFS PHY driver data for Samsung EXYNOS7 SoC
> > + *
> > + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> > + */
> > +#ifndef _PHY_EXYNOS7_UFS_H_
> > +#define _PHY_EXYNOS7_UFS_H_
> > +
> > +#include "phy-samsung-ufs.h"
> > +
> > +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
> > +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> > +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> > +
> > +/* Calibration for phy initialization */ static const struct
> > +samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> > + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
> > + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
> > + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
> > + PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
> > + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
> > + END_UFS_PHY_CFG
> > +};
> > +
> > +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> > + END_UFS_PHY_CFG
> > +};
> > +
> > +/* Calibration for HS mode series A/B */ static const struct
> > +samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
> > + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
> > + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
> > + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
> > + /* Setting order: 1st(0x16, 2nd(0x15) */
> > + PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
> > + PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
> > + PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
> > + PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
> > + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
> > + PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
> > + PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
> > + PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
> > + END_UFS_PHY_CFG
> > +};
> > +
> > +/* Calibration for HS mode series A/B atfer PMC */ static const
> > +struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
> > + PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
> > + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
> > + END_UFS_PHY_CFG
> > +};
> > +
> > +static const struct samsung_ufs_phy_cfg
> *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
> > + [CFG_PRE_INIT] = exynos7_pre_init_cfg,
> > + [CFG_POST_INIT] = exynos7_post_init_cfg,
> > + [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
> > + [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
> > +};
> > +
> > +static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
> > + .cfg = exynos7_ufs_phy_cfgs,
> > + .isol = {
> > + .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
> > + .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
> > + .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
> > + },
> > +};
> > +
> > +#endif /* _PHY_EXYNOS7_UFS_H_ */
> > diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> > b/drivers/phy/samsung/phy-samsung-ufs.c
> > new file mode 100644
> > index 000000000000..2d5db24de49b
> > --- /dev/null
> > +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> > @@ -0,0 +1,311 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * UFS PHY driver for Samsung SoC
> > + *
> > + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> > + * Author: Seungwon Jeon <[email protected]>
> > + * Author: Alim Akhtar <[email protected]>
> > + *
> > + */
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/of.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/phy/phy-samsung-ufs.h> #include
> > +<linux/platform_device.h> #include <linux/regmap.h>
> > +
> > +#include "phy-samsung-ufs.h"
> > +
> > +#define for_each_phy_lane(phy, i) \
> > + for (i = 0; i < (phy)->lane_cnt; i++) #define for_each_phy_cfg(cfg)
> > +\
> > + for (; (cfg)->id; (cfg)++)
> > +
> > +#define PHY_DEF_LANE_CNT 1
> > +
> > +static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> > + const struct samsung_ufs_phy_cfg *cfg, u8 lane) {
> > + enum {LANE_0, LANE_1}; /* lane index */
> > +
> > + switch (lane) {
> > + case LANE_0:
> > + writel(cfg->val, (phy)->reg_pma + cfg->off_0);
> > + break;
> > + case LANE_1:
> > + if (cfg->id == PHY_TRSV_BLK)
> > + writel(cfg->val, (phy)->reg_pma + cfg->off_1);
> > + break;
> > + }
> > +}
> > +
> > +int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy) {
> > + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> > + const unsigned int timeout_us = 100000;
> > + const unsigned int sleep_us = 10;
> > + u32 val;
> > + int err;
> > +
> > + err = readl_poll_timeout(
> > + ufs_phy->reg_pma +
> PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
> > + val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
> > + if (err) {
> > + dev_err(ufs_phy->dev,
> > + "failed to get phy pll lock acquisition %d\n", err);
> > + goto out;
> > + }
> > +
> > + err = readl_poll_timeout(
> > + ufs_phy->reg_pma +
> PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
> > + val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
> > + if (err) {
> > + dev_err(ufs_phy->dev,
> > + "failed to get phy cdr lock acquisition %d\n", err);
> > + goto out;
> > + }
> > +
> > +out:
> > + return err;
> > +}
> > +
> > +int samsung_ufs_phy_calibrate(struct phy *phy) {
> > + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> > + struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
> > + const struct samsung_ufs_phy_cfg *cfg;
> > + int i;
> > + int err = 0;
> > +
> > + if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
> > + ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
> > + dev_err(ufs_phy->dev, "invalid phy config index %d\n",
> > + ufs_phy-
> >ufs_phy_state);
> > + return -EINVAL;
> > + }
> > +
> > + if (ufs_phy->is_pre_init)
> > + ufs_phy->is_pre_init = false;
> > + if (ufs_phy->is_post_init) {
> > + ufs_phy->is_post_init = false;
> > + ufs_phy->ufs_phy_state = CFG_POST_INIT;
> > + }
> > + if (ufs_phy->is_pre_pmc) {
> > + ufs_phy->is_pre_pmc = false;
> > + ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
> > + }
> > + if (ufs_phy->is_post_pmc) {
> > + ufs_phy->is_post_pmc = false;
> > + ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
> > + }
> > +
> > + switch (ufs_phy->ufs_phy_state) {
> > + case CFG_PRE_INIT:
> > + ufs_phy->is_post_init = true;
> > + break;
> > + case CFG_POST_INIT:
> > + ufs_phy->is_pre_pmc = true;
> > + break;
> > + case CFG_PRE_PWR_HS:
> > + ufs_phy->is_post_pmc = true;
> > + break;
> > + case CFG_POST_PWR_HS:
> > + break;
> > + default:
> > + dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
> > + }
> > +
> > + cfg = cfgs[ufs_phy->ufs_phy_state];
> > + if (!cfg)
> > + goto out;
> > +
> > + for_each_phy_cfg(cfg) {
> > + for_each_phy_lane(ufs_phy, i) {
> > + samsung_ufs_phy_config(ufs_phy, cfg, i);
> > + }
> > + }
> > +
> > + if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
> > + err = samsung_ufs_phy_wait_for_lock_acq(phy);
> > +out:
> > + return err;
> > +}
> > +
> > +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) {
> > + struct clk *child, *parent;
> > +
> > + child = devm_clk_get(phy->dev, "ref_clk");
> > + if (IS_ERR(child))
> > + dev_err(phy->dev, "failed to get ref_clk clock\n");
> > + else
> > + phy->ref_clk = child;
> > +
> > + parent = devm_clk_get(phy->dev, "ref_clk_parent");
> > + if (IS_ERR(parent))
> > + dev_err(phy->dev, "failed to get ref_clk_parent clock\n");
> > + else
> > + phy->ref_clk_parent = parent;
> > +
> > + return clk_set_parent(child, parent); }
> > +
> > +static int samsung_ufs_phy_init(struct phy *phy) {
> > + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> > +
> > + _phy->lane_cnt = phy->attrs.bus_width;
> > + _phy->ufs_phy_state = CFG_PRE_INIT;
> > +
> > + _phy->is_pre_init = true;
> > + _phy->is_post_init = false;
> > + _phy->is_pre_pmc = false;
> > + _phy->is_post_pmc = false;
> > +
> > + samsung_ufs_phy_clks_init(_phy);
> > +
> > + samsung_ufs_phy_calibrate(phy);
> > +
> > + return 0;
> > +}
> > +
> > +static int samsung_ufs_phy_power_on(struct phy *phy) {
> > + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> > + int ret;
> > +
> > + ret = clk_prepare_enable(_phy->ref_clk);
> > + if (ret) {
> > + dev_err(_phy->dev, "%s: ref_clk enable failed %d\n",
> > + __func__, ret);
> > + return ret;
> > + }
> > +
> > + samsung_ufs_phy_ctrl_isol(_phy, false);
> > + return 0;
> > +}
> > +
> > +static int samsung_ufs_phy_power_off(struct phy *phy) {
> > + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> > +
> > + samsung_ufs_phy_ctrl_isol(_phy, true);
> > + clk_disable_unprepare(_phy->ref_clk);
> > + return 0;
> > +}
> > +
> > +static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
> > + enum phy_mode mode, int submode) {
> > + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(generic_phy);
> > +
> > + _phy->mode = PHY_MODE_INVALID;
> > +
> > + if (mode > 0)
> > + _phy->mode = mode;
> > +
> > + return 0;
> > +}
> > +
> > +static struct phy_ops samsung_ufs_phy_ops = {
> > + .init = samsung_ufs_phy_init,
> > + .power_on = samsung_ufs_phy_power_on,
> > + .power_off = samsung_ufs_phy_power_off,
> > + .calibrate = samsung_ufs_phy_calibrate,
> > + .set_mode = samsung_ufs_phy_set_mode,
> > +}
> > +;
> > +static const struct of_device_id samsung_ufs_phy_match[];
> > +
> > +static int samsung_ufs_phy_probe(struct platform_device *pdev) {
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + const struct of_device_id *match;
> > + struct samsung_ufs_phy *phy;
> > + struct phy *gen_phy;
> > + struct phy_provider *phy_provider;
> > + const struct samsung_ufs_phy_drvdata *drvdata;
> > + int err = 0;
> > +
> > + match = of_match_node(samsung_ufs_phy_match, dev->of_node);
> > + if (!match) {
> > + err = -EINVAL;
> > + dev_err(dev, "failed to get match_node\n");
> > + goto out;
> > + }
> > +
> > + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> > + if (!phy) {
> > + err = -ENOMEM;
> > + goto out;
> > + }
> > +
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy-
> pma");
> > + phy->reg_pma = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(phy->reg_pma)) {
> > + err = PTR_ERR(phy->reg_pma);
> > + goto out;
> > + }
> > +
> > + phy->reg_pmu = syscon_regmap_lookup_by_phandle(
> > + dev->of_node, "samsung,pmu-syscon");
> > + if (IS_ERR(phy->reg_pmu)) {
> > + err = PTR_ERR(phy->reg_pmu);
> > + dev_err(dev, "failed syscon remap for pmu\n");
> > + goto out;
> > + }
> > +
> > + gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
> > + if (IS_ERR(gen_phy)) {
> > + err = PTR_ERR(gen_phy);
> > + dev_err(dev, "failed to create PHY for ufs-phy\n");
> > + goto out;
> > + }
> > +
> > + drvdata = match->data;
> > + phy->dev = dev;
> > + phy->drvdata = drvdata;
> > + phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
> > + phy->isol = &drvdata->isol;
> > + phy->lane_cnt = PHY_DEF_LANE_CNT;
> > +
> > + phy_set_drvdata(gen_phy, phy);
> > +
> > + phy_provider = devm_of_phy_provider_register(dev,
> of_phy_simple_xlate);
> > + if (IS_ERR(phy_provider)) {
> > + err = PTR_ERR(phy_provider);
> > + dev_err(dev, "failed to register phy-provider\n");
> > + goto out;
> > + }
> > +out:
> > + return err;
> > +}
> > +
> > +static const struct of_device_id samsung_ufs_phy_match[] = {
> > + {
> > + .compatible = "samsung,exynos7-ufs-phy",
> > + .data = &exynos7_ufs_phy,
> > + },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
> > +
> > +static struct platform_driver samsung_ufs_phy_driver = {
> > + .probe = samsung_ufs_phy_probe,
> > + .driver = {
> > + .name = "samsung-ufs-phy",
> > + .of_match_table = samsung_ufs_phy_match,
> > + },
> > +};
> > +module_platform_driver(samsung_ufs_phy_driver);
> > +MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
> > +MODULE_AUTHOR("Seungwon Jeon <[email protected]>");
> > +MODULE_AUTHOR("Alim Akhtar <[email protected]>");
> > +MODULE_LICENSE("GPL v2");
> > diff --git a/drivers/phy/samsung/phy-samsung-ufs.h
> > b/drivers/phy/samsung/phy-samsung-ufs.h
> > new file mode 100644
> > index 000000000000..d0ae2b416b2b
> > --- /dev/null
> > +++ b/drivers/phy/samsung/phy-samsung-ufs.h
> > @@ -0,0 +1,100 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * UFS PHY driver for Samsung EXYNOS SoC
> > + *
> > + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> > + * Author: Seungwon Jeon <[email protected]>
> > + * Author: Alim Akhtar <[email protected]>
> > + *
> > + */
> > +#ifndef _PHY_SAMSUNG_UFS_
> > +#define _PHY_SAMSUNG_UFS_
> > +
> > +#define PHY_COMN_BLK 1
> > +#define PHY_TRSV_BLK 2
> > +#define END_UFS_PHY_CFG { 0 }
> > +#define PHY_TRSV_CH_OFFSET 0x30
> > +#define PHY_APB_ADDR(off) ((off) << 2)
> > +
> > +#define PHY_COMN_REG_CFG(o, v, d) { \
> > + .off_0 = PHY_APB_ADDR((o)), \
> > + .off_1 = 0, \
> > + .val = (v), \
> > + .desc = (d), \
> > + .id = PHY_COMN_BLK, \
> > +}
> > +
> > +#define PHY_TRSV_REG_CFG(o, v, d) { \
> > + .off_0 = PHY_APB_ADDR((o)), \
> > + .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
> > + .val = (v), \
> > + .desc = (d), \
> > + .id = PHY_TRSV_BLK, \
> > +}
> > +
> > +/* UFS PHY registers */
> > +#define PHY_PLL_LOCK_STATUS 0x1e
> > +#define PHY_CDR_LOCK_STATUS 0x5e
> > +
> > +#define PHY_PLL_LOCK_BIT BIT(5)
> > +#define PHY_CDR_LOCK_BIT BIT(4)
> > +
> > +/* PHY calibration point/state */
> > +enum {
> > + CFG_PRE_INIT,
> > + CFG_POST_INIT,
> > + CFG_PRE_PWR_HS,
> > + CFG_POST_PWR_HS,
> > + CFG_TAG_MAX,
> > +};
> > +
> > +struct samsung_ufs_phy_cfg {
> > + u32 off_0;
> > + u32 off_1;
> > + u32 val;
> > + u8 desc;
> > + u8 id;
> > +};
> > +
> > +struct samsung_ufs_phy_drvdata {
> > + const struct samsung_ufs_phy_cfg **cfg;
> > + struct pmu_isol {
> > + u32 offset;
> > + u32 mask;
> > + u32 en;
> > + } isol;
> > +};
> > +
> > +struct samsung_ufs_phy {
> > + struct device *dev;
> > + void __iomem *reg_pma;
> > + struct regmap *reg_pmu;
> > + struct clk *ref_clk;
> > + struct clk *ref_clk_parent;
> > + const struct samsung_ufs_phy_drvdata *drvdata;
> > + struct samsung_ufs_phy_cfg **cfg;
> > + const struct pmu_isol *isol;
> > + u8 lane_cnt;
> > + int ufs_phy_state;
> > + enum phy_mode mode;
> > + bool is_pre_init;
> > + bool is_post_init;
> > + bool is_pre_pmc;
> > + bool is_post_pmc;
> > +};
> > +
> > +static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy
> > +*phy) {
> > + return (struct samsung_ufs_phy *)phy_get_drvdata(phy); }
> > +
> > +static inline void samsung_ufs_phy_ctrl_isol(
> > + struct samsung_ufs_phy *phy, u32 isol) {
> > + regmap_update_bits(phy->reg_pmu, phy->isol->offset,
> > + phy->isol->mask, isol ? 0 : phy->isol->en); }
> > +
> > +#include "phy-exynos7-ufs.h"
> > +
> > +#endif /* _PHY_SAMSUNG_UFS_ */
> > diff --git a/include/linux/phy/phy-samsung-ufs.h
> > b/include/linux/phy/phy-samsung-ufs.h
> > new file mode 100644
> > index 000000000000..1def56207f5d
> > --- /dev/null
> > +++ b/include/linux/phy/phy-samsung-ufs.h
> > @@ -0,0 +1,70 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * phy-samsung-ufs.h - Header file for the UFS PHY of Samsung SoC
> > + *
> > + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
> > + * Author: Seungwon Jeon <[email protected]>
> > + * Author: Alim Akhtar <[email protected]>
> > + *
> > + */
> > +
> > +#ifndef _PHY_EXYNOS_UFS_H_
> > +#define _PHY_EXYNOS_UFS_H_
> > +
> > +#include "phy.h"
> > +
> > +/* description for PHY calibration */ enum {
> > + /* applicable to any */
> > + PWR_DESC_ANY = 0,
> > + /* mode */
> > + PWR_DESC_PWM = 1,
> > + PWR_DESC_HS = 2,
> > + /* series */
> > + PWR_DESC_SER_A = 1,
> > + PWR_DESC_SER_B = 2,
> > + /* gear */
> > + PWR_DESC_G1 = 1,
> > + PWR_DESC_G2 = 2,
> > + PWR_DESC_G3 = 3,
> > + PWR_DESC_G4 = 4,
> > + PWR_DESC_G5 = 5,
> > + PWR_DESC_G6 = 6,
> > + PWR_DESC_G7 = 7,
> > + /* field mask */
> > + MD_MASK = 0x3,
> > + SR_MASK = 0x3,
> > + GR_MASK = 0x7,
> > +};
> > +
> > +#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
> > + (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
> > +#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
> > + (((s) & SR_MASK) << 2) | PWR_DESC_HS)
> > +#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1,
> PWR_DESC_ANY)
> > +#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1,
> PWR_DESC_SER_A)
> > +#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1,
> PWR_DESC_SER_B)
> > +#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2,
> PWR_DESC_ANY)
> > +#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2,
> PWR_DESC_SER_A)
> > +#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2,
> PWR_DESC_SER_B)
> > +#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3,
> PWR_DESC_ANY)
> > +#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3,
> PWR_DESC_SER_A)
> > +#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3,
> PWR_DESC_SER_B)
> > +#define PWR_MODE_HS_ANY
> PWR_MODE(PWR_DESC_ANY,\
> > + PWR_DESC_ANY, PWR_DESC_HS)
> > +#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
> > + PWR_DESC_ANY, PWR_DESC_PWM)
> > +#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
> > + PWR_DESC_ANY, PWR_DESC_ANY)
> > +#define IS_PWR_MODE_HS(d) (((d) & MD_MASK) == PWR_DESC_HS)
> > +#define IS_PWR_MODE_PWM(d) (((d) & MD_MASK) ==
> PWR_DESC_PWM)
> > +#define IS_PWR_MODE_ANY(d) ((d) == PWR_MODE_ANY)
> > +#define IS_PWR_MODE_HS_ANY(d) ((d) == PWR_MODE_HS_ANY)
> > +#define COMP_PWR_MODE(a, b) ((a) == (b))
> > +#define COMP_PWR_MODE_GEAR(a, b) ((((a) >> 4) & GR_MASK) == \
> > + (((b) >> 4) & GR_MASK))
> > +#define COMP_PWR_MODE_SER(a, b) ((((a) >> 2) & SR_MASK)
> == \
> > + (((b) >> 2) & SR_MASK))
> > +#define COMP_PWR_MODE_MD(a, b) (((a) & MD_MASK) ==
> ((b) & MD_MASK))
> > +
> > +#endif /* _PHY_EXYNOS_UFS_H_ */
> >
Hello Pawel
Thanks for helping in testing.
> -----Original Message-----
> From: Paweł Chmiel <[email protected]>
> Sent: 20 March 2020 01:12
> To: Alim Akhtar <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH v3 0/5] exynos-ufs: Add support for UFS HCI
>
> On Thu, 2020-03-19 at 20:30 +0530, Alim Akhtar wrote:
> > This patch-set introduces UFS (Universal Flash Storage) host
> > controller support for Samsung family SoC. Mostly, it consists of UFS PHY and
> host specific driver.
> >
> > - Changes since v2:
> > * fixed build warning by kbuild test robot
> > * Added Reported-by tags
> >
> > - Changes since v1:
> > * fixed make dt_binding_check error as pointed by Rob
> > * Addressed Krzysztof's review comments
> > * Added Reviewed-by tags
> >
> >
> > patch 1/5: define devicetree bindings for UFS PHY patch 2/5: Adds UFS
> > PHY driver patch 3/5: define devicetree bindings for UFS HCI patch
> > 4/5: Adds Samsung UFS HCI driver patch 5/5: Enabled UFS on exynos7
> > platform
> Hi
> Is this compatible with Exynos7420? Looking at u-boot source code, there is
> Espresso7420 - isn't it the same device? Also this driver looks very similar to the
> one from vendor kernel sources (for my device).
>
Exynos7 and Exynos7420 are compatible and belong to same Exynos SoC series (but there are some fine differences)
> I did tried to run this on my Exynos7420 based device (Samsung S6 Edge
> phone) with 5.6-rc6, to get any storage working (since it doesn't have sdcard
> slot).
>
I think this should work on S6 Edge, but not entirely sure, as I am not aware of the S6 H/W schematic, specially PMIC connection.
> At first i got error in exynos_ufs_config_smu. Looking at vendor sources, on my
> device only secureos is able to write to those registers so i fixed it by using smc
> calls and driver probes fine. Will this be also supported by driver (maybe in
> future)?
>
> But now got another error
> [ 1.610464] exynos-ufshc 15570000.ufs: ufshcd_intr: Unhandled
> interrupt 0x00000000
> [ 1.610629] host_regs: 00000000: 0383ff0f 00000000 00000200 00000000
> [ 1.610747] host_regs: 00000010: 00000101 00007fce 00000000 00000000
> [ 1.610863] host_regs: 00000020: 00000000 00030e75 00000000 00000000
> [ 1.614727] host_regs: 00000030: 0000000f 00000000 00000000 00000000
> [ 1.621061] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [ 1.627396] host_regs: 00000050: f8c37000 00000000 00000001 00000000
> [ 1.633730] host_regs: 00000060: 00000001 00000000 00000000 00000000
> [ 1.640065] host_regs: 00000070: f9644000 00000000 00000000 00000000
> [ 1.646400] host_regs: 00000080: 00000001 00000000 00000000 00000000
> [ 1.652734] host_regs: 00000090: 00000002 95290000 00000000 00000000
> [ 1.747649] exynos-ufshc 15570000.ufs: ufshcd_intr: Unhandled
> interrupt 0x00000000
> [ 1.747807] host_regs: 00000000: 0383ff0f 00000000 00000200 00000000
> [ 1.747924] host_regs: 00000010: 00000101 00007fce 00000000 00000000
> [ 1.748041] host_regs: 00000020: 00000000 00030e75 00000000 00000000
> [ 1.751909] host_regs: 00000030: 0000000f 00000000 00000000 00000000
> [ 1.758244] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [ 1.764578] host_regs: 00000050: f8c37000 00000000 00000001 00000000
> [ 1.770913] host_regs: 00000060: 00000001 00000000 00000000 00000000
> [ 1.777248] host_regs: 00000070: f9644000 00000000 00000000 00000000
> [ 1.783582] host_regs: 00000080: 00000001 00000000 00000000 00000000
> [ 1.789917] host_regs: 00000090: 00000002 95290000 00000000 00000000
> [ 1.884841] exynos-ufshc 15570000.ufs: ufshcd_intr: Unhandled
> interrupt 0x00000000
> [ 1.884999] host_regs: 00000000: 0383ff0f 00000000 00000200 00000000
> [ 1.885116] host_regs: 00000010: 00000101 00007fce 00000000 00000000
> [ 1.885233] host_regs: 00000020: 00000000 00030e75 00000000 00000000
> [ 1.889100] host_regs: 00000030: 0000000f 00000000 00000000 00000000
> [ 1.895435] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [ 1.901770] host_regs: 00000050: f8c37000 00000000 00000001 00000000
> [ 1.908104] host_regs: 00000060: 00000001 00000000 00000000 00000000
> [ 1.914439] host_regs: 00000070: f9644000 00000000 00000000 00000000
> [ 1.920773] host_regs: 00000080: 00000001 00000000 00000000 00000000
> [ 1.927108] host_regs: 00000090: 00000002 95290000 00000000 00000000
> [ 2.998155] exynos-ufshc 15570000.ufs: ufshcd_query_flag: Sending
> flag query for idn 1 failed, err = -11
> [ 4.502138] exynos-ufshc 15570000.ufs: ufshcd_query_flag: Sending
> flag query for idn 1 failed, err = -11
> [ 6.006137] exynos-ufshc 15570000.ufs: ufshcd_query_flag: Sending
> flag query for idn 1 failed, err = -11
> [ 6.006311] exynos-ufshc 15570000.ufs: ufshcd_query_flag_retry:
> query attribute, opcode 5, idn 1, failed with error -11 after 3 retires
> [ 6.006545] exynos-ufshc 15570000.ufs: ufshcd_complete_dev_init
> reading fDeviceInit flag failed with error -11
>
> Do You have any idea what could be wrong?
>
To me, It looks like UFS device is not powered ON or properly Reseted, I have seen this kind of issues in past and
AFAIR, fix was to keep the PMIC rail which was hook to device RESET_N always-on.
> Thanks
> >
> > Note: This series is based on Linux-5.6-rc6 (commit: fb33c6510d55)
> >
> >
> > Alim Akhtar (5):
> > dt-bindings: phy: Document Samsung UFS PHY bindings
> > phy: samsung-ufs: add UFS PHY driver for samsung SoC
> > Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
> > controller
> > scsi: ufs-exynos: add UFS host support for Exynos SoCs
> > arm64: dts: Add node for ufs exynos7
> >
> > .../bindings/phy/samsung,ufs-phy.yaml | 62 +
> > .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
> > .../boot/dts/exynos/exynos7-espresso.dts | 16 +
> > arch/arm64/boot/dts/exynos/exynos7.dtsi | 44 +-
> > drivers/phy/samsung/Kconfig | 9 +
> > drivers/phy/samsung/Makefile | 1 +
> > drivers/phy/samsung/phy-exynos7-ufs.h | 85 +
> > drivers/phy/samsung/phy-samsung-ufs.c | 311 ++++
> > drivers/phy/samsung/phy-samsung-ufs.h | 100 ++
> > drivers/scsi/ufs/Kconfig | 12 +
> > drivers/scsi/ufs/Makefile | 1 +
> > drivers/scsi/ufs/ufs-exynos.c | 1399 +++++++++++++++++
> > drivers/scsi/ufs/ufs-exynos.h | 268 ++++
> > drivers/scsi/ufs/unipro.h | 41 +
> > include/linux/phy/phy-samsung-ufs.h | 70 +
> > 15 files changed, 2521 insertions(+), 2 deletions(-) create mode
> > 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> > create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
> > create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
> > create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
> > create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644
> > drivers/scsi/ufs/ufs-exynos.h create mode 100644
> > include/linux/phy/phy-samsung-ufs.h
> >