SDCC clocks must be rounded down to avoid overclocking the controller.
Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Mantas Pucka <[email protected]>
---
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 3f9c2f61a5d9..5c5d1b04ea7a 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1654,7 +1654,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = 4,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
--
2.7.4
IPQ6018 has a sdhci-msm compatible MMC controller. Add the appropriate
compatible to the documentation.
Signed-off-by: Mantas Pucka <[email protected]>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 4f2d9e8127dd..5ad846b724f3 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -36,6 +36,7 @@ properties:
- enum:
- qcom,ipq5018-sdhci
- qcom,ipq5332-sdhci
+ - qcom,ipq6018-sdhci
- qcom,ipq9574-sdhci
- qcom,qcm2290-sdhci
- qcom,qcs404-sdhci
--
2.7.4
IPQ6018 has one SD/eMMC controller, add node for it.
Signed-off-by: Mantas Pucka <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9ff4e9d45065..b129b23d68b1 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -414,6 +414,29 @@
};
};
+ sdhc_1: mmc@7804000 {
+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x07804000 0x0 0x1000>,
+ <0x0 0x07805000 0x0 0x1000>,
+ <0x0 0x07808000 0x0 0x2000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface", "core", "xo", "ice";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+ supports-cqe;
+ bus-width = <8>;
+ status = "disabled";
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;
--
2.7.4
Quoting Mantas Pucka (2023-04-24 05:13:30)
> SDCC clocks must be rounded down to avoid overclocking the controller.
>
> Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
>
There should be no extra newline here.
> Signed-off-by: Mantas Pucka <[email protected]>
On Mon, 24 Apr 2023 15:13:31 +0300, Mantas Pucka wrote:
> IPQ6018 has a sdhci-msm compatible MMC controller. Add the appropriate
> compatible to the documentation.
>
> Signed-off-by: Mantas Pucka <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Mon, 24 Apr 2023 at 14:14, Mantas Pucka <[email protected]> wrote:
>
> IPQ6018 has a sdhci-msm compatible MMC controller. Add the appropriate
> compatible to the documentation.
>
> Signed-off-by: Mantas Pucka <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> index 4f2d9e8127dd..5ad846b724f3 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
> @@ -36,6 +36,7 @@ properties:
> - enum:
> - qcom,ipq5018-sdhci
> - qcom,ipq5332-sdhci
> + - qcom,ipq6018-sdhci
> - qcom,ipq9574-sdhci
> - qcom,qcm2290-sdhci
> - qcom,qcs404-sdhci
> --
> 2.7.4
>
On 24. 04. 2023. 14:13, Mantas Pucka wrote:
> IPQ6018 has one SD/eMMC controller, add node for it.
>
> Signed-off-by: Mantas Pucka <[email protected]>
Tested-by: Robert Marko <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 9ff4e9d45065..b129b23d68b1 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -414,6 +414,29 @@
> };
> };
>
> + sdhc_1: mmc@7804000 {
> + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x07804000 0x0 0x1000>,
> + <0x0 0x07805000 0x0 0x1000>,
> + <0x0 0x07808000 0x0 0x2000>;
> + reg-names = "hc", "cqhci", "ice";
> +
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> + clock-names = "iface", "core", "xo", "ice";
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> + supports-cqe;
> + bus-width = <8>;
> + status = "disabled";
> + };
> +
> blsp_dma: dma-controller@7884000 {
> compatible = "qcom,bam-v1.7.0";
> reg = <0x0 0x07884000 0x0 0x2b000>;