Changes in patch v2:
Addressed review comments in patch v1
v1 - https://lkml.org/lkml/2020/7/20/96
Rajesh Gumasta (4):
dt-bindings: dma: Add DT binding document
dmaengine: tegra: Add Tegra GPC DMA driver
arm64: configs: enable tegra gpc dma
arm64: tegra: Add GPCDMA node in dt
.../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 +
arch/arm64/configs/defconfig | 1 +
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-gpc-dma.c | 1472 ++++++++++++++++++++
8 files changed, 1679 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
create mode 100644 drivers/dma/tegra-gpc-dma.c
--
2.7.4
Add DT binding document for Nvidia Tegra GPCDMA controller.
Signed-off-by: Rajesh Gumasta <[email protected]>
---
.../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++++++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
new file mode 100644
index 0000000..39827ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra-gpc-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nvidia Tegra GPC DMA Controller Device Tree Bindings
+
+description: |
+ Tegra GPC DMA controller is a general purpose dma used for faster data
+ transfers between memory to memory, memory to device and device to memory.
+ Terms 'dma' and 'gpcdma' can be used interchangeably.
+
+maintainers:
+ - Jon Hunter <[email protected]>
+ - Rajesh Gumasta <[email protected]>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 1
+
+ compatible:
+ - enum:
+ - nvidia,tegra186-gpcdma
+ - nvidia,tegra194-gpcdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: gpcdma
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+ - "#dma-cells"
+ - iommus
+
+examples:
+ - |
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x2600000 0x0 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA_SID_GPCDMA_0>;
+ dma-coherent;
+ };
+
+...
--
2.7.4
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
supports dma transfers between memory to memory, IO peripheral to memory
and memory to IO peripheral.
Signed-off-by: Pavan Kunapuli <[email protected]>
Signed-off-by: Rajesh Gumasta <[email protected]>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-gpc-dma.c | 1472 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1485 insertions(+)
create mode 100644 drivers/dma/tegra-gpc-dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index e9ed916..84b3a0a 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -639,6 +639,18 @@ config TEGRA210_ADMA
peripheral and vice versa. It does not support memory to
memory data transfer.
+config TEGRA_GPC_DMA
+ tristate "NVIDIA Tegra GPC DMA support"
+ depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
+ driver. The DMA controller has multiple DMA channels which can
+ be configured for different peripherals like UART, SPI, etc
+ which are on APB bus.
+ This DMA controller transfers data from memory to peripheral FIFO
+ or vice versa. It also supports memory to memory data transfer.
+
config TIMB_DMA
tristate "Timberdale FPGA DMA support"
depends on MFD_TIMBERDALE || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index e60f813..43e3a6e 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
+obj-$(CONFIG_TEGRA_GPC_DMA) += tegra-gpc-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o
diff --git a/drivers/dma/tegra-gpc-dma.c b/drivers/dma/tegra-gpc-dma.c
new file mode 100644
index 0000000..723b352
--- /dev/null
+++ b/drivers/dma/tegra-gpc-dma.c
@@ -0,0 +1,1472 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller.
+ *
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <dt-bindings/memory/tegra186-mc.h>
+#include "virt-dma.h"
+
+/* CSR register */
+#define TEGRA_GPCDMA_CHAN_CSR 0x00
+#define TEGRA_GPCDMA_CSR_ENB BIT(31)
+#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
+#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
+#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO (0 << 24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO BIT(24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO BIT(25)
+#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO GENMASK(25, 24)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC (0 << 21)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC BIT(21)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC BIT(22)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC GENMASK(22, 21)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM BIT(23)
+#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT GENMASK(23, 22)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_SHIFT 16
+#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED BIT(18)
+#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
+#define TEGRA_GPCDMA_CSR_WEIGHT_SHIFT 10
+
+/* STATUS register */
+#define TEGRA_GPCDMA_CHAN_STATUS 0x004
+#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
+#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
+#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
+#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
+#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
+#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
+#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
+
+#define TEGRA_GPCDMA_CHAN_CSRE 0x008
+#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
+
+/* Source address */
+#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
+
+/* Destination address */
+#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
+
+/* High address pointer */
+#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
+#define TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_SHIFT 0
+#define TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_MASK 0xFF
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_SHIFT 16
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_MASK 0xFF
+
+/* MC sequence register */
+#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
+#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
+#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT_SHIFT 25
+#define TEGRA_GPCDMA_MCSEQ_BURST_2 (0 << 23)
+#define TEGRA_GPCDMA_MCSEQ_BURST_16 GENMASK(24, 23)
+#define TEGRA_GPCDMA_MCSEQ_WRAP1_SHIFT 20
+#define TEGRA_GPCDMA_MCSEQ_WRAP0_SHIFT 17
+#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
+#define TEGRA_GPCDMA_MCSEQ_MC_PROT_SHIFT 14
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_SHIFT 7
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT 0
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK 0x7F
+
+/* MMIO sequence register */
+#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
+#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 (0 << 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 BIT(28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 BIT(29)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_64 GENMASK(29, 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_128 BIT(30)
+#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_1 (0 << 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_2 BIT(23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_4 GENMASK(24, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_8 GENMASK(25, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_16 GENMASK(26, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID_SHIFT 19
+#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD_SHIFT 16
+#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT_SHIFT 7
+
+/* Channel WCOUNT */
+#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
+
+/* Transfer count */
+#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
+
+/* DMA byte count status */
+#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
+
+/* Error Status Register */
+#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT (8)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK (0xF)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
+ ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
+ TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
+#define TEGRA_DMA_BM_FIFO_FULL_ERR (0xF)
+#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR (0xE)
+#define TEGRA_DMA_PERIPH_ID_ERR (0xD)
+#define TEGRA_DMA_STREAM_ID_ERR (0xC)
+#define TEGRA_DMA_MC_SLAVE_ERR (0xB)
+#define TEGRA_DMA_MMIO_SLAVE_ERR (0xA)
+
+/* Fixed Pattern */
+#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
+
+#define TEGRA_GPCDMA_CHAN_TZ 0x38
+#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
+#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
+
+#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
+#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
+
+/*
+ * If any burst is in flight and DMA paused then this is the time to complete
+ * on-flight burst and update DMA status register.
+ */
+#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
+#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
+
+/* Channel base address offset from GPCDMA base address */
+#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
+
+struct tegra_dma;
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @hw_support_pause: DMA HW engine support pause of the channel.
+ */
+struct tegra_dma_chip_data {
+ int nr_channels;
+ int channel_reg_size;
+ int max_dma_count;
+ bool hw_support_pause;
+};
+
+/* DMA channel registers */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long src_ptr;
+ unsigned long dst_ptr;
+ unsigned long high_addr_ptr;
+ unsigned long mc_seq;
+ unsigned long mmio_seq;
+ unsigned long wcount;
+ unsigned long fixed_pattern;
+};
+
+/*
+ * tegra_dma_sg_req: Dma request details to configure hardware. This
+ * contains the details for one transfer to configure DMA hw.
+ * The client's request for data transfer can be broken into multiple
+ * sub-transfer as per requester details and hw support.
+ * This sub transfer get added in the list of transfer and point to Tegra
+ * DMA descriptor which manages the transfer details.
+ */
+struct tegra_dma_sg_req {
+ struct tegra_dma_channel_regs ch_regs;
+ int req_len;
+ bool configured;
+ bool last_sg;
+ struct list_head node;
+ struct tegra_dma_desc *dma_desc;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
+ * manage client request and keep track of transfer status, callbacks
+ * and request counts etc.
+ */
+struct tegra_dma_desc {
+ struct virt_dma_desc vd;
+ int bytes_requested;
+ int bytes_transferred;
+ struct tegra_dma_channel *tdc;
+};
+
+struct tegra_dma_channel;
+
+typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
+ bool to_terminate);
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct virt_dma_chan vc;
+ struct tegra_dma_desc *dma_desc;
+ struct tegra_dma_desc *pending_dma_desc;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ unsigned long chan_base_offset;
+ raw_spinlock_t lock;
+ bool busy;
+ bool is_pending;
+ struct tegra_dma *tdma;
+ struct list_head pending_sg_req;
+ dma_isr_handler isr_handler;
+ int slave_id;
+ struct dma_slave_config dma_sconfig;
+ struct tegra_dma_channel_regs channel_reg;
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ struct reset_control *rst;
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, vc.chan);
+}
+
+static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct tegra_dma_desc, vd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return tdc->vc.chan.device->dev;
+}
+
+static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
+{
+ pr_info("DMA Channel %d name %s register dump:\n",
+ tdc->id, tdc->name);
+ pr_info("CSR %x STA %x CSRE %x SRC %x DST %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
+ );
+ pr_info("MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
+ );
+ pr_info("DMA ERR_STA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+}
+
+static void tegra_dma_desc_free(struct virt_dma_desc *vd)
+{
+ struct tegra_dma_desc *dma_desc = vd_to_tegra_dma_desc(vd);
+ struct tegra_dma_channel *tdc = dma_desc->tdc;
+ unsigned long flags;
+
+ if (!dma_desc)
+ return;
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ kfree(dma_desc);
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ if (!list_empty(&tdc->pending_sg_req)) {
+ dev_err(tdc2dev(tdc), "Configuration not allowed\n");
+ return -EBUSY;
+ }
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ if (tdc->slave_id == -1)
+ tdc->slave_id = sconfig->slave_id;
+ tdc->config_init = true;
+ return 0;
+}
+
+static int tegra_dma_pause(struct tegra_dma_channel *tdc)
+{
+ u32 val;
+ int ret;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
+
+ /* Wait until busy bit is de-asserted */
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ val,
+ !(val & TEGRA_GPCDMA_STATUS_BUSY),
+ TEGRA_GPCDMA_BURST_COMPLETE_TIME,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+
+ if (ret) {
+ dev_err(tdc2dev(tdc), "DMA pause timed out\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static void tegra_dma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 csr, status;
+
+ csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ /* Disable interrupts */
+ csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
+
+ /* Disable DMA */
+ csr &= ~TEGRA_GPCDMA_CSR_ENB;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+
+ /* Clear interrupt status if it is there */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ }
+ tdc->busy = false;
+}
+
+static void tegra_dma_start(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req)
+{
+ struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+
+ /* Start DMA */
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+}
+
+static void tdc_start_head_req(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_sg_req *sg_req;
+ struct virt_dma_desc *vdesc;
+
+ if (list_empty(&tdc->pending_sg_req))
+ return;
+
+ if (tdc->is_pending)
+ return;
+
+ vdesc = vchan_next_desc(&tdc->vc);
+ if (!vdesc)
+ return;
+ list_del(&vdesc->node);
+ tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
+ tdc->is_pending = true;
+ tdc->dma_desc->tdc = tdc;
+ sg_req = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sg_req), node);
+ tegra_dma_start(tdc, sg_req);
+ sg_req->configured = true;
+ tdc->busy = true;
+}
+
+static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_sg_req *sgreq;
+
+ while (!list_empty(&tdc->pending_sg_req)) {
+ sgreq = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sgreq), node);
+ list_del(&sgreq->node);
+ kfree(sgreq);
+ }
+ tdc->isr_handler = NULL;
+}
+
+static void handle_once_dma_done(struct tegra_dma_channel *tdc,
+ bool to_terminate)
+{
+ struct tegra_dma_desc *dma_desc;
+ struct tegra_dma_sg_req *sgreq;
+
+ tdc->busy = false;
+ sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
+ dma_desc = sgreq->dma_desc;
+ dma_desc->bytes_transferred += sgreq->req_len;
+
+ if (sgreq->last_sg) {
+ vchan_cookie_complete(&tdc->dma_desc->vd);
+ tdc->is_pending = false;
+ tdc->dma_desc = NULL;
+ }
+ list_del(&sgreq->node);
+ kfree(sgreq);
+
+ if (to_terminate || list_empty(&tdc->pending_sg_req))
+ return;
+
+ tdc_start_head_req(tdc);
+}
+
+static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
+ unsigned int err_status)
+{
+ switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
+ case TEGRA_DMA_BM_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d bm fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d peripheral fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal peripheral id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_STREAM_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal stream id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MC_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mc slave error\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MMIO_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mmio slave error\n", tdc->id);
+ break;
+
+ default:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d security violation %x\n", tdc->id,
+ err_status);
+ }
+}
+
+static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ unsigned int err_status;
+ unsigned long status;
+
+ raw_spin_lock(&tdc->lock);
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ err_status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+
+ if (err_status) {
+ tegra_dma_chan_decode_error(tdc, err_status);
+ tegra_dma_dump_chan_regs(tdc);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ }
+
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ TEGRA_GPCDMA_STATUS_ISE_EOC);
+ if (tdc->isr_handler) {
+ tdc->isr_handler(tdc, false);
+ } else {
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d: status %lx ISR handler absent!\n",
+ tdc->id, status);
+ tegra_dma_dump_chan_regs(tdc);
+ }
+ raw_spin_unlock(&tdc->lock);
+ return IRQ_HANDLED;
+ }
+
+ raw_spin_unlock(&tdc->lock);
+ return IRQ_NONE;
+}
+
+static void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ if (list_empty(&tdc->pending_sg_req)) {
+ dev_err(tdc2dev(tdc), "No DMA request\n");
+ goto end;
+ }
+
+ if (!tdc->busy)
+ if (vchan_issue_pending(&tdc->vc))
+ tdc_start_head_req(tdc);
+
+end:
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
+{
+ u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
+ csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+}
+
+static int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_sg_req *sgreq;
+ unsigned long wcount = 0;
+ unsigned long status;
+ unsigned long flags;
+ bool was_busy;
+ int err;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ if (list_empty(&tdc->pending_sg_req)) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ if (tdc->tdma->chip_data->hw_support_pause) {
+ err = tegra_dma_pause(tdc);
+ if (err) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return err;
+ }
+ } else {
+ /* Before Reading DMA status to figure out number
+ * of bytes transferred by DMA channel:
+ * Change the client associated with the DMA channel
+ * to stop DMA engine from starting any more bursts for
+ * the given client and wait for in flight bursts to complete
+ */
+ tegra_dma_reset_client(tdc);
+
+ /* Wait for in flight data transfer to finish */
+ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
+
+ /* If TX/RX path is still active wait till it becomes
+ * inactive
+ */
+
+ if (readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset +
+ TEGRA_GPCDMA_CHAN_STATUS,
+ status,
+ !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
+ TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
+ 5,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT)) {
+ dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
+ tegra_dma_dump_chan_regs(tdc);
+ }
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tdc->isr_handler(tdc, true);
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ }
+
+ was_busy = tdc->busy;
+ tegra_dma_stop(tdc);
+
+ if (!list_empty(&tdc->pending_sg_req) && was_busy) {
+ sgreq = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sgreq), node);
+ sgreq->dma_desc->bytes_transferred +=
+ sgreq->req_len - (wcount * 4);
+ }
+
+skip_dma_stop:
+ tegra_dma_abort_all(tdc);
+ vchan_free_chan_resources(&tdc->vc);
+ if (tdc->is_pending) {
+ tdc->pending_dma_desc = tdc->dma_desc;
+ tdc->is_pending = false;
+ tdc->dma_desc = NULL;
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ struct tegra_dma_sg_req *sg_req;
+ unsigned int residual;
+ enum dma_status ret;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+
+ /*
+ * Incase if dma client terminate the request and triggers tx_status
+ * before the dma completion then free pending dma desc if exist
+ */
+ if (tdc->pending_dma_desc) {
+ dma_desc = tdc->pending_dma_desc;
+ tdc->pending_dma_desc = NULL;
+ if (dma_desc->vd.tx.cookie == cookie) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ kfree(dma_desc);
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+ }
+
+ /* Check in pending list */
+ list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
+ dma_desc = sg_req->dma_desc;
+ if (dma_desc->vd.tx.cookie == cookie) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+ }
+
+ dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+static inline int get_bus_width(struct tegra_dma_channel *tdc,
+ enum dma_slave_buswidth slave_bw)
+{
+ switch (slave_bw) {
+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ case DMA_SLAVE_BUSWIDTH_8_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_64;
+ default:
+ dev_warn(tdc2dev(tdc),
+ "slave bw is not supported, using 32bits\n");
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ }
+}
+
+static inline int get_burst_size(struct tegra_dma_channel *tdc,
+ u32 burst_size,
+ enum dma_slave_buswidth slave_bw,
+ int len)
+{
+ int burst_mmio_width;
+ int burst_byte;
+
+ /*
+ * burst_size from client is in terms of the bus_width.
+ * convert that into words.
+ */
+ burst_byte = burst_size * slave_bw;
+ burst_mmio_width = burst_byte / 4;
+
+ /* If burst size is 0 then calculate the burst size based on length */
+ if (!burst_mmio_width) {
+ if (len & 0xF)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ else if ((len >> 3) & 0x1)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ else if ((len >> 4) & 0x1)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ else if ((len >> 5) & 0x1)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ else
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ }
+ if (burst_mmio_width < 2)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ else if (burst_mmio_width < 4)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ else if (burst_mmio_width < 8)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ else if (burst_mmio_width < 16)
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ else
+ return TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+}
+
+static int get_transfer_param(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction,
+ unsigned long *apb_addr,
+ unsigned long *mmio_seq,
+ unsigned long *csr,
+ unsigned int *burst_size,
+ enum dma_slave_buswidth *slave_bw)
+{
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ *apb_addr = tdc->dma_sconfig.dst_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
+ *burst_size = tdc->dma_sconfig.dst_maxburst;
+ *slave_bw = tdc->dma_sconfig.dst_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
+ return 0;
+
+ case DMA_DEV_TO_MEM:
+ *apb_addr = tdc->dma_sconfig.src_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
+ *burst_size = tdc->dma_sconfig.src_maxburst;
+ *slave_bw = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
+ return 0;
+ case DMA_MEM_TO_MEM:
+ *burst_size = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ return 0;
+ default:
+ dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
+ return -EINVAL;
+ }
+ return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *tegra_dma_prep_dma_memset(
+ struct dma_chan *dc, dma_addr_t dest, int value, size_t len,
+ unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_sg_req *sg_req = NULL;
+ struct tegra_dma_desc *dma_desc;
+ struct list_head req_list;
+ unsigned long csr, mc_seq;
+
+ INIT_LIST_HEAD(&req_list);
+ /* Set dma mode to fixed pattern */
+ csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= (1 << TEGRA_GPCDMA_CSR_WEIGHT_SHIFT);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
+ TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
+
+ /* Set the address wrapping */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
+ TEGRA_GPCDMA_MCSEQ_WRAP0_SHIFT;
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
+ TEGRA_GPCDMA_MCSEQ_WRAP1_SHIFT;
+
+ /* Program outstanding MC requests */
+ mc_seq |= (1 << TEGRA_GPCDMA_MCSEQ_REQ_COUNT_SHIFT);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(struct tegra_dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
+ if (!sg_req) {
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ sg_req->ch_regs.src_ptr = 0;
+ sg_req->ch_regs.dst_ptr = dest;
+ sg_req->ch_regs.high_addr_ptr = ((dest >> 32) &
+ TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_MASK) <<
+ TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_SHIFT;
+ sg_req->ch_regs.fixed_pattern = value;
+ /* Word count reg takes value as (N +1) words */
+ sg_req->ch_regs.wcount = ((len - 4) >> 2);
+ sg_req->ch_regs.csr = csr;
+ sg_req->ch_regs.mmio_seq = 0;
+ sg_req->ch_regs.mc_seq = mc_seq;
+ sg_req->configured = false;
+ sg_req->last_sg = false;
+ sg_req->dma_desc = dma_desc;
+ sg_req->req_len = len;
+ sg_req->last_sg = true;
+
+ list_add_tail(&sg_req->node, &tdc->pending_sg_req);
+
+ if (!tdc->isr_handler)
+ tdc->isr_handler = handle_once_dma_done;
+
+ tdc->pending_dma_desc = NULL;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *tegra_dma_prep_dma_memcpy(
+ struct dma_chan *dc, dma_addr_t dest, dma_addr_t src, size_t len,
+ unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_sg_req *sg_req = NULL;
+ struct tegra_dma_desc *dma_desc;
+ struct list_head req_list;
+ unsigned long csr, mc_seq;
+
+ INIT_LIST_HEAD(&req_list);
+ /* Set dma mode to memory to memory transfer */
+ csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= (1 << TEGRA_GPCDMA_CSR_WEIGHT_SHIFT);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= ((TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
+ TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT) |
+ (TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
+ TEGRA_GPCDMA_MCSEQ_STREAM_ID1_SHIFT));
+
+ /* Set the address wrapping */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
+ TEGRA_GPCDMA_MCSEQ_WRAP0_SHIFT;
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
+ TEGRA_GPCDMA_MCSEQ_WRAP1_SHIFT;
+
+ /* Program outstanding MC requests */
+ mc_seq |= (1 << TEGRA_GPCDMA_MCSEQ_REQ_COUNT_SHIFT);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(struct tegra_dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (src & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
+ if (!sg_req) {
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ sg_req->ch_regs.src_ptr = src;
+ sg_req->ch_regs.dst_ptr = dest;
+ sg_req->ch_regs.high_addr_ptr = (src >> 32) &
+ TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_MASK;
+ sg_req->ch_regs.high_addr_ptr |= ((dest >> 32) &
+ TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_MASK) <<
+ TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_SHIFT;
+ /* Word count reg takes value as (N +1) words */
+ sg_req->ch_regs.wcount = ((len - 4) >> 2);
+ sg_req->ch_regs.csr = csr;
+ sg_req->ch_regs.mmio_seq = 0;
+ sg_req->ch_regs.mc_seq = mc_seq;
+ sg_req->configured = false;
+ sg_req->last_sg = false;
+ sg_req->dma_desc = dma_desc;
+ sg_req->req_len = len;
+ sg_req->last_sg = true;
+
+ list_add_tail(&sg_req->node, &tdc->pending_sg_req);
+
+ if (!tdc->isr_handler)
+ tdc->isr_handler = handle_once_dma_done;
+
+ tdc->pending_dma_desc = NULL;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
+ struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned long flags,
+ void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ struct tegra_dma_sg_req *sg_req = NULL;
+ enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_desc *dma_desc;
+ struct list_head req_list;
+ struct scatterlist *sg;
+ u32 burst_size;
+ unsigned int i;
+ int ret;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "dma channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
+ &burst_size, &slave_bw);
+ if (ret < 0)
+ return NULL;
+
+ INIT_LIST_HEAD(&req_list);
+
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Program the slave id in requestor select */
+ csr |= tdc->slave_id << TEGRA_GPCDMA_CSR_REQ_SEL_SHIFT;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Configure default priority weight for the channel*/
+ csr |= (1 << TEGRA_GPCDMA_CSR_WEIGHT_SHIFT);
+
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
+ TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
+
+ /* Set the address wrapping on both MC and MMIO side */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
+ TEGRA_GPCDMA_MCSEQ_WRAP0_SHIFT;
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
+ TEGRA_GPCDMA_MCSEQ_WRAP1_SHIFT;
+ mmio_seq |= (1 << TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD_SHIFT);
+
+ /* Program 2 MC outstanding requests by default. */
+ mc_seq |= (1 << TEGRA_GPCDMA_MCSEQ_REQ_COUNT_SHIFT);
+
+ /* Setting MC burst size depending on MMIO burst size */
+ if (burst_size == 64)
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+ else
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
+
+ dma_desc = kzalloc(sizeof(struct tegra_dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len;
+ dma_addr_t mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
+ if (!sg_req) {
+ kfree(dma_desc);
+ goto sg_alloc_error;
+ }
+
+ mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
+ dma_desc->bytes_requested += len;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ sg_req->ch_regs.src_ptr = mem;
+ sg_req->ch_regs.dst_ptr = apb_ptr;
+ sg_req->ch_regs.high_addr_ptr = (mem >> 32) &
+ TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_MASK;
+ } else if (direction == DMA_DEV_TO_MEM) {
+ sg_req->ch_regs.src_ptr = apb_ptr;
+ sg_req->ch_regs.dst_ptr = mem;
+ sg_req->ch_regs.high_addr_ptr = ((mem >> 32) &
+ TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_MASK) <<
+ TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_SHIFT;
+ }
+
+ /*
+ * Word count register takes input in words. Writing a value
+ * of N into word count register means a req of (N+1) words.
+ */
+ sg_req->ch_regs.wcount = ((len - 4) >> 2);
+ sg_req->ch_regs.csr = csr;
+ sg_req->ch_regs.mmio_seq = mmio_seq;
+ sg_req->ch_regs.mc_seq = mc_seq;
+ sg_req->configured = false;
+ sg_req->last_sg = false;
+ sg_req->dma_desc = dma_desc;
+ sg_req->req_len = len;
+ list_add_tail(&sg_req->node, &tdc->pending_sg_req);
+ }
+ sg_req->last_sg = true;
+
+ /*
+ * Make sure that mode should not be conflicting with currently
+ * configured mode.
+ */
+ if (!tdc->isr_handler)
+ tdc->isr_handler = handle_once_dma_done;
+
+ tdc->pending_dma_desc = NULL;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+
+sg_alloc_error:
+ while (!list_empty(&tdc->pending_sg_req)) {
+ sg_req = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sg_req), node);
+ list_del(&sg_req->node);
+ kfree(sg_req);
+ }
+ return NULL;
+}
+
+static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ dma_cookie_init(&tdc->vc.chan);
+ tdc->config_init = false;
+ return 0;
+}
+
+static void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct list_head sg_req_list;
+ unsigned long flags;
+
+ INIT_LIST_HEAD(&sg_req_list);
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ if (tdc->busy)
+ tegra_dma_terminate_all(dc);
+
+ tasklet_kill(&tdc->vc.task);
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ tdc->pending_dma_desc = NULL;
+ list_splice_init(&tdc->pending_sg_req, &sg_req_list);
+ tdc->config_init = false;
+ tdc->isr_handler = NULL;
+ tdc->slave_id = -1;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct tegra_dma_channel *tdc;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ tdc = to_tegra_dma_chan(chan);
+ tdc->slave_id = dma_spec->args[0];
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = false,
+};
+
+static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+};
+
+static const struct of_device_id tegra_dma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra186-gpcdma",
+ .data = &tegra186_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra194-gpcdma",
+ .data = &tegra194_dma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+
+static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
+ int chan, int stream_id)
+{
+ unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
+ TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
+ TEGRA_GPCDMA_MCSEQ_STREAM_ID1_SHIFT);
+
+ reg_val |= (stream_id << TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
+ reg_val |= (stream_id << TEGRA_GPCDMA_MCSEQ_STREAM_ID1_SHIFT);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ return 0;
+}
+
+static int tegra_dma_probe(struct platform_device *pdev)
+{
+ const struct tegra_dma_chip_data *cdata = NULL;
+ struct tegra_dma_chip_data *chip_data = NULL;
+ unsigned int nr_chans, stream_id;
+ unsigned int start_chan_idx = 0;
+ struct tegra_dma *tdma;
+ struct resource *res;
+ unsigned int i;
+ int ret;
+
+ if (pdev->dev.of_node) {
+ const struct of_device_id *match;
+
+ match = of_match_device(of_match_ptr(tegra_dma_of_match),
+ &pdev->dev);
+ if (!match) {
+ dev_err(&pdev->dev, "Error: No device match found\n");
+ return -ENODEV;
+ }
+ cdata = match->data;
+
+ ret = of_property_read_u32(pdev->dev.of_node, "dma-channels",
+ &nr_chans);
+ if (!ret) {
+ /* Allocate chip data and update number of channels */
+ chip_data =
+ devm_kzalloc(&pdev->dev,
+ sizeof(struct tegra_dma_chip_data),
+ GFP_KERNEL);
+ if (!chip_data) {
+ dev_err(&pdev->dev, "Error: memory allocation failed\n");
+ return -ENOMEM;
+ }
+ memcpy(chip_data, cdata,
+ sizeof(struct tegra_dma_chip_data));
+ chip_data->nr_channels = nr_chans;
+ cdata = chip_data;
+ }
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "nvidia,start-dma-channel-index",
+ &start_chan_idx);
+ if (ret)
+ start_chan_idx = 0;
+
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "nvidia,stream-id", &stream_id);
+ if (ret)
+ stream_id = TEGRA186_SID_GPCDMA_0;
+
+ } else {
+ /* If no device tree then fallback to chip data */
+ cdata =
+ (struct tegra_dma_chip_data *)pdev->id_entry->driver_data;
+ stream_id = TEGRA186_SID_GPCDMA_0;
+ }
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ if (IS_ERR(tdma->rst)) {
+ if (!(PTR_ERR(tdma->rst) == -EPROBE_DEFER))
+ dev_err(&pdev->dev, "Missing controller reset\n");
+ return PTR_ERR(tdma->rst);
+ }
+ reset_control_reset(tdma->rst);
+
+ tdma->dma_dev.dev = &pdev->dev;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
+ start_chan_idx * cdata->channel_reg_size +
+ i * cdata->channel_reg_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ,
+ start_chan_idx + i);
+ if (!res) {
+ ret = -EINVAL;
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ goto err_irq;
+ }
+ tdc->irq = res->start;
+ snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+
+ tdc->tdma = tdma;
+ tdc->id = i;
+ tdc->slave_id = -1;
+
+ vchan_init(&tdc->vc, &tdma->dma_dev);
+ tdc->vc.desc_free = tegra_dma_desc_free;
+ raw_spin_lock_init(&tdc->lock);
+
+ INIT_LIST_HEAD(&tdc->pending_sg_req);
+ tdc->pending_dma_desc = NULL;
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, i, stream_id);
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
+
+ /*
+ * Only word aligned transfers are supported. Set the copy
+ * alignment shift.
+ */
+ tdma->dma_dev.copy_align = 2;
+ tdma->dma_dev.fill_align = 2;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
+ tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
+ tdma->dma_dev.device_config = tegra_dma_slave_config;
+ tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ /* Register DMA channel interrupt handlers after everything is setup */
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "request_irq failed with err %d channel %d\n",
+ i, ret);
+ goto err_irq;
+ }
+ }
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "GPC DMA driver registration failed %d\n", ret);
+ goto err_irq;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "GPC DMA OF registration failed %d\n", ret);
+ goto err_unregister_dma_dev;
+ }
+
+ dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
+ cdata->nr_channels);
+ return 0;
+
+err_unregister_dma_dev:
+ dma_async_device_unregister(&tdma->dma_dev);
+err_irq:
+ return ret;
+}
+
+static int tegra_dma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ return 0;
+}
+
+/*
+ * Save and restore csr and channel register on pm_suspend
+ * and pm_resume respectively
+ */
+static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+ struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
+
+ ch_reg->csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+ ch_reg->src_ptr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR);
+ ch_reg->dst_ptr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR);
+ ch_reg->high_addr_ptr = tdc_read(tdc,
+ TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR);
+ ch_reg->mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ ch_reg->mmio_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ);
+ ch_reg->wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT);
+ }
+ return 0;
+}
+
+static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+ struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_reg->wcount);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_reg->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_reg->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR,
+ ch_reg->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_reg->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_reg->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ (ch_reg->csr & ~TEGRA_GPCDMA_CSR_ENB));
+ }
+ return 0;
+}
+
+static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
+};
+
+static struct platform_driver tegra_dmac_driver = {
+ .driver = {
+ .name = "tegra-gpcdma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_dma_dev_pm_ops,
+ .of_match_table = tegra_dma_of_match,
+ },
+ .probe = tegra_dma_probe,
+ .remove = tegra_dma_remove,
+};
+
+module_platform_driver(tegra_dmac_driver);
+
+MODULE_ALIAS("platform:tegra-gpc-dma");
+MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
+MODULE_AUTHOR("Pavan Kunapuli <[email protected]>");
+MODULE_AUTHOR("Rajesh Gumasta <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++
3 files changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 2fcaa2e..56ed8d8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -54,6 +54,10 @@
};
};
+ dma@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 58100fb..91bb17e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -70,6 +70,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x2600000 0x0 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ nvidia,start-dma-channel-index = <1>;
+ dma-channels = <31>;
+ status = "disabled";
+ };
+
aconnect {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 4bc187a..0bd67bd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -68,6 +68,50 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x0 0x2600000 0x0 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ nvidia,start-dma-channel-index = <1>;
+ dma-channels = <31>;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
--
2.7.4
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
dma controller driver
Signed-off-by: Rajesh Gumasta <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 883e8ba..600f568 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -775,6 +775,7 @@ CONFIG_MV_XOR_V2=y
CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
CONFIG_TEGRA20_APB_DMA=y
+CONFIG_TEGRA_GPC_DMA=m
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
--
2.7.4
06.08.2020 10:30, Rajesh Gumasta пишет:
> +static struct dma_async_tx_descriptor *tegra_dma_prep_dma_memset(
> + struct dma_chan *dc, dma_addr_t dest, int value, size_t len,
> + unsigned long flags)
> +{
This looks and reads okay, although the following style of code's
formatting is a bit more common for the kernel:
static struct dma_async_tx_descriptor *
tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest,
int value, size_t len, unsigned long flags)
You could make this small improvement in a v3. Same for all similar
cases in the code.
06.08.2020 10:30, Rajesh Gumasta пишет:
> +static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
> + int chan, int stream_id)
> +{
> + unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
> +
> + reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
> + TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
> + reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
> + TEGRA_GPCDMA_MCSEQ_STREAM_ID1_SHIFT);
> +
> + reg_val |= (stream_id << TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
> + reg_val |= (stream_id << TEGRA_GPCDMA_MCSEQ_STREAM_ID1_SHIFT);
Have you seen my comment to v1 about FIELD_GET/FIELD_PREP?
If you disagree with something, then you should answer with a rationale
and not silently ignore review comments.
06.08.2020 10:30, Rajesh Gumasta пишет:
...
> +/*
> + * Save and restore csr and channel register on pm_suspend
> + * and pm_resume respectively
> + */
> +static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
> +{
> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> + int i;
> +
> + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> + struct tegra_dma_channel *tdc = &tdma->channels[i];
> + struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
> +
> + ch_reg->csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
> + ch_reg->src_ptr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR);
> + ch_reg->dst_ptr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR);
> + ch_reg->high_addr_ptr = tdc_read(tdc,
> + TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR);
> + ch_reg->mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
> + ch_reg->mmio_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ);
> + ch_reg->wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT);
> + }
> + return 0;
> +}
> +
> +static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
> +{
> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> + int i;
> +
> + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> + struct tegra_dma_channel *tdc = &tdma->channels[i];
> + struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_reg->wcount);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_reg->dst_ptr);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_reg->src_ptr);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR,
> + ch_reg->high_addr_ptr);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_reg->mmio_seq);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_reg->mc_seq);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
> + (ch_reg->csr & ~TEGRA_GPCDMA_CSR_ENB));
> + }
> + return 0;
> +}
> +
> +static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
> +};
Please explain why this is needed. All DMA should be stopped (not
paused) on system's suspend, shouldn't it?
06.08.2020 16:56, Rajesh Gumasta пишет:
...
>>> +static const struct __maybe_unused dev_pm_ops
>> tegra_dma_dev_pm_ops = {
>>> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend,
>>> +tegra_dma_pm_resume) };
>>
>> Please explain why this is needed. All DMA should be stopped (not
>> paused) on system's suspend, shouldn't it?
> I have rechecked with HW verification team and they confirmed that after suspend, csr and channel registers will get reset hence on resume we need to restore back.
> Also GPCDMA does not support power gate as a unit.
But all registers are re-programmed on starting a DMA transfer, hence
why do you need to save-restore them on suspend-resume?
> -----Original Message-----
> From: Dmitry Osipenko <[email protected]>
> Sent: Thursday, August 6, 2020 7:16 PM
> To: Rajesh Gumasta <[email protected]>; Laxman Dewangan
> <[email protected]>; Jonathan Hunter <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: Krishna Yarlagadda <[email protected]>; Pavan Kunapuli
> <[email protected]>
> Subject: Re: [Patch v2 2/4] dmaengine: tegra: Add Tegra GPC DMA driver
>
> External email: Use caution opening links or attachments
>
>
> 06.08.2020 10:30, Rajesh Gumasta пишет:
> ...
> > +/*
> > + * Save and restore csr and channel register on pm_suspend
> > + * and pm_resume respectively
> > + */
> > +static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
> {
> > + struct tegra_dma *tdma = dev_get_drvdata(dev);
> > + int i;
> > +
> > + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> > + struct tegra_dma_channel *tdc = &tdma->channels[i];
> > + struct tegra_dma_channel_regs *ch_reg =
> > + &tdc->channel_reg;
> > +
> > + ch_reg->csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
> > + ch_reg->src_ptr = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_SRC_PTR);
> > + ch_reg->dst_ptr = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_DST_PTR);
> > + ch_reg->high_addr_ptr = tdc_read(tdc,
> > + TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR);
> > + ch_reg->mc_seq = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_MCSEQ);
> > + ch_reg->mmio_seq = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_MMIOSEQ);
> > + ch_reg->wcount = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_WCOUNT);
> > + }
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused tegra_dma_pm_resume(struct device *dev) {
> > + struct tegra_dma *tdma = dev_get_drvdata(dev);
> > + int i;
> > +
> > + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> > + struct tegra_dma_channel *tdc = &tdma->channels[i];
> > + struct tegra_dma_channel_regs *ch_reg =
> > + &tdc->channel_reg;
> > +
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_reg-
> >wcount);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_reg-
> >dst_ptr);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_reg-
> >src_ptr);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR,
> > + ch_reg->high_addr_ptr);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_reg-
> >mmio_seq);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_reg->mc_seq);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
> > + (ch_reg->csr & ~TEGRA_GPCDMA_CSR_ENB));
> > + }
> > + return 0;
> > +}
> > +
> > +static const struct __maybe_unused dev_pm_ops
> tegra_dma_dev_pm_ops = {
> > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend,
> > +tegra_dma_pm_resume) };
>
> Please explain why this is needed. All DMA should be stopped (not
> paused) on system's suspend, shouldn't it?
I have rechecked with HW verification team and they confirmed that after suspend, csr and channel registers will get reset hence on resume we need to restore back.
Also GPCDMA does not support power gate as a unit.
Thanks
Rajesh
On 06/08/2020 08:30, Rajesh Gumasta wrote:
> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
> supports dma transfers between memory to memory, IO peripheral to memory
> and memory to IO peripheral.
>
> Signed-off-by: Pavan Kunapuli <[email protected]>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/tegra-gpc-dma.c | 1472 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1485 insertions(+)
> create mode 100644 drivers/dma/tegra-gpc-dma.c
...
> +static void tdc_start_head_req(struct tegra_dma_channel *tdc)
> +{
> + struct tegra_dma_sg_req *sg_req;
> + struct virt_dma_desc *vdesc;
> +
> + if (list_empty(&tdc->pending_sg_req))
> + return;
> +
> + if (tdc->is_pending)
> + return;
> +
> + vdesc = vchan_next_desc(&tdc->vc);
> + if (!vdesc)
> + return;
> + list_del(&vdesc->node);
> + tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
> + tdc->is_pending = true;
> + tdc->dma_desc->tdc = tdc;
> + sg_req = list_first_entry(&tdc->pending_sg_req,
> + typeof(*sg_req), node);
> + tegra_dma_start(tdc, sg_req);
> + sg_req->configured = true;
> + tdc->busy = true;
> +}
I really don't understand this. First we get a descriptor for the
vchan_next_desc and then we get a sg_req from another list. I really
don't see why we need to have two lists here. Seems overly complicated.
Jon
--
nvpublic
On 06/08/2020 08:30, Rajesh Gumasta wrote:
> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
> supports dma transfers between memory to memory, IO peripheral to memory
> and memory to IO peripheral.
>
> Signed-off-by: Pavan Kunapuli <[email protected]>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/tegra-gpc-dma.c | 1472 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1485 insertions(+)
> create mode 100644 drivers/dma/tegra-gpc-dma.c
> +static void tegra_dma_desc_free(struct virt_dma_desc *vd)
> +{
> + struct tegra_dma_desc *dma_desc = vd_to_tegra_dma_desc(vd);
> + struct tegra_dma_channel *tdc = dma_desc->tdc;
> + unsigned long flags;
> +
> + if (!dma_desc)
> + return;
Personally, I would do this the other way around. If dma_desc is valid
then do the below.
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> + kfree(dma_desc);
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> +}
> +
> +static int tegra_dma_slave_config(struct dma_chan *dc,
> + struct dma_slave_config *sconfig)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> +
> + if (!list_empty(&tdc->pending_sg_req)) {
> + dev_err(tdc2dev(tdc), "Configuration not allowed\n");
> + return -EBUSY;
> + }
> +
> + memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
> + if (tdc->slave_id == -1)
> + tdc->slave_id = sconfig->slave_id;
> + tdc->config_init = true;
> + return 0;
> +}
> +
> +static int tegra_dma_pause(struct tegra_dma_channel *tdc)
> +{
> + u32 val;
> + int ret;
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
> +
> + /* Wait until busy bit is de-asserted */
> + ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
> + tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
> + val,
> + !(val & TEGRA_GPCDMA_STATUS_BUSY),
> + TEGRA_GPCDMA_BURST_COMPLETE_TIME,
> + TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
> +
> + if (ret) {
> + dev_err(tdc2dev(tdc), "DMA pause timed out\n");
> + return ret;
No need to return here.
> + }
> +
> + return ret;
> +}
...
> +static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
> +{
> + struct tegra_dma_channel *tdc = dev_id;
> + unsigned int err_status;
> + unsigned long status;
> +
> + raw_spin_lock(&tdc->lock);
> +
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + err_status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
> +
> + if (err_status) {
> + tegra_dma_chan_decode_error(tdc, err_status);
> + tegra_dma_dump_chan_regs(tdc);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
> + }
> +
> + if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
> + TEGRA_GPCDMA_STATUS_ISE_EOC);
> + if (tdc->isr_handler) {
> + tdc->isr_handler(tdc, false);
> + } else {
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d: status %lx ISR handler absent!\n",
> + tdc->id, status);
> + tegra_dma_dump_chan_regs(tdc);
> + }
> + raw_spin_unlock(&tdc->lock);
> + return IRQ_HANDLED;
It is usually better to init a return value to IRQ_NONE at the beginning
and then update the variable here and just have one return point.
> + }
> +
> + raw_spin_unlock(&tdc->lock);
> + return IRQ_NONE;
> +}
...
> +static inline int get_bus_width(struct tegra_dma_channel *tdc,
> + enum dma_slave_buswidth slave_bw)
> +{
> + switch (slave_bw) {
> + case DMA_SLAVE_BUSWIDTH_1_BYTE:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
> + case DMA_SLAVE_BUSWIDTH_2_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
> + case DMA_SLAVE_BUSWIDTH_8_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_64;
> + default:
> + dev_warn(tdc2dev(tdc),
> + "slave bw is not supported, using 32bits\n");
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
This is an error and so please return an error. I doubtful that there is
any point in trying to continue.
> + }
> +}
> +
> +static inline int get_burst_size(struct tegra_dma_channel *tdc,
> + u32 burst_size,
> + enum dma_slave_buswidth slave_bw,
> + int len)
> +{
> + int burst_mmio_width;
> + int burst_byte;
> +
> + /*
> + * burst_size from client is in terms of the bus_width.
> + * convert that into words.
> + */
> + burst_byte = burst_size * slave_bw;
> + burst_mmio_width = burst_byte / 4;
> +
> + /* If burst size is 0 then calculate the burst size based on length */
> + if (!burst_mmio_width) {
> + if (len & 0xF)
case statement?
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_1;
> + else if ((len >> 3) & 0x1)
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_2;
> + else if ((len >> 4) & 0x1)
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_4;
> + else if ((len >> 5) & 0x1)
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_8;
> + else
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_16;
> + }
> + if (burst_mmio_width < 2)
case statement?
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_1;
> + else if (burst_mmio_width < 4)
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_2;
> + else if (burst_mmio_width < 8)
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_4;
> + else if (burst_mmio_width < 16)
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_8;
> + else
> + return TEGRA_GPCDMA_MMIOSEQ_BURST_16;
> +}
...
> +static int tegra_dma_probe(struct platform_device *pdev)
> +{
> + const struct tegra_dma_chip_data *cdata = NULL;
> + struct tegra_dma_chip_data *chip_data = NULL;
> + unsigned int nr_chans, stream_id;
> + unsigned int start_chan_idx = 0;
> + struct tegra_dma *tdma;
> + struct resource *res;
> + unsigned int i;
> + int ret;
> +
> + if (pdev->dev.of_node) {
This is always true
> + const struct of_device_id *match;
> +
> + match = of_match_device(of_match_ptr(tegra_dma_of_match),
> + &pdev->dev);
> + if (!match) {
No need to test this.
> + dev_err(&pdev->dev, "Error: No device match found\n");
> + return -ENODEV;
> + }
> + cdata = match->data;
> +
> + ret = of_property_read_u32(pdev->dev.of_node, "dma-channels",
> + &nr_chans);
You appear to have this in two places; one in DT and one in the chip
data. We can use the chip data and so we don't need this.
> + if (!ret) {
> + /* Allocate chip data and update number of channels */
> + chip_data =
> + devm_kzalloc(&pdev->dev,
> + sizeof(struct tegra_dma_chip_data),
> + GFP_KERNEL);
> + if (!chip_data) {
> + dev_err(&pdev->dev, "Error: memory allocation failed\n");
> + return -ENOMEM;
> + }
> + memcpy(chip_data, cdata,
> + sizeof(struct tegra_dma_chip_data));
> + chip_data->nr_channels = nr_chans;
> + cdata = chip_data;
> + }
> + ret = of_property_read_u32(pdev->dev.of_node,
> + "nvidia,start-dma-channel-index",
> + &start_chan_idx);
This is not a valid property for DT. Please remove.
Cheers
Jon
--
nvpublic
On 06/08/2020 08:30, Rajesh Gumasta wrote:
> Add device tree node for GPCDMA controller on Tegra186 target
> and Tegra194 target.
>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++
> 3 files changed, 94 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 2fcaa2e..56ed8d8 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -54,6 +54,10 @@
> };
> };
>
> + dma@2600000 {
> + status = "okay";
> + };
> +
> memory-controller@2c00000 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 58100fb..91bb17e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -70,6 +70,52 @@
> snps,rxpbl = <8>;
> };
>
> + gpcdma: dma@2600000 {
> + compatible = "nvidia,tegra186-gpcdma";
> + reg = <0x0 0x2600000 0x0 0x210000>;
> + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> + dma-coherent;
> + nvidia,start-dma-channel-index = <1>;
> + dma-channels = <31>;
The above two properties are not mentioned in the dt-binding doc. I
really don't think we want these, especially the first as this is not
describing the h/w.
Jon
--
nvpublic
On 06/08/2020 08:30, Rajesh Gumasta wrote:
> Changes in patch v2:
> Addressed review comments in patch v1
Is there any update on this series? Would be good to get this upstream.
Jon
--
nvpublic
On 14-01-21, 10:11, Jon Hunter wrote:
>
> On 06/08/2020 08:30, Rajesh Gumasta wrote:
> > Changes in patch v2:
> > Addressed review comments in patch v1
>
>
> Is there any update on this series? Would be good to get this upstream.
Not sure why, this is is not in my queue, can someone please resend this
to me
Thanks
--
~Vinod
On 15/01/2021 05:56, Vinod Koul wrote:
> On 14-01-21, 10:11, Jon Hunter wrote:
>>
>> On 06/08/2020 08:30, Rajesh Gumasta wrote:
>>> Changes in patch v2:
>>> Addressed review comments in patch v1
>>
>>
>> Is there any update on this series? Would be good to get this upstream.
>
> Not sure why, this is is not in my queue, can someone please resend this
> to me
Sorry, this question was meant for Rajesh. This series is not ready yet.
There are still some items that need to be addressed.
Thanks
Jon
--
nvpublic
> -----Original Message-----
> From: Jonathan Hunter <[email protected]>
> Sent: Friday, January 15, 2021 6:51 PM
> To: Vinod Koul <[email protected]>
> Cc: Rajesh Gumasta <[email protected]>; Laxman Dewangan
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Krishna Yarlagadda <[email protected]>
> Subject: Re: [Patch v2 0/4] Add Nvidia Tegra GPC-DMA driver
>
>
> On 15/01/2021 05:56, Vinod Koul wrote:
> > On 14-01-21, 10:11, Jon Hunter wrote:
> >>
> >> On 06/08/2020 08:30, Rajesh Gumasta wrote:
> >>> Changes in patch v2:
> >>> Addressed review comments in patch v1
> >>
> >>
> >> Is there any update on this series? Would be good to get this upstream.
> >
> > Not sure why, this is is not in my queue, can someone please resend
> > this to me
>
> Sorry, this question was meant for Rajesh. This series is not ready yet.
> There are still some items that need to be addressed.
>
> Thanks
> Jon
>
Yes, some pending review comments on v2 patch needs to addressed.
Currently this is put on hold due to other priority things.
I will update this thread once I resume working addressing the comments.
Thanks
Rajesh
Add support for Nvida Tegra general purpose DMA driver for
Tegra186 and Tegra194 platform.
Changes in patch v3:
Addressed review comments in patch v2
v2 - https://lkml.org/lkml/2020/8/6/90
v1 - https://lkml.org/lkml/2020/7/20/96
Akhil R (4):
dt-bindings: dmaengine: Add doc for tegra gpcdma
dmaengine: tegra: Add tegra gpcdma driver
arm64: defconfig: tegra: Enable GPCDMA
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
.../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 +
arch/arm64/configs/defconfig | 1 +
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-gpc-dma.c | 1343 ++++++++++++++++++++
8 files changed, 1552 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
create mode 100644 drivers/dma/tegra-gpc-dma.c
--
2.7.4
Add DT binding document for Nvidia Tegra GPCDMA controller.
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
.../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++++++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
new file mode 100644
index 0000000..39827ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra-gpc-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nvidia Tegra GPC DMA Controller Device Tree Bindings
+
+description: |
+ Tegra GPC DMA controller is a general purpose dma used for faster data
+ transfers between memory to memory, memory to device and device to memory.
+ Terms 'dma' and 'gpcdma' can be used interchangeably.
+
+maintainers:
+ - Jon Hunter <[email protected]>
+ - Rajesh Gumasta <[email protected]>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 1
+
+ compatible:
+ - enum:
+ - nvidia,tegra186-gpcdma
+ - nvidia,tegra194-gpcdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: gpcdma
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+ - "#dma-cells"
+ - iommus
+
+examples:
+ - |
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x2600000 0x0 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA_SID_GPCDMA_0>;
+ dma-coherent;
+ };
+
+...
--
2.7.4
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
dma controller driver
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f423d08..d247a7e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -930,6 +930,7 @@ CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
+CONFIG_TEGRA_GPC_DMA=m
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
--
2.7.4
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
supports dma transfers between memory to memory, IO peripheral to memory
and memory to IO peripheral.
Signed-off-by: Pavan Kunapuli <[email protected]>
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-gpc-dma.c | 1343 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1356 insertions(+)
create mode 100644 drivers/dma/tegra-gpc-dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 39b5b46..9d1d93d 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -632,6 +632,18 @@ config TEGRA210_ADMA
peripheral and vice versa. It does not support memory to
memory data transfer.
+config TEGRA_GPC_DMA
+ tristate "NVIDIA Tegra GPC DMA support"
+ depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
+ driver. The DMA controller has multiple DMA channels which can
+ be configured for different peripherals like UART, SPI, etc
+ which are on APB bus.
+ This DMA controller transfers data from memory to peripheral FIFO
+ or vice versa. It also supports memory to memory data transfer.
+
config TIMB_DMA
tristate "Timberdale FPGA DMA support"
depends on MFD_TIMBERDALE || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index aa69094..943e8d7 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
+obj-$(CONFIG_TEGRA_GPC_DMA) += tegra-gpc-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o
diff --git a/drivers/dma/tegra-gpc-dma.c b/drivers/dma/tegra-gpc-dma.c
new file mode 100644
index 0000000..d990121
--- /dev/null
+++ b/drivers/dma/tegra-gpc-dma.c
@@ -0,0 +1,1343 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller.
+ *
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <dt-bindings/memory/tegra186-mc.h>
+#include "virt-dma.h"
+
+/* CSR register */
+#define TEGRA_GPCDMA_CHAN_CSR 0x00
+#define TEGRA_GPCDMA_CSR_ENB BIT(31)
+#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
+#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
+
+#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
+#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
+#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
+#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
+
+#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
+#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
+
+#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
+#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
+#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
+
+/* STATUS register */
+#define TEGRA_GPCDMA_CHAN_STATUS 0x004
+#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
+#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
+#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
+#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
+#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
+#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
+#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
+
+#define TEGRA_GPCDMA_CHAN_CSRE 0x008
+#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
+
+/* Source address */
+#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
+
+/* Destination address */
+#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
+
+/* High address pointer */
+#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
+#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
+
+/* MC sequence register */
+#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
+#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
+#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
+#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
+#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
+#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
+#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
+
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
+
+/* MMIO sequence register */
+#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
+#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
+#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST GENMASK(26, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_1 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_4 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 7)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 15)
+#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
+#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
+#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
+
+/* Channel WCOUNT */
+#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
+
+/* Transfer count */
+#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
+
+/* DMA byte count status */
+#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
+
+/* Error Status Register */
+#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT (8)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK (0xF)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
+ ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
+ TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
+#define TEGRA_DMA_BM_FIFO_FULL_ERR (0xF)
+#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR (0xE)
+#define TEGRA_DMA_PERIPH_ID_ERR (0xD)
+#define TEGRA_DMA_STREAM_ID_ERR (0xC)
+#define TEGRA_DMA_MC_SLAVE_ERR (0xB)
+#define TEGRA_DMA_MMIO_SLAVE_ERR (0xA)
+
+/* Fixed Pattern */
+#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
+
+#define TEGRA_GPCDMA_CHAN_TZ 0x38
+#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
+#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
+
+#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
+#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
+
+/*
+ * If any burst is in flight and DMA paused then this is the time to complete
+ * on-flight burst and update DMA status register.
+ */
+#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
+#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
+
+/* Channel base address offset from GPCDMA base address */
+#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
+
+struct tegra_dma;
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @hw_support_pause: DMA HW engine support pause of the channel.
+ */
+struct tegra_dma_chip_data {
+ int nr_channels;
+ int channel_reg_size;
+ int max_dma_count;
+ bool hw_support_pause;
+};
+
+/* DMA channel registers */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long src_ptr;
+ unsigned long dst_ptr;
+ unsigned long high_addr_ptr;
+ unsigned long mc_seq;
+ unsigned long mmio_seq;
+ unsigned long wcount;
+ unsigned long fixed_pattern;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
+ * manage client request and keep track of transfer status, callbacks
+ * and request counts etc.
+ */
+struct tegra_dma_desc {
+ struct virt_dma_desc vd;
+ int bytes_requested;
+ int bytes_transferred;
+ struct tegra_dma_channel *tdc;
+ struct tegra_dma_channel_regs ch_regs;
+};
+
+struct tegra_dma_channel;
+
+typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
+ bool to_terminate);
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct virt_dma_chan vc;
+ struct tegra_dma_desc *dma_desc;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ unsigned int stream_id;
+ unsigned long chan_base_offset;
+ raw_spinlock_t lock;
+ bool busy;
+ bool is_pending;
+ struct tegra_dma *tdma;
+ dma_isr_handler isr_handler;
+ int slave_id;
+ struct dma_slave_config dma_sconfig;
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ struct reset_control *rst;
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, vc.chan);
+}
+
+static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct tegra_dma_desc, vd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return tdc->vc.chan.device->dev;
+}
+
+static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
+{
+ dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
+ tdc->id, tdc->name);
+ dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
+ );
+ dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
+ );
+ dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+}
+
+static void tegra_dma_desc_free(struct virt_dma_desc *vd)
+{
+ struct tegra_dma_desc *dma_desc = vd_to_tegra_dma_desc(vd);
+ struct tegra_dma_channel *tdc = dma_desc->tdc;
+ unsigned long flags;
+
+ if (dma_desc) {
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ kfree(dma_desc);
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ }
+}
+
+static int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ if (tdc->dma_desc) {
+ dev_err(tdc2dev(tdc), "Configuration not allowed\n");
+ return -EBUSY;
+ }
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ if (tdc->slave_id == -1)
+ tdc->slave_id = sconfig->slave_id;
+ tdc->config_init = true;
+ return 0;
+}
+
+static int tegra_dma_pause(struct tegra_dma_channel *tdc)
+{
+ u32 val;
+ int ret;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
+
+ /* Wait until busy bit is de-asserted */
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ val,
+ !(val & TEGRA_GPCDMA_STATUS_BUSY),
+ TEGRA_GPCDMA_BURST_COMPLETE_TIME,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+
+ if (ret)
+ dev_err(tdc2dev(tdc), "DMA pause timed out\n");
+
+ return ret;
+}
+
+static void tegra_dma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 csr, status;
+
+ csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ /* Disable interrupts */
+ csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
+
+ /* Disable DMA */
+ csr &= ~TEGRA_GPCDMA_CSR_ENB;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+
+ /* Clear interrupt status if it is there */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ }
+ tdc->busy = false;
+}
+
+static void tegra_dma_start(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_channel_regs *ch_regs = &tdc->dma_desc->ch_regs;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+
+ /* Start DMA */
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+}
+
+static void tdc_start_head_req(struct tegra_dma_channel *tdc)
+{
+ struct virt_dma_desc *vdesc;
+
+ if (tdc->is_pending)
+ return;
+
+ vdesc = vchan_next_desc(&tdc->vc);
+ if (!vdesc)
+ return;
+
+ tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
+ if (!tdc->dma_desc)
+ return;
+
+ list_del(&vdesc->node);
+
+ tdc->is_pending = true;
+ tdc->dma_desc->tdc = tdc;
+ tegra_dma_start(tdc);
+ tdc->busy = true;
+}
+
+static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
+{
+ kfree(tdc->dma_desc);
+ tdc->isr_handler = NULL;
+}
+
+static void handle_once_dma_done(struct tegra_dma_channel *tdc,
+ bool to_terminate)
+{
+ struct tegra_dma_desc *dma_desc;
+
+ tdc->busy = false;
+ dma_desc = tdc->dma_desc;
+ dma_desc->bytes_transferred += dma_desc->bytes_requested;
+
+ vchan_cookie_complete(&tdc->dma_desc->vd);
+ tdc->is_pending = false;
+ kfree(tdc->dma_desc);
+
+ if (to_terminate)
+ return;
+
+ tdc_start_head_req(tdc);
+}
+
+static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
+ unsigned int err_status)
+{
+ switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
+ case TEGRA_DMA_BM_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d bm fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d peripheral fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal peripheral id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_STREAM_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal stream id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MC_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mc slave error\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MMIO_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mmio slave error\n", tdc->id);
+ break;
+
+ default:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d security violation %x\n", tdc->id,
+ err_status);
+ }
+}
+
+static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ unsigned int err_status;
+ unsigned long status;
+
+ raw_spin_lock(&tdc->lock);
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ err_status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+
+ if (err_status) {
+ tegra_dma_chan_decode_error(tdc, err_status);
+ tegra_dma_dump_chan_regs(tdc);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ }
+
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ TEGRA_GPCDMA_STATUS_ISE_EOC);
+ if (tdc->isr_handler) {
+ tdc->isr_handler(tdc, false);
+ } else {
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d: status %lx ISR handler absent!\n",
+ tdc->id, status);
+ tegra_dma_dump_chan_regs(tdc);
+ }
+ ret = IRQ_HANDLED;
+ }
+
+ raw_spin_unlock(&tdc->lock);
+ return ret;
+}
+
+static void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->busy)
+ if (vchan_issue_pending(&tdc->vc))
+ tdc_start_head_req(tdc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
+{
+ u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
+ csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+}
+
+static int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long wcount = 0;
+ unsigned long status;
+ unsigned long flags;
+ bool was_busy;
+ int err;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->dma_desc) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ if (tdc->tdma->chip_data->hw_support_pause) {
+ err = tegra_dma_pause(tdc);
+ if (err) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return err;
+ }
+ } else {
+ /* Before Reading DMA status to figure out number
+ * of bytes transferred by DMA channel:
+ * Change the client associated with the DMA channel
+ * to stop DMA engine from starting any more bursts for
+ * the given client and wait for in flight bursts to complete
+ */
+ tegra_dma_reset_client(tdc);
+
+ /* Wait for in flight data transfer to finish */
+ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
+
+ /* If TX/RX path is still active wait till it becomes
+ * inactive
+ */
+
+ if (readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset +
+ TEGRA_GPCDMA_CHAN_STATUS,
+ status,
+ !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
+ TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
+ 5,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT)) {
+ dev_dbg(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
+ tegra_dma_dump_chan_regs(tdc);
+ }
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tdc->isr_handler(tdc, true);
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ }
+
+ was_busy = tdc->busy;
+
+ tegra_dma_stop(tdc);
+ if (tdc->dma_desc && was_busy)
+ tdc->dma_desc->bytes_transferred +=
+ tdc->dma_desc->bytes_requested - (wcount * 4);
+
+skip_dma_stop:
+ tegra_dma_abort_all(tdc);
+ vchan_free_chan_resources(&tdc->vc);
+ if (tdc->is_pending) {
+ tdc->is_pending = false;
+ kfree(tdc->dma_desc);
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc = NULL;
+ struct virt_dma_desc *vd;
+ unsigned int residual;
+ enum dma_status ret;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+
+ vd = vchan_find_desc(&tdc->vc, cookie);
+ if (vd)
+ dma_desc = vd_to_tegra_dma_desc(vd);
+
+ if (dma_desc) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ kfree(dma_desc);
+ } else {
+ dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+static inline int get_bus_width(struct tegra_dma_channel *tdc,
+ enum dma_slave_buswidth slave_bw)
+{
+ switch (slave_bw) {
+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ default:
+ dev_err(tdc2dev(tdc), "given slave bw is not supported\n");
+ return -EINVAL;
+ }
+}
+
+static inline int get_burst_size_by_len(int len)
+{
+ int ret;
+
+ switch (len) {
+ case BIT(0) ... BIT(2):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ break;
+ case BIT(3):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ break;
+ case BIT(4):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ break;
+ case BIT(5):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ break;
+ default:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ break;
+ }
+
+ return ret;
+}
+
+static inline int get_burst_size(struct tegra_dma_channel *tdc,
+ u32 burst_size,
+ enum dma_slave_buswidth slave_bw,
+ int len)
+{
+ int burst_mmio_width, burst_byte, ret;
+
+ /*
+ * burst_size from client is in terms of the bus_width.
+ * convert that into words.
+ */
+ burst_byte = burst_size * slave_bw;
+ burst_mmio_width = burst_byte / 4;
+
+ switch (burst_mmio_width) {
+ case 0:
+ ret = get_burst_size_by_len(len);
+ break;
+ case 1:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ break;
+ case 2 ... 3:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ break;
+ case 4 ... 7:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ break;
+ case 8 ... 15:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ break;
+ default:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ break;
+ }
+
+ return ret;
+}
+
+static int get_transfer_param(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction,
+ unsigned long *apb_addr,
+ unsigned long *mmio_seq,
+ unsigned long *csr,
+ unsigned int *burst_size,
+ enum dma_slave_buswidth *slave_bw)
+{
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ *apb_addr = tdc->dma_sconfig.dst_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
+ *burst_size = tdc->dma_sconfig.dst_maxburst;
+ *slave_bw = tdc->dma_sconfig.dst_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
+ return 0;
+
+ case DMA_DEV_TO_MEM:
+ *apb_addr = tdc->dma_sconfig.src_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
+ *burst_size = tdc->dma_sconfig.src_maxburst;
+ *slave_bw = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
+ return 0;
+ case DMA_MEM_TO_MEM:
+ *burst_size = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ return 0;
+ default:
+ dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
+ return -EINVAL;
+ }
+ return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
+ size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ /* Set dma mode to fixed pattern */
+ csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ dma_desc->ch_regs.src_ptr = 0;
+ dma_desc->ch_regs.dst_ptr = dest;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ dma_desc->ch_regs.fixed_pattern = value;
+ /* Word count reg takes value as (N +1) words */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = 0;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+
+ tdc->dma_desc = dma_desc;
+
+ if (!tdc->isr_handler)
+ tdc->isr_handler = handle_once_dma_done;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
+ dma_addr_t src, size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ /* Set dma mode to memory to memory transfer */
+ csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
+ (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (src & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ dma_desc->ch_regs.src_ptr = src;
+ dma_desc->ch_regs.dst_ptr = dest;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
+ dma_desc->ch_regs.high_addr_ptr |=
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ /* Word count reg takes value as (N +1) words */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = 0;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+
+ if (!tdc->isr_handler)
+ tdc->isr_handler = handle_once_dma_done;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_desc *dma_desc;
+ struct scatterlist *sg;
+ u32 burst_size;
+ unsigned int i;
+ int ret;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "dma channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
+ &burst_size, &slave_bw);
+ if (ret < 0)
+ return NULL;
+
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Program the slave id in requestor select */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Configure default priority weight for the channel*/
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping on both MC and MMIO side */
+
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
+
+ /* Program 2 MC outstanding requests by default. */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+
+ /* Setting MC burst size depending on MMIO burst size */
+ if (burst_size == 64)
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+ else
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len;
+ dma_addr_t mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
+ dma_desc->bytes_requested += len;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ dma_desc->ch_regs.src_ptr = mem;
+ dma_desc->ch_regs.dst_ptr = apb_ptr;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
+ } else if (direction == DMA_DEV_TO_MEM) {
+ dma_desc->ch_regs.src_ptr = apb_ptr;
+ dma_desc->ch_regs.dst_ptr = mem;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
+ }
+
+ /*
+ * Word count register takes input in words. Writing a value
+ * of N into word count register means a req of (N+1) words.
+ */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = mmio_seq;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+ tdc->dma_desc = dma_desc;
+ }
+
+ /*
+ * Make sure that mode should not be conflicting with currently
+ * configured mode.
+ */
+ if (!tdc->isr_handler)
+ tdc->isr_handler = handle_once_dma_done;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ dma_cookie_init(&tdc->vc.chan);
+ tdc->config_init = false;
+ return 0;
+}
+
+static void tegra_dma_chan_synchronize(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ vchan_synchronize(&tdc->vc);
+}
+
+static void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ if (tdc->busy)
+ tegra_dma_terminate_all(dc);
+
+ tegra_dma_chan_synchronize(dc);
+
+ tasklet_kill(&tdc->vc.task);
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ tdc->config_init = false;
+ tdc->isr_handler = NULL;
+ tdc->slave_id = -1;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct tegra_dma_channel *tdc;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ tdc = to_tegra_dma_chan(chan);
+ tdc->slave_id = dma_spec->args[0];
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
+ .nr_channels = 31,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = false,
+};
+
+static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
+ .nr_channels = 31,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+};
+
+static const struct of_device_id tegra_dma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra186-gpcdma",
+ .data = &tegra186_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra194-gpcdma",
+ .data = &tegra194_dma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+
+static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
+ int chan, int stream_id)
+{
+ unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ return 0;
+}
+
+static int tegra_dma_probe(struct platform_device *pdev)
+{
+ const struct tegra_dma_chip_data *cdata = NULL;
+ const unsigned int start_chan_idx = 1;
+ unsigned int stream_id, i;
+ struct tegra_dma *tdma;
+ struct resource *res;
+ int ret;
+
+ cdata = of_device_get_match_data(&pdev->dev);
+
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "nvidia,stream-id", &stream_id);
+ if (ret)
+ stream_id = TEGRA186_SID_GPCDMA_0;
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ if (IS_ERR(tdma->rst)) {
+ if (!(PTR_ERR(tdma->rst) == -EPROBE_DEFER))
+ dev_err(&pdev->dev, "Missing controller reset\n");
+ return PTR_ERR(tdma->rst);
+ }
+ reset_control_reset(tdma->rst);
+
+ tdma->dma_dev.dev = &pdev->dev;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
+ start_chan_idx * cdata->channel_reg_size +
+ i * cdata->channel_reg_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ,
+ start_chan_idx + i);
+ if (!res) {
+ ret = -EINVAL;
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ goto err_irq;
+ }
+ tdc->irq = res->start;
+ snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+
+ tdc->tdma = tdma;
+ tdc->id = i;
+ tdc->slave_id = -1;
+
+ vchan_init(&tdc->vc, &tdma->dma_dev);
+ tdc->vc.desc_free = tegra_dma_desc_free;
+ raw_spin_lock_init(&tdc->lock);
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, i, stream_id);
+ tdc->stream_id = stream_id;
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
+
+ /*
+ * Only word aligned transfers are supported. Set the copy
+ * alignment shift.
+ */
+ tdma->dma_dev.copy_align = 2;
+ tdma->dma_dev.fill_align = 2;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
+ tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
+ tdma->dma_dev.device_config = tegra_dma_slave_config;
+ tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ /* Register DMA channel interrupt handlers after everything is setup */
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "request_irq failed with err %d channel %d\n",
+ i, ret);
+ goto err_irq;
+ }
+ }
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "GPC DMA driver registration failed %d\n", ret);
+ goto err_irq;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "GPC DMA OF registration failed %d\n", ret);
+ goto err_unregister_dma_dev;
+ }
+
+ dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
+ cdata->nr_channels);
+
+ return 0;
+
+err_unregister_dma_dev:
+ dma_async_device_unregister(&tdma->dma_dev);
+err_irq:
+ return ret;
+}
+
+static int tegra_dma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ return 0;
+}
+
+/*
+ * Save and restore csr and channel register on pm_suspend
+ * and pm_resume respectively
+ */
+static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned long flags;
+ unsigned int i;
+ bool busy;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ busy = tdc->busy;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+
+ if (busy) {
+ dev_err(tdma->dev, "channel %u busy\n", i);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned int i;
+
+ reset_control_reset(tdma->rst);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tegra_dma_program_sid(tdc, i, tdc->stream_id);
+ }
+
+ return 0;
+}
+
+static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
+};
+
+static struct platform_driver tegra_dmac_driver = {
+ .driver = {
+ .name = "tegra-gpcdma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_dma_dev_pm_ops,
+ .of_match_table = tegra_dma_of_match,
+ },
+ .probe = tegra_dma_probe,
+ .remove = tegra_dma_remove,
+};
+
+module_platform_driver(tegra_dmac_driver);
+
+MODULE_ALIAS("platform:tegra-gpc-dma");
+MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
+MODULE_AUTHOR("Pavan Kunapuli <[email protected]>");
+MODULE_AUTHOR("Rajesh Gumasta <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 ++++++++++++++++++++++++++
3 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index fcd71bf..71dd10e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -56,6 +56,10 @@
};
};
+ dma@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index d02f6bf..9b565155 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -73,6 +73,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x2600000 0x0 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ nvidia,start-dma-channel-index = <1>;
+ dma-channels = <31>;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index b7d5328..bc85c91 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -72,6 +72,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
--
2.7.4
Hi Akhil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on vkoul-dmaengine/next arm64/for-next/core v5.14-rc7 next-20210827]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20210827-150504
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: nds32-allyesconfig (attached as .config)
compiler: nds32le-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/0cc2ab4a5b7f236155b7b7740b26589f0dac8e7c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20210827-150504
git checkout 0cc2ab4a5b7f236155b7b7740b26589f0dac8e7c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=nds32
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_reset_client':
drivers/dma/tegra-gpc-dma.c:62:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
62 | FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
| ^~~~~~~~~~
drivers/dma/tegra-gpc-dma.c:543:16: note: in expansion of macro 'TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED'
543 | csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra-gpc-dma.c:834:74: warning: right shift count >= width of type [-Wshift-count-overflow]
834 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra-gpc-dma.c:905:65: warning: right shift count >= width of type [-Wshift-count-overflow]
905 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
| ^~
drivers/dma/tegra-gpc-dma.c:907:66: warning: right shift count >= width of type [-Wshift-count-overflow]
907 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra-gpc-dma.c:1012:81: warning: right shift count >= width of type [-Wshift-count-overflow]
1012 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
| ^~
drivers/dma/tegra-gpc-dma.c:1017:81: warning: right shift count >= width of type [-Wshift-count-overflow]
1017 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
| ^~
cc1: some warnings being treated as errors
vim +834 drivers/dma/tegra-gpc-dma.c
779
780 static struct dma_async_tx_descriptor *
781 tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
782 size_t len, unsigned long flags)
783 {
784 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
785 struct tegra_dma_desc *dma_desc;
786 unsigned long csr, mc_seq;
787
788 /* Set dma mode to fixed pattern */
789 csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
790 /* Enable once or continuous mode */
791 csr |= TEGRA_GPCDMA_CSR_ONCE;
792 /* Enable IRQ mask */
793 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
794 /* Enable the dma interrupt */
795 if (flags & DMA_PREP_INTERRUPT)
796 csr |= TEGRA_GPCDMA_CSR_IE_EOC;
797 /* Configure default priority weight for the channel */
798 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
799
800 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
801 /* retain stream-id and clean rest */
802 mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
803
804 /* Set the address wrapping */
805 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
806 TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
807 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
808 TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
809
810 /* Program outstanding MC requests */
811 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
812 /* Set burst size */
813 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
814
815 dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
816 if (!dma_desc)
817 return NULL;
818
819 dma_desc->bytes_requested = 0;
820 dma_desc->bytes_transferred = 0;
821
822 if ((len & 3) || (dest & 3) ||
823 len > tdc->tdma->chip_data->max_dma_count) {
824 dev_err(tdc2dev(tdc),
825 "Dma length/memory address is not supported\n");
826 kfree(dma_desc);
827 return NULL;
828 }
829
830 dma_desc->bytes_requested += len;
831 dma_desc->ch_regs.src_ptr = 0;
832 dma_desc->ch_regs.dst_ptr = dest;
833 dma_desc->ch_regs.high_addr_ptr =
> 834 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
835 dma_desc->ch_regs.fixed_pattern = value;
836 /* Word count reg takes value as (N +1) words */
837 dma_desc->ch_regs.wcount = ((len - 4) >> 2);
838 dma_desc->ch_regs.csr = csr;
839 dma_desc->ch_regs.mmio_seq = 0;
840 dma_desc->ch_regs.mc_seq = mc_seq;
841
842 tdc->dma_desc = dma_desc;
843
844 if (!tdc->isr_handler)
845 tdc->isr_handler = handle_once_dma_done;
846
847 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
848 }
849
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Akhil,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on vkoul-dmaengine/next arm64/for-next/core v5.14-rc7 next-20210827]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20210827-150504
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-buildonly-randconfig-r005-20210827 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 1076082a0d97bd5c16a25ee7cf3dbb6ee4b5a9fe)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/0day-ci/linux/commit/0cc2ab4a5b7f236155b7b7740b26589f0dac8e7c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20210827-150504
git checkout 0cc2ab4a5b7f236155b7b7740b26589f0dac8e7c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All error/warnings (new ones prefixed by >>):
>> drivers/dma/tegra-gpc-dma.c:543:9: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
^
drivers/dma/tegra-gpc-dma.c:62:6: note: expanded from macro 'TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED'
FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
^
drivers/dma/tegra-gpc-dma.c:671:10: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
^
drivers/dma/tegra-gpc-dma.c:114:6: note: expanded from macro 'TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8'
FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
^
drivers/dma/tegra-gpc-dma.c:688:9: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
^
drivers/dma/tegra-gpc-dma.c:122:6: note: expanded from macro 'TEGRA_GPCDMA_MMIOSEQ_BURST_1'
FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 0)
^
drivers/dma/tegra-gpc-dma.c:726:9: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
^
drivers/dma/tegra-gpc-dma.c:122:6: note: expanded from macro 'TEGRA_GPCDMA_MMIOSEQ_BURST_1'
FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 0)
^
drivers/dma/tegra-gpc-dma.c:759:10: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
*csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
^
drivers/dma/tegra-gpc-dma.c:54:6: note: expanded from macro 'TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC'
FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
^
drivers/dma/tegra-gpc-dma.c:789:8: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
^
drivers/dma/tegra-gpc-dma.c:58:6: note: expanded from macro 'TEGRA_GPCDMA_CSR_DMA_FIXED_PAT'
FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
^
>> drivers/dma/tegra-gpc-dma.c:834:53: warning: shift count >= width of type [-Wshift-count-overflow]
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
^ ~~
drivers/dma/tegra-gpc-dma.c:859:8: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
^
drivers/dma/tegra-gpc-dma.c:56:6: note: expanded from macro 'TEGRA_GPCDMA_CSR_DMA_MEM2MEM'
FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
^
drivers/dma/tegra-gpc-dma.c:905:51: warning: shift count >= width of type [-Wshift-count-overflow]
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
^ ~~
drivers/dma/tegra-gpc-dma.c:907:52: warning: shift count >= width of type [-Wshift-count-overflow]
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
^ ~~
drivers/dma/tegra-gpc-dma.c:951:9: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
^
drivers/dma/tegra-gpc-dma.c:1012:53: warning: shift count >= width of type [-Wshift-count-overflow]
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
^ ~~
drivers/dma/tegra-gpc-dma.c:1017:53: warning: shift count >= width of type [-Wshift-count-overflow]
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
^ ~~
drivers/dma/tegra-gpc-dma.c:1128:13: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
^
>> drivers/dma/tegra-gpc-dma.c:1322:21: warning: attribute declaration must precede definition [-Wignored-attributes]
static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
^
include/linux/compiler_attributes.h:287:56: note: expanded from macro '__maybe_unused'
#define __maybe_unused __attribute__((__unused__))
^
include/linux/pm.h:277:8: note: previous definition is here
struct dev_pm_ops {
^
6 warnings and 9 errors generated.
vim +/FIELD_PREP +543 drivers/dma/tegra-gpc-dma.c
537
538 static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
539 {
540 u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
541
542 csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
> 543 csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
544 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
545 }
546
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
On 27/08/2021 07:04, Akhil R wrote:
> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
> supports dma transfers between memory to memory, IO peripheral to memory
> and memory to IO peripheral.
>
> Signed-off-by: Pavan Kunapuli <[email protected]>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/tegra-gpc-dma.c | 1343 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1356 insertions(+)
> create mode 100644 drivers/dma/tegra-gpc-dma.c
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 39b5b46..9d1d93d 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -632,6 +632,18 @@ config TEGRA210_ADMA
> peripheral and vice versa. It does not support memory to
> memory data transfer.
>
> +config TEGRA_GPC_DMA
> + tristate "NVIDIA Tegra GPC DMA support"
> + depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
> + select DMA_ENGINE
> + help
> + Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
> + driver. The DMA controller has multiple DMA channels which can
> + be configured for different peripherals like UART, SPI, etc
> + which are on APB bus.
> + This DMA controller transfers data from memory to peripheral FIFO
> + or vice versa. It also supports memory to memory data transfer.
> +
> config TIMB_DMA
> tristate "Timberdale FPGA DMA support"
> depends on MFD_TIMBERDALE || COMPILE_TEST
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index aa69094..943e8d7 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -73,6 +73,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
> obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
> obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
> obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
> +obj-$(CONFIG_TEGRA_GPC_DMA) += tegra-gpc-dma.o
> obj-$(CONFIG_TIMB_DMA) += timb_dma.o
> obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
> obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o
> diff --git a/drivers/dma/tegra-gpc-dma.c b/drivers/dma/tegra-gpc-dma.c
> new file mode 100644
> index 0000000..d990121
> --- /dev/null
> +++ b/drivers/dma/tegra-gpc-dma.c
> @@ -0,0 +1,1343 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller.
> + *
> + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mm.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_dma.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +#include <linux/version.h>
> +#include <dt-bindings/memory/tegra186-mc.h>
> +#include "virt-dma.h"
> +
> +/* CSR register */
> +#define TEGRA_GPCDMA_CHAN_CSR 0x00
> +#define TEGRA_GPCDMA_CSR_ENB BIT(31)
> +#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
> +#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
> +
> +#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
> +#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
> +#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
> +#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
> +#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
> +
> +#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
> +#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
> +#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
> +#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
> +#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
> +#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
> +#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
> +
> +#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
> +#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
> + FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
> +#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
> +#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
> +
> +/* STATUS register */
> +#define TEGRA_GPCDMA_CHAN_STATUS 0x004
> +#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
> +#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
> +#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
> +#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
> +#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
> +#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
> +#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
> +#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
> +#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
> +#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
> +
> +#define TEGRA_GPCDMA_CHAN_CSRE 0x008
> +#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
> +
> +/* Source address */
> +#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
> +
> +/* Destination address */
> +#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
> +
> +/* High address pointer */
> +#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
> +#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
> +#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
> +
> +/* MC sequence register */
> +#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
> +#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
> +#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
> +#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
> +#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
> + FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
> +#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
> + FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
> +#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
> +#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
> +#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
> +
> +#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
> +#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
> +
> +/* MMIO sequence register */
> +#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
> +#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
> +#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
> +#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
> +#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
> +#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
> +#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
> +#define TEGRA_GPCDMA_MMIOSEQ_BURST GENMASK(26, 23)
> +#define TEGRA_GPCDMA_MMIOSEQ_BURST_1 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 0)
> +#define TEGRA_GPCDMA_MMIOSEQ_BURST_2 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 1)
> +#define TEGRA_GPCDMA_MMIOSEQ_BURST_4 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 3)
> +#define TEGRA_GPCDMA_MMIOSEQ_BURST_8 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 7)
> +#define TEGRA_GPCDMA_MMIOSEQ_BURST_16 \
> + FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 15)
> +#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
> +#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
> +#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
> +
> +/* Channel WCOUNT */
> +#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
> +
> +/* Transfer count */
> +#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
> +
> +/* DMA byte count status */
> +#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
> +
> +/* Error Status Register */
> +#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
> +#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT (8)
> +#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK (0xF)
> +#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
> + ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
> + TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
> +#define TEGRA_DMA_BM_FIFO_FULL_ERR (0xF)
> +#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR (0xE)
> +#define TEGRA_DMA_PERIPH_ID_ERR (0xD)
> +#define TEGRA_DMA_STREAM_ID_ERR (0xC)
> +#define TEGRA_DMA_MC_SLAVE_ERR (0xB)
> +#define TEGRA_DMA_MMIO_SLAVE_ERR (0xA)
> +
> +/* Fixed Pattern */
> +#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
> +
> +#define TEGRA_GPCDMA_CHAN_TZ 0x38
> +#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
> +#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
> +
> +#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
> +#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
> +
> +/*
> + * If any burst is in flight and DMA paused then this is the time to complete
> + * on-flight burst and update DMA status register.
> + */
> +#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
> +#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
> +
> +/* Channel base address offset from GPCDMA base address */
> +#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
> +
> +struct tegra_dma;
> +
> +/*
> + * tegra_dma_chip_data Tegra chip specific DMA data
> + * @nr_channels: Number of channels available in the controller.
> + * @channel_reg_size: Channel register size.
> + * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
> + * @hw_support_pause: DMA HW engine support pause of the channel.
> + */
> +struct tegra_dma_chip_data {
> + int nr_channels;
> + int channel_reg_size;
> + int max_dma_count;
> + bool hw_support_pause;
> +};
> +
> +/* DMA channel registers */
> +struct tegra_dma_channel_regs {
> + unsigned long csr;
> + unsigned long src_ptr;
> + unsigned long dst_ptr;
> + unsigned long high_addr_ptr;
> + unsigned long mc_seq;
> + unsigned long mmio_seq;
> + unsigned long wcount;
> + unsigned long fixed_pattern;
> +};
> +
> +/*
> + * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
> + * manage client request and keep track of transfer status, callbacks
> + * and request counts etc.
> + */
> +struct tegra_dma_desc {
> + struct virt_dma_desc vd;
> + int bytes_requested;
> + int bytes_transferred;
> + struct tegra_dma_channel *tdc;
> + struct tegra_dma_channel_regs ch_regs;
> +};
> +
> +struct tegra_dma_channel;
> +
> +typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
> + bool to_terminate);
> +
> +/*
> + * tegra_dma_channel: Channel specific information
> + */
> +struct tegra_dma_channel {
> + struct virt_dma_chan vc;
> + struct tegra_dma_desc *dma_desc;
> + char name[30];
> + bool config_init;
> + int id;
> + int irq;
> + unsigned int stream_id;
> + unsigned long chan_base_offset;
> + raw_spinlock_t lock;
> + bool busy;
> + bool is_pending;
> + struct tegra_dma *tdma;
> + dma_isr_handler isr_handler;
> + int slave_id;
> + struct dma_slave_config dma_sconfig;
> +};
> +
> +/*
> + * tegra_dma: Tegra DMA specific information
> + */
> +struct tegra_dma {
> + struct dma_device dma_dev;
> + struct device *dev;
> + void __iomem *base_addr;
> + const struct tegra_dma_chip_data *chip_data;
> + struct reset_control *rst;
> + struct tegra_dma_channel channels[0];
> +};
> +
> +static inline void tdc_write(struct tegra_dma_channel *tdc,
> + u32 reg, u32 val)
> +{
> + writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
> +}
> +
> +static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
> +{
> + return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
> +}
> +
> +static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
> +{
> + return container_of(dc, struct tegra_dma_channel, vc.chan);
> +}
> +
> +static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
> +{
> + return container_of(vd, struct tegra_dma_desc, vd);
> +}
> +
> +static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
> +{
> + return tdc->vc.chan.device->dev;
> +}
> +
> +static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
> +{
> + dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
> + tdc->id, tdc->name);
> + dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
> + );
> + dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
> + );
> + dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
> + tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
> +}
> +
> +static void tegra_dma_desc_free(struct virt_dma_desc *vd)
> +{
> + struct tegra_dma_desc *dma_desc = vd_to_tegra_dma_desc(vd);
> + struct tegra_dma_channel *tdc = dma_desc->tdc;
> + unsigned long flags;
> +
> + if (dma_desc) {
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> + kfree(dma_desc);
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + }
> +}
I think that this can be simplified to simply ...
static void tegra_dma_desc_free(struct virt_dma_desc *vd)
{
kfree(container_of(vd, struct tegra_dma_desc, vd));
}
> +
> +static int tegra_dma_slave_config(struct dma_chan *dc,
> + struct dma_slave_config *sconfig)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> +
> + if (tdc->dma_desc) {
Any reason not to check config_init here instead?
> + dev_err(tdc2dev(tdc), "Configuration not allowed\n");
> + return -EBUSY;
> + }
> +
> + memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
> + if (tdc->slave_id == -1)
> + tdc->slave_id = sconfig->slave_id;
How do you ensure that you are not trying to use an ID that is already
being used? If you look at the tegra210-adma.c driver you will see that
we have a bit mask for determining if the IDs are in used or not (see
tx_requests_reserved and rx_requests_reserved).
> + tdc->config_init = true;
> + return 0;
> +}
> +
> +static int tegra_dma_pause(struct tegra_dma_channel *tdc)
> +{
> + u32 val;
> + int ret;
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
> +
> + /* Wait until busy bit is de-asserted */
> + ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
> + tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
> + val,
> + !(val & TEGRA_GPCDMA_STATUS_BUSY),
> + TEGRA_GPCDMA_BURST_COMPLETE_TIME,
> + TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
> +
> + if (ret)
> + dev_err(tdc2dev(tdc), "DMA pause timed out\n");
> +
> + return ret;
> +}
> +
> +static void tegra_dma_stop(struct tegra_dma_channel *tdc)
> +{
> + u32 csr, status;
> +
> + csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
> +
> + /* Disable interrupts */
> + csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
> +
> + /* Disable DMA */
> + csr &= ~TEGRA_GPCDMA_CSR_ENB;
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
> +
> + /* Clear interrupt status if it is there */
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
> + dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
> + }
> + tdc->busy = false;
> +}
> +
> +static void tegra_dma_start(struct tegra_dma_channel *tdc)
> +{
> + struct tegra_dma_channel_regs *ch_regs = &tdc->dma_desc->ch_regs;
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
> +
> + /* Start DMA */
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
> + ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
> +}
> +
> +static void tdc_start_head_req(struct tegra_dma_channel *tdc)
> +{
> + struct virt_dma_desc *vdesc;
> +
> + if (tdc->is_pending)
> + return;
> +
> + vdesc = vchan_next_desc(&tdc->vc);
> + if (!vdesc)
> + return;
> +
> + tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
> + if (!tdc->dma_desc)
> + return;
> +
> + list_del(&vdesc->node);
> +
> + tdc->is_pending = true;
Is is_pending really needed?
> + tdc->dma_desc->tdc = tdc;
> + tegra_dma_start(tdc);
I would combine this function and tegra_dma_start() into a single
function called tegra_dma_start().
> + tdc->busy = true;
> +}
> +
> +static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
> +{
> + kfree(tdc->dma_desc);
> + tdc->isr_handler = NULL;
> +}
> +
> +static void handle_once_dma_done(struct tegra_dma_channel *tdc,
> + bool to_terminate)
This function name is not very descriptive. Maybe just
tegra_dma_isr_callback().
> +{
> + struct tegra_dma_desc *dma_desc;
> +
> + tdc->busy = false;
> + dma_desc = tdc->dma_desc;
> + dma_desc->bytes_transferred += dma_desc->bytes_requested;
> +
> + vchan_cookie_complete(&tdc->dma_desc->vd);
> + tdc->is_pending = false;
> + kfree(tdc->dma_desc);
> +
> + if (to_terminate)
> + return;
> +
> + tdc_start_head_req(tdc);
> +}
> +
> +static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
> + unsigned int err_status)
> +{
> + switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
> + case TEGRA_DMA_BM_FIFO_FULL_ERR:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d bm fifo full\n", tdc->id);
> + break;
> +
> + case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d peripheral fifo full\n", tdc->id);
> + break;
> +
> + case TEGRA_DMA_PERIPH_ID_ERR:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d illegal peripheral id\n", tdc->id);
> + break;
> +
> + case TEGRA_DMA_STREAM_ID_ERR:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d illegal stream id\n", tdc->id);
> + break;
> +
> + case TEGRA_DMA_MC_SLAVE_ERR:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d mc slave error\n", tdc->id);
> + break;
> +
> + case TEGRA_DMA_MMIO_SLAVE_ERR:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d mmio slave error\n", tdc->id);
> + break;
> +
> + default:
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d security violation %x\n", tdc->id,
> + err_status);
> + }
> +}
> +
> +static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
> +{
> + struct tegra_dma_channel *tdc = dev_id;
> + irqreturn_t ret = IRQ_NONE;
> + unsigned int err_status;
> + unsigned long status;
> +
> + raw_spin_lock(&tdc->lock);
> +
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + err_status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
> +
> + if (err_status) {
> + tegra_dma_chan_decode_error(tdc, err_status);
> + tegra_dma_dump_chan_regs(tdc);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
> + }
> +
> + if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
> + TEGRA_GPCDMA_STATUS_ISE_EOC);
> + if (tdc->isr_handler) {
> + tdc->isr_handler(tdc, false);
> + } else {
> + dev_err(tdc->tdma->dev,
> + "GPCDMA CH%d: status %lx ISR handler absent!\n",
> + tdc->id, status);
> + tegra_dma_dump_chan_regs(tdc);
> + }
> + ret = IRQ_HANDLED;
> + }
> +
> + raw_spin_unlock(&tdc->lock);
> + return ret;
> +}
> +
> +static void tegra_dma_issue_pending(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> +
> + if (!tdc->busy)
> + if (vchan_issue_pending(&tdc->vc))
> + tdc_start_head_req(tdc);
> +
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> +}
> +
> +static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
> +{
> + u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
> +
> + csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
> + csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
> +}
> +
> +static int tegra_dma_terminate_all(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + unsigned long wcount = 0;
> + unsigned long status;
> + unsigned long flags;
> + bool was_busy;
> + int err;
> +
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> +
> + if (!tdc->dma_desc) {
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return 0;
> + }
> +
> + if (!tdc->busy)
> + goto skip_dma_stop;
> +
> + if (tdc->tdma->chip_data->hw_support_pause) {
> + err = tegra_dma_pause(tdc);
> + if (err) {
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return err;
> + }
> + } else {
> + /* Before Reading DMA status to figure out number
> + * of bytes transferred by DMA channel:
> + * Change the client associated with the DMA channel
> + * to stop DMA engine from starting any more bursts for
> + * the given client and wait for in flight bursts to complete
> + */
> + tegra_dma_reset_client(tdc);
> +
> + /* Wait for in flight data transfer to finish */
> + udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
> +
> + /* If TX/RX path is still active wait till it becomes
> + * inactive
> + */
> +
> + if (readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
> + tdc->chan_base_offset +
> + TEGRA_GPCDMA_CHAN_STATUS,
> + status,
> + !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
> + TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
> + 5,
> + TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT)) {
> + dev_dbg(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
> + tegra_dma_dump_chan_regs(tdc);
> + }
I would be tempted to make the code in the 'else' clause
tegra_dma_sw_pause(). Then you could have tegra_dma_hw_pause() and
tegra_dma_sw_pause().
> + }
> +
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
> + if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
> + dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
> + tdc->isr_handler(tdc, true);
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
> + }
> +
> + was_busy = tdc->busy;
> +
> + tegra_dma_stop(tdc);
> + if (tdc->dma_desc && was_busy)
> + tdc->dma_desc->bytes_transferred +=
> + tdc->dma_desc->bytes_requested - (wcount * 4);
> +
> +skip_dma_stop:
> + tegra_dma_abort_all(tdc);
> + vchan_free_chan_resources(&tdc->vc);
> + if (tdc->is_pending) {
> + tdc->is_pending = false;
> + kfree(tdc->dma_desc);
> + }
> +
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return 0;
> +}
> +
> +static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
> + dma_cookie_t cookie,
> + struct dma_tx_state *txstate)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + struct tegra_dma_desc *dma_desc = NULL;
> + struct virt_dma_desc *vd;
> + unsigned int residual;
> + enum dma_status ret;
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> +
> + ret = dma_cookie_status(dc, cookie, txstate);
> + if (ret == DMA_COMPLETE) {
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return ret;
> + }
> +
> + vd = vchan_find_desc(&tdc->vc, cookie);
> + if (vd)
> + dma_desc = vd_to_tegra_dma_desc(vd);
> +
> + if (dma_desc) {
> + residual = dma_desc->bytes_requested -
> + (dma_desc->bytes_transferred %
> + dma_desc->bytes_requested);
> + dma_set_residue(txstate, residual);
> + kfree(dma_desc);
> + } else {
> + dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
> + }
> +
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return ret;
> +}
> +
> +static inline int get_bus_width(struct tegra_dma_channel *tdc,
> + enum dma_slave_buswidth slave_bw)
> +{
> + switch (slave_bw) {
> + case DMA_SLAVE_BUSWIDTH_1_BYTE:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
> + case DMA_SLAVE_BUSWIDTH_2_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
> + default:
> + dev_err(tdc2dev(tdc), "given slave bw is not supported\n");
> + return -EINVAL;
> + }
> +}
> +
> +static inline int get_burst_size_by_len(int len)
> +{
> + int ret;
> +
> + switch (len) {
> + case BIT(0) ... BIT(2):
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
> + break;
> + case BIT(3):
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
> + break;
> + case BIT(4):
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
> + break;
> + case BIT(5):
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
> + break;
> + default:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static inline int get_burst_size(struct tegra_dma_channel *tdc,
> + u32 burst_size,
> + enum dma_slave_buswidth slave_bw,
> + int len)
> +{
> + int burst_mmio_width, burst_byte, ret;
> +
> + /*
> + * burst_size from client is in terms of the bus_width.
> + * convert that into words.
> + */
> + burst_byte = burst_size * slave_bw;
> + burst_mmio_width = burst_byte / 4;
> +
> + switch (burst_mmio_width) {
> + case 0:
> + ret = get_burst_size_by_len(len);
> + break;
> + case 1:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
> + break;
> + case 2 ... 3:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
> + break;
> + case 4 ... 7:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
> + break;
> + case 8 ... 15:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
> + break;
> + default:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static int get_transfer_param(struct tegra_dma_channel *tdc,
> + enum dma_transfer_direction direction,
> + unsigned long *apb_addr,
> + unsigned long *mmio_seq,
> + unsigned long *csr,
> + unsigned int *burst_size,
> + enum dma_slave_buswidth *slave_bw)
> +{
> + switch (direction) {
> + case DMA_MEM_TO_DEV:
> + *apb_addr = tdc->dma_sconfig.dst_addr;
> + *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
> + *burst_size = tdc->dma_sconfig.dst_maxburst;
> + *slave_bw = tdc->dma_sconfig.dst_addr_width;
> + *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
> + return 0;
> +
> + case DMA_DEV_TO_MEM:
> + *apb_addr = tdc->dma_sconfig.src_addr;
> + *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
> + *burst_size = tdc->dma_sconfig.src_maxburst;
> + *slave_bw = tdc->dma_sconfig.src_addr_width;
> + *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
> + return 0;
> + case DMA_MEM_TO_MEM:
> + *burst_size = tdc->dma_sconfig.src_addr_width;
> + *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
> + return 0;
> + default:
> + dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
> + return -EINVAL;
> + }
> + return -EINVAL;
> +}
> +
> +static struct dma_async_tx_descriptor *
> +tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
> + size_t len, unsigned long flags)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + struct tegra_dma_desc *dma_desc;
> + unsigned long csr, mc_seq;
> +
> + /* Set dma mode to fixed pattern */
> + csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
> + /* Enable once or continuous mode */
> + csr |= TEGRA_GPCDMA_CSR_ONCE;
> + /* Enable IRQ mask */
> + csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
> + /* Enable the dma interrupt */
> + if (flags & DMA_PREP_INTERRUPT)
> + csr |= TEGRA_GPCDMA_CSR_IE_EOC;
> + /* Configure default priority weight for the channel */
> + csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
> +
> + mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
> + /* retain stream-id and clean rest */
> + mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
> +
> + /* Set the address wrapping */
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
> + TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
> + TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
> +
> + /* Program outstanding MC requests */
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
> + /* Set burst size */
> + mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
> +
> + dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
> + if (!dma_desc)
> + return NULL;
> +
> + dma_desc->bytes_requested = 0;
> + dma_desc->bytes_transferred = 0;
> +
> + if ((len & 3) || (dest & 3) ||
> + len > tdc->tdma->chip_data->max_dma_count) {
> + dev_err(tdc2dev(tdc),
> + "Dma length/memory address is not supported\n");
> + kfree(dma_desc);
> + return NULL;
> + }
> +
> + dma_desc->bytes_requested += len;
> + dma_desc->ch_regs.src_ptr = 0;
> + dma_desc->ch_regs.dst_ptr = dest;
> + dma_desc->ch_regs.high_addr_ptr =
> + FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
> + dma_desc->ch_regs.fixed_pattern = value;
> + /* Word count reg takes value as (N +1) words */
> + dma_desc->ch_regs.wcount = ((len - 4) >> 2);
> + dma_desc->ch_regs.csr = csr;
> + dma_desc->ch_regs.mmio_seq = 0;
> + dma_desc->ch_regs.mc_seq = mc_seq;
> +
> + tdc->dma_desc = dma_desc;
> +
> + if (!tdc->isr_handler)
> + tdc->isr_handler = handle_once_dma_done;
Is this actually set to anything other than handle_once_dma_done? In not
you can get rid of the function pointer completely.
> +
> + return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
> + dma_addr_t src, size_t len, unsigned long flags)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + struct tegra_dma_desc *dma_desc;
> + unsigned long csr, mc_seq;
> +
> + /* Set dma mode to memory to memory transfer */
> + csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
> + /* Enable once or continuous mode */
> + csr |= TEGRA_GPCDMA_CSR_ONCE;
> + /* Enable IRQ mask */
> + csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
> + /* Enable the dma interrupt */
> + if (flags & DMA_PREP_INTERRUPT)
> + csr |= TEGRA_GPCDMA_CSR_IE_EOC;
> + /* Configure default priority weight for the channel */
> + csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
> +
> + mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
> + /* retain stream-id and clean rest */
> + mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
> + (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
> +
> + /* Set the address wrapping */
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
> + TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
> + TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
> +
> + /* Program outstanding MC requests */
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
> + /* Set burst size */
> + mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
> +
> + dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
> + if (!dma_desc)
> + return NULL;
> +
> + dma_desc->bytes_requested = 0;
> + dma_desc->bytes_transferred = 0;
> +
> + if ((len & 3) || (src & 3) || (dest & 3) ||
> + len > tdc->tdma->chip_data->max_dma_count) {
> + dev_err(tdc2dev(tdc),
> + "Dma length/memory address is not supported\n");
> + kfree(dma_desc);
> + return NULL;
> + }
> +
> + dma_desc->bytes_requested += len;
> + dma_desc->ch_regs.src_ptr = src;
> + dma_desc->ch_regs.dst_ptr = dest;
> + dma_desc->ch_regs.high_addr_ptr =
> + FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
> + dma_desc->ch_regs.high_addr_ptr |=
> + FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
> + /* Word count reg takes value as (N +1) words */
> + dma_desc->ch_regs.wcount = ((len - 4) >> 2);
> + dma_desc->ch_regs.csr = csr;
> + dma_desc->ch_regs.mmio_seq = 0;
> + dma_desc->ch_regs.mc_seq = mc_seq;
> +
> + if (!tdc->isr_handler)
> + tdc->isr_handler = handle_once_dma_done;
> +
> + return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
> + unsigned int sg_len, enum dma_transfer_direction direction,
> + unsigned long flags, void *context)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
> + enum dma_slave_buswidth slave_bw;
> + struct tegra_dma_desc *dma_desc;
> + struct scatterlist *sg;
> + u32 burst_size;
> + unsigned int i;
> + int ret;
> +
> + if (!tdc->config_init) {
> + dev_err(tdc2dev(tdc), "dma channel is not configured\n");
> + return NULL;
> + }
> + if (sg_len < 1) {
> + dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
> + return NULL;
> + }
> +
> + ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
> + &burst_size, &slave_bw);
> + if (ret < 0)
> + return NULL;
> +
> + /* Enable once or continuous mode */
> + csr |= TEGRA_GPCDMA_CSR_ONCE;
> + /* Program the slave id in requestor select */
> + csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
> + /* Enable IRQ mask */
> + csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
> + /* Configure default priority weight for the channel*/
> + csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
> +
> + /* Enable the dma interrupt */
> + if (flags & DMA_PREP_INTERRUPT)
> + csr |= TEGRA_GPCDMA_CSR_IE_EOC;
> +
> + mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
> + /* retain stream-id and clean rest */
> + mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
> +
> + /* Set the address wrapping on both MC and MMIO side */
> +
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
> + TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
> + TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
> + mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
> +
> + /* Program 2 MC outstanding requests by default. */
> + mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
> +
> + /* Setting MC burst size depending on MMIO burst size */
> + if (burst_size == 64)
> + mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
> + else
> + mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
> +
> + dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
> + if (!dma_desc)
> + return NULL;
> +
> + dma_desc->bytes_requested = 0;
> + dma_desc->bytes_transferred = 0;
> +
> + /* Make transfer requests */
> + for_each_sg(sgl, sg, sg_len, i) {
> + u32 len;
> + dma_addr_t mem;
> +
> + mem = sg_dma_address(sg);
> + len = sg_dma_len(sg);
> +
> + if ((len & 3) || (mem & 3) ||
> + len > tdc->tdma->chip_data->max_dma_count) {
> + dev_err(tdc2dev(tdc),
> + "Dma length/memory address is not supported\n");
> + kfree(dma_desc);
> + return NULL;
> + }
> +
> + mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
> + dma_desc->bytes_requested += len;
> +
> + if (direction == DMA_MEM_TO_DEV) {
> + dma_desc->ch_regs.src_ptr = mem;
> + dma_desc->ch_regs.dst_ptr = apb_ptr;
> + dma_desc->ch_regs.high_addr_ptr =
> + FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
> + } else if (direction == DMA_DEV_TO_MEM) {
> + dma_desc->ch_regs.src_ptr = apb_ptr;
> + dma_desc->ch_regs.dst_ptr = mem;
> + dma_desc->ch_regs.high_addr_ptr =
> + FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
> + }
> +
> + /*
> + * Word count register takes input in words. Writing a value
> + * of N into word count register means a req of (N+1) words.
> + */
> + dma_desc->ch_regs.wcount = ((len - 4) >> 2);
> + dma_desc->ch_regs.csr = csr;
> + dma_desc->ch_regs.mmio_seq = mmio_seq;
> + dma_desc->ch_regs.mc_seq = mc_seq;
> + tdc->dma_desc = dma_desc;
> + }
> +
> + /*
> + * Make sure that mode should not be conflicting with currently
> + * configured mode.
> + */
> + if (!tdc->isr_handler)
> + tdc->isr_handler = handle_once_dma_done;
> +
> + return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
> +}
> +
> +static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> +
> + dma_cookie_init(&tdc->vc.chan);
> + tdc->config_init = false;
> + return 0;
> +}
> +
> +static void tegra_dma_chan_synchronize(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> +
> + vchan_synchronize(&tdc->vc);
> +}
> +
> +static void tegra_dma_free_chan_resources(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + unsigned long flags;
> +
> + dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
> +
> + if (tdc->busy)
> + tegra_dma_terminate_all(dc);
> +
> + tegra_dma_chan_synchronize(dc);
> +
> + tasklet_kill(&tdc->vc.task);
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> + tdc->config_init = false;
> + tdc->isr_handler = NULL;
> + tdc->slave_id = -1;
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> +}
> +
> +static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
> + struct of_dma *ofdma)
> +{
> + struct tegra_dma *tdma = ofdma->of_dma_data;
> + struct tegra_dma_channel *tdc;
> + struct dma_chan *chan;
> +
> + chan = dma_get_any_slave_channel(&tdma->dma_dev);
> + if (!chan)
> + return NULL;
> +
> + tdc = to_tegra_dma_chan(chan);
> + tdc->slave_id = dma_spec->args[0];
> +
> + return chan;
> +}
> +
> +static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
> + .nr_channels = 31,
> + .channel_reg_size = SZ_64K,
> + .max_dma_count = SZ_1G,
> + .hw_support_pause = false,
> +};
> +
> +static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
> + .nr_channels = 31,
> + .channel_reg_size = SZ_64K,
> + .max_dma_count = SZ_1G,
> + .hw_support_pause = true,
> +};
> +
> +static const struct of_device_id tegra_dma_of_match[] = {
> + {
> + .compatible = "nvidia,tegra186-gpcdma",
> + .data = &tegra186_dma_chip_data,
> + }, {
> + .compatible = "nvidia,tegra194-gpcdma",
> + .data = &tegra194_dma_chip_data,
> + }, {
> + },
> +};
> +MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
> +
> +static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
> + int chan, int stream_id)
> +{
> + unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
> +
> + reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
> + reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
> +
> + reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
> + reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
> + return 0;
> +}
> +
> +static int tegra_dma_probe(struct platform_device *pdev)
> +{
> + const struct tegra_dma_chip_data *cdata = NULL;
> + const unsigned int start_chan_idx = 1;
What is this?
> + unsigned int stream_id, i;
> + struct tegra_dma *tdma;
> + struct resource *res;
> + int ret;
> +
> + cdata = of_device_get_match_data(&pdev->dev);
> +
> + ret = of_property_read_u32(pdev->dev.of_node,
> + "nvidia,stream-id", &stream_id);
Property not mentioned in the binding doc.
> + if (ret)
> + stream_id = TEGRA186_SID_GPCDMA_0;
> +
> + tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
> + sizeof(struct tegra_dma_channel), GFP_KERNEL);
> + if (!tdma)
> + return -ENOMEM;
> +
> + tdma->dev = &pdev->dev;
> + tdma->chip_data = cdata;
> + platform_set_drvdata(pdev, tdma);
> +
> + tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(tdma->base_addr))
> + return PTR_ERR(tdma->base_addr);
> +
> + tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
> + if (IS_ERR(tdma->rst)) {
> + if (!(PTR_ERR(tdma->rst) == -EPROBE_DEFER))
> + dev_err(&pdev->dev, "Missing controller reset\n");
dev_err_probe()
> + return PTR_ERR(tdma->rst);
> + }
> + reset_control_reset(tdma->rst);
> +
> + tdma->dma_dev.dev = &pdev->dev;
> +
> + INIT_LIST_HEAD(&tdma->dma_dev.channels);
> + for (i = 0; i < cdata->nr_channels; i++) {
> + struct tegra_dma_channel *tdc = &tdma->channels[i];
> +
> + tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
> + start_chan_idx * cdata->channel_reg_size +
> + i * cdata->channel_reg_size;
> + res = platform_get_resource(pdev, IORESOURCE_IRQ,
> + start_chan_idx + i);
> + if (!res) {
> + ret = -EINVAL;
> + dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
> + goto err_irq;
Is this goto needed?
> + }
> + tdc->irq = res->start;
> + snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
> +
> + tdc->tdma = tdma;
> + tdc->id = i;
> + tdc->slave_id = -1;
> +
> + vchan_init(&tdc->vc, &tdma->dma_dev);
> + tdc->vc.desc_free = tegra_dma_desc_free;
> + raw_spin_lock_init(&tdc->lock);
> +
> + /* program stream-id for this channel */
> + tegra_dma_program_sid(tdc, i, stream_id);
> + tdc->stream_id = stream_id;
> + }
> +
> + dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
> + dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
> + dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
> + dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
> +
> + /*
> + * Only word aligned transfers are supported. Set the copy
> + * alignment shift.
> + */
> + tdma->dma_dev.copy_align = 2;
> + tdma->dma_dev.fill_align = 2;
> + tdma->dma_dev.device_alloc_chan_resources =
> + tegra_dma_alloc_chan_resources;
> + tdma->dma_dev.device_free_chan_resources =
> + tegra_dma_free_chan_resources;
> + tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
> + tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
> + tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
> + tdma->dma_dev.device_config = tegra_dma_slave_config;
> + tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
> + tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
> + tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
> + tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
> + tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
> +
> + /* Register DMA channel interrupt handlers after everything is setup */
> + for (i = 0; i < cdata->nr_channels; i++) {
> + struct tegra_dma_channel *tdc = &tdma->channels[i];
> +
> + ret = devm_request_irq(&pdev->dev, tdc->irq,
> + tegra_dma_isr, 0, tdc->name, tdc);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "request_irq failed with err %d channel %d\n",
> + i, ret);
> + goto err_irq;
> + }
> + }
> +
> + ret = dma_async_device_register(&tdma->dma_dev);
> + if (ret < 0) {
> + dev_err(&pdev->dev,
> + "GPC DMA driver registration failed %d\n", ret);
> + goto err_irq;
> + }
> +
> + ret = of_dma_controller_register(pdev->dev.of_node,
> + tegra_dma_of_xlate, tdma);
> + if (ret < 0) {
> + dev_err(&pdev->dev,
> + "GPC DMA OF registration failed %d\n", ret);
> + goto err_unregister_dma_dev;
> + }
> +
> + dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
> + cdata->nr_channels);
> +
> + return 0;
> +
> +err_unregister_dma_dev:
> + dma_async_device_unregister(&tdma->dma_dev);
> +err_irq:
> + return ret;
> +}
> +
> +static int tegra_dma_remove(struct platform_device *pdev)
> +{
> + struct tegra_dma *tdma = platform_get_drvdata(pdev);
> +
> + of_dma_controller_free(pdev->dev.of_node);
> + dma_async_device_unregister(&tdma->dma_dev);
> +
> + return 0;
> +}
> +
> +/*
> + * Save and restore csr and channel register on pm_suspend
> + * and pm_resume respectively
> + */
> +static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
> +{
> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> + unsigned long flags;
> + unsigned int i;
> + bool busy;
> +
> + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> + struct tegra_dma_channel *tdc = &tdma->channels[i];
> +
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> + busy = tdc->busy;
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> +
> + if (busy) {
> + dev_err(tdma->dev, "channel %u busy\n", i);
> + return -EBUSY;
> + }
> + }
Do we need to ensure that no one attempts to start the DMA after it has
been suspended?
> +
> + return 0;
> +}
> +
> +static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
> +{
> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> + unsigned int i;
> +
> + reset_control_reset(tdma->rst);
> +
> + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> + struct tegra_dma_channel *tdc = &tdma->channels[i];
> +
> + tegra_dma_program_sid(tdc, i, tdc->stream_id);
> + }
> +
> + return 0;
> +}
> +
> +static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
> +};
> +
> +static struct platform_driver tegra_dmac_driver = {
> + .driver = {
> + .name = "tegra-gpcdma",
> + .owner = THIS_MODULE,
> + .pm = &tegra_dma_dev_pm_ops,
> + .of_match_table = tegra_dma_of_match,
> + },
> + .probe = tegra_dma_probe,
> + .remove = tegra_dma_remove,
> +};
> +
> +module_platform_driver(tegra_dmac_driver);
> +
> +MODULE_ALIAS("platform:tegra-gpc-dma");
> +MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
> +MODULE_AUTHOR("Pavan Kunapuli <[email protected]>");
> +MODULE_AUTHOR("Rajesh Gumasta <[email protected]>");
> +MODULE_LICENSE("GPL v2");
>
On 27/08/2021 07:04, Akhil R wrote:
> Add device tree node for GPCDMA controller on Tegra186 target
> and Tegra194 target.
>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 ++++++++++++++++++++++++++
> 3 files changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index fcd71bf..71dd10e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -56,6 +56,10 @@
> };
> };
>
> + dma@2600000 {
> + status = "okay";
> + };
> +
> memory-controller@2c00000 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index d02f6bf..9b565155 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -73,6 +73,52 @@
> snps,rxpbl = <8>;
> };
>
> + gpcdma: dma@2600000 {
> + compatible = "nvidia,tegra186-gpcdma";
> + reg = <0x0 0x2600000 0x0 0x210000>;
> + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> + dma-coherent;
> + nvidia,start-dma-channel-index = <1>;
> + dma-channels = <31>;
The above two properties are not defined in the binding doc and don't
appear to be used.
> + status = "disabled";
> + };
> +
> aconnect@2900000 {
> compatible = "nvidia,tegra186-aconnect",
> "nvidia,tegra210-aconnect";
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index b7d5328..bc85c91 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -72,6 +72,52 @@
> snps,rxpbl = <8>;
> };
>
> + gpcdma: dma@2600000 {
Please correct indentation.
> + compatible = "nvidia,tegra194-gpcdma";
> + reg = <0x2600000 0x210000>;
> + resets = <&bpmp TEGRA194_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> +
> + iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
> + dma-coherent;
> +
> + status = "disabled";
You enable the GPC DMA for Tegra186 but not for Tegra194. Any reason why?
Jon
--
nvpublic
On 27/08/2021 07:04, Akhil R wrote:
> Add DT binding document for Nvidia Tegra GPCDMA controller.
>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> .../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
> new file mode 100644
> index 0000000..39827ab
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
> @@ -0,0 +1,99 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/nvidia,tegra-gpc-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nvidia Tegra GPC DMA Controller Device Tree Bindings
I think we typically say NVIDIA in all caps.
> +
> +description: |
> + Tegra GPC DMA controller is a general purpose dma used for faster data
Maybe worth saying that the GPC DMA is the Genernal Purpose Central
(GPC) DMA controller. Also 'DMA' should be in all caps and not 'dma'.
> + transfers between memory to memory, memory to device and device to memory.
> + Terms 'dma' and 'gpcdma' can be used interchangeably.
Note sure this last sentence really adds any value.
> +
> +maintainers:
> + - Jon Hunter <[email protected]>
> + - Rajesh Gumasta <[email protected]>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + "#dma-cells":
> + const: 1
Good to add a description here. Look at the
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml for
reference.
> +
> + compatible:
> + - enum:
> + - nvidia,tegra186-gpcdma
> + - nvidia,tegra194-gpcdma
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
I believe that this should be 32. Look at the
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml for
reference.
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: gpcdma
> +
> + iommus:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - resets
> + - reset-names
> + - "#dma-cells"
> + - iommus
> +
> +examples:
> + - |
> + gpcdma: dma@2600000 {
> + compatible = "nvidia,tegra186-gpcdma";
> + reg = <0x0 0x2600000 0x0 0x210000>;
> + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH
Please fix indentation.
> + GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
> + GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
Please fix indentation.
> + iommus = <&smmu TEGRA_SID_GPCDMA_0>;
> + dma-coherent;
> + };
> +
> +...
>
Jon
--
nvpublic
On 27/08/2021 07:04, Akhil R wrote:
> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
> supports dma transfers between memory to memory, IO peripheral to memory
> and memory to IO peripheral.
>
> Signed-off-by: Pavan Kunapuli <[email protected]>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/tegra-gpc-dma.c | 1343 +++++++++++++++++++++++++++++++++++++++++++
All the current Tegra DMA driver files are named
drivers/dma/tegraXXX-XXX-dma.c. So we should follow the same convention
here and call this drivers/dma/tegra186-gpc-dma.c.
Cheers
Jon
--
nvpublic
On 27/08/2021 07:04, Akhil R wrote:
> Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
> dma controller driver
>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index f423d08..d247a7e 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -930,6 +930,7 @@ CONFIG_OWL_DMA=y
> CONFIG_PL330_DMA=y
> CONFIG_TEGRA20_APB_DMA=y
> CONFIG_TEGRA210_ADMA=m
> +CONFIG_TEGRA_GPC_DMA=m
Again for consistency please name this CONFIG_TEGRA186_GPC_DMA.
Thanks!
Jon
--
nvpublic
On 01/09/2021 21:56, Jon Hunter wrote:
>
> On 27/08/2021 07:04, Akhil R wrote:
>> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
>> supports dma transfers between memory to memory, IO peripheral to memory
>> and memory to IO peripheral.
>>
>> Signed-off-by: Pavan Kunapuli <[email protected]>
>> Signed-off-by: Rajesh Gumasta <[email protected]>
>> Signed-off-by: Akhil R <[email protected]>
>> ---
>>  drivers/dma/Kconfig        |  12 +
>>  drivers/dma/Makefile       |   1 +
>> Â drivers/dma/tegra-gpc-dma.c | 1343
>> +++++++++++++++++++++++++++++++++++++++++++
>> Â 3 files changed, 1356 insertions(+)
>> Â create mode 100644 drivers/dma/tegra-gpc-dma.c
...
>> +static int tegra_dma_terminate_all(struct dma_chan *dc)
>> +{
>> +Â Â Â struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
>> +Â Â Â unsigned long wcount = 0;
>> +Â Â Â unsigned long status;
>> +Â Â Â unsigned long flags;
>> +Â Â Â bool was_busy;
>> +Â Â Â int err;
>> +
>> +Â Â Â raw_spin_lock_irqsave(&tdc->lock, flags);
>> +
>> +Â Â Â if (!tdc->dma_desc) {
>> +Â Â Â Â Â Â Â raw_spin_unlock_irqrestore(&tdc->lock, flags);
>> +Â Â Â Â Â Â Â return 0;
>> +Â Â Â }
>> +
>> +Â Â Â if (!tdc->busy)
>> +Â Â Â Â Â Â Â goto skip_dma_stop;
>> +
>> +Â Â Â if (tdc->tdma->chip_data->hw_support_pause) {
>> +Â Â Â Â Â Â Â err = tegra_dma_pause(tdc);
>> +Â Â Â Â Â Â Â if (err) {
>> +Â Â Â Â Â Â Â Â Â Â Â raw_spin_unlock_irqrestore(&tdc->lock, flags);
>> +Â Â Â Â Â Â Â Â Â Â Â return err;
>> +Â Â Â Â Â Â Â }
>> +Â Â Â } else {
>> +Â Â Â Â Â Â Â /* Before Reading DMA status to figure out number
>> +Â Â Â Â Â Â Â Â * of bytes transferred by DMA channel:
>> +Â Â Â Â Â Â Â Â * Change the client associated with the DMA channel
>> +Â Â Â Â Â Â Â Â * to stop DMA engine from starting any more bursts for
>> +Â Â Â Â Â Â Â Â * the given client and wait for in flight bursts to complete
>> +Â Â Â Â Â Â Â Â */
>> +Â Â Â Â Â Â Â tegra_dma_reset_client(tdc);
>> +
>> +Â Â Â Â Â Â Â /* Wait for in flight data transfer to finish */
>> +Â Â Â Â Â Â Â udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
>> +
>> +Â Â Â Â Â Â Â /* If TX/RX path is still active wait till it becomes
>> +Â Â Â Â Â Â Â Â * inactive
>> +Â Â Â Â Â Â Â Â */
>> +
>> +Â Â Â Â Â Â Â if (readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â tdc->chan_base_offset +
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â TEGRA_GPCDMA_CHAN_STATUS,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â status,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 5,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT)) {
>> +Â Â Â Â Â Â Â Â Â Â Â dev_dbg(tdc2dev(tdc), "Timeout waiting for DMA burst
>> completion!\n");
>> +Â Â Â Â Â Â Â Â Â Â Â tegra_dma_dump_chan_regs(tdc);
>> +Â Â Â Â Â Â Â }
>
> I would be tempted to make the code in the 'else' clause
> tegra_dma_sw_pause(). Then you could have tegra_dma_hw_pause() and
> tegra_dma_sw_pause().
Thinking some more tegra_dma_hw_pause() and tegra_dma_sw_pause() it not
very clear/accurate. I would be tempted to call these tegra_dma_pause()
and tegra_dma_stop_client() or tegra_dma_stop_transactions(), because
without having a proper hardware pause, you are simply ignoring the
client sync events.
Jon
--
nvpublic
Add support for Nvida Tegra general purpose DMA driver for
Tegra186 and Tegra194 platform.
Changes in patch v4:
Addressed review comments in patch v3
v3 - https://lkml.org/lkml/2021/8/27/34
v2 - https://lkml.org/lkml/2020/8/6/90
v1 - https://lkml.org/lkml/2020/7/20/96
Akhil R (4):
dt-bindings: dmaengine: Add doc for tegra gpcdma
dmaengine: tegra: Add tegra gpcdma driver
arm64: defconfig: tegra: Enable GPCDMA
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 106 ++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 +
arch/arm64/configs/defconfig | 1 +
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1371 ++++++++++++++++++++
8 files changed, 1587 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
create mode 100644 drivers/dma/tegra186-gpc-dma.c
--
2.7.4
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
supports dma transfers between memory to memory, IO peripheral to memory
and memory to IO peripheral.
Signed-off-by: Pavan Kunapuli <[email protected]>
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1371 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 1384 insertions(+)
create mode 100644 drivers/dma/tegra186-gpc-dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 39b5b46..7d7f69f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -632,6 +632,18 @@ config TEGRA210_ADMA
peripheral and vice versa. It does not support memory to
memory data transfer.
+config TEGRA186_GPC_DMA
+ tristate "NVIDIA Tegra GPC DMA support"
+ depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
+ driver. The DMA controller has multiple DMA channels which can
+ be configured for different peripherals like UART, SPI, etc
+ which are on APB bus.
+ This DMA controller transfers data from memory to peripheral FIFO
+ or vice versa. It also supports memory to memory data transfer.
+
config TIMB_DMA
tristate "Timberdale FPGA DMA support"
depends on MFD_TIMBERDALE || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index aa69094..d3941ec 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
+obj-$(CONFIG_TEGRA186_GPC_DMA) += tegra186-gpc-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
new file mode 100644
index 0000000..dcdec7b
--- /dev/null
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -0,0 +1,1371 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller.
+ *
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <dt-bindings/memory/tegra186-mc.h>
+#include "virt-dma.h"
+
+/* CSR register */
+#define TEGRA_GPCDMA_CHAN_CSR 0x00
+#define TEGRA_GPCDMA_CSR_ENB BIT(31)
+#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
+#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
+
+#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
+#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
+#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
+#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
+
+#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
+#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
+
+#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
+#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
+#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
+
+/* STATUS register */
+#define TEGRA_GPCDMA_CHAN_STATUS 0x004
+#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
+#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
+#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
+#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
+#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
+#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
+#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
+
+#define TEGRA_GPCDMA_CHAN_CSRE 0x008
+#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
+
+/* Source address */
+#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
+
+/* Destination address */
+#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
+
+/* High address pointer */
+#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
+#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
+
+/* MC sequence register */
+#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
+#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
+#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
+#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
+#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
+#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
+#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
+
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
+
+/* MMIO sequence register */
+#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
+#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
+#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST GENMASK(26, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_1 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_4 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 7)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 15)
+#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
+#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
+#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
+
+/* Channel WCOUNT */
+#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
+
+/* Transfer count */
+#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
+
+/* DMA byte count status */
+#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
+
+/* Error Status Register */
+#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT (8)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK (0xF)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
+ ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
+ TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
+#define TEGRA_DMA_BM_FIFO_FULL_ERR (0xF)
+#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR (0xE)
+#define TEGRA_DMA_PERIPH_ID_ERR (0xD)
+#define TEGRA_DMA_STREAM_ID_ERR (0xC)
+#define TEGRA_DMA_MC_SLAVE_ERR (0xB)
+#define TEGRA_DMA_MMIO_SLAVE_ERR (0xA)
+
+/* Fixed Pattern */
+#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
+
+#define TEGRA_GPCDMA_CHAN_TZ 0x38
+#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
+#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
+
+#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
+#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
+
+/*
+ * If any burst is in flight and DMA paused then this is the time to complete
+ * on-flight burst and update DMA status register.
+ */
+#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
+#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
+
+/* Channel base address offset from GPCDMA base address */
+#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
+
+struct tegra_dma;
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @hw_support_pause: DMA HW engine support pause of the channel.
+ */
+struct tegra_dma_chip_data {
+ int nr_channels;
+ int channel_reg_size;
+ int max_dma_count;
+ bool hw_support_pause;
+};
+
+/* DMA channel registers */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long src_ptr;
+ unsigned long dst_ptr;
+ unsigned long high_addr_ptr;
+ unsigned long mc_seq;
+ unsigned long mmio_seq;
+ unsigned long wcount;
+ unsigned long fixed_pattern;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
+ * manage client request and keep track of transfer status, callbacks
+ * and request counts etc.
+ */
+struct tegra_dma_desc {
+ struct virt_dma_desc vd;
+ int bytes_requested;
+ int bytes_transferred;
+ struct tegra_dma_channel *tdc;
+ struct tegra_dma_channel_regs ch_regs;
+};
+
+struct tegra_dma_channel;
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct virt_dma_chan vc;
+ struct tegra_dma_desc *dma_desc;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ unsigned int stream_id;
+ unsigned long chan_base_offset;
+ raw_spinlock_t lock;
+ bool busy;
+ struct tegra_dma *tdma;
+ int slave_id;
+ bool sid_reserved;
+ enum dma_transfer_direction sid_dir;
+ struct dma_slave_config dma_sconfig;
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ struct reset_control *rst;
+ unsigned long sid_m2d_reserved;
+ unsigned long sid_d2m_reserved;
+ unsigned long sid_m2m_reserved;
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, vc.chan);
+}
+
+static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct tegra_dma_desc, vd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return tdc->vc.chan.device->dev;
+}
+
+static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
+{
+ dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
+ tdc->id, tdc->name);
+ dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
+ );
+ dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
+ );
+ dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+}
+
+static void tegra_dma_desc_free(struct virt_dma_desc *vd)
+{
+ kfree(container_of(vd, struct tegra_dma_desc, vd));
+}
+
+static int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ if (tdc->dma_desc) {
+ dev_err(tdc2dev(tdc), "Configuration not allowed\n");
+ return -EBUSY;
+ }
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ if (tdc->slave_id == -1)
+ tdc->slave_id = sconfig->slave_id;
+
+ tdc->config_init = true;
+ return 0;
+}
+
+static int tegra_dma_pause(struct tegra_dma_channel *tdc)
+{
+ u32 val;
+ int ret;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
+
+ /* Wait until busy bit is de-asserted */
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ val,
+ !(val & TEGRA_GPCDMA_STATUS_BUSY),
+ TEGRA_GPCDMA_BURST_COMPLETE_TIME,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+
+ if (ret)
+ dev_err(tdc2dev(tdc), "DMA pause timed out\n");
+
+ return ret;
+}
+
+static void tegra_dma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 csr, status;
+
+ csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ /* Disable interrupts */
+ csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
+
+ /* Disable DMA */
+ csr &= ~TEGRA_GPCDMA_CSR_ENB;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+
+ /* Clear interrupt status if it is there */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ }
+ tdc->busy = false;
+}
+
+static void tegra_dma_start(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_channel_regs *ch_regs;
+ struct virt_dma_desc *vdesc;
+
+ if (tdc->busy)
+ return;
+
+ vdesc = vchan_next_desc(&tdc->vc);
+ if (!vdesc)
+ return;
+
+ tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
+ if (!tdc->dma_desc)
+ return;
+
+ list_del(&vdesc->node);
+
+ tdc->dma_desc->tdc = tdc;
+ ch_regs = &tdc->dma_desc->ch_regs;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+
+ /* Start DMA */
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+
+ tdc->busy = true;
+}
+
+static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ switch (tdc->sid_dir) {
+ case DMA_MEM_TO_DEV:
+ clear_bit(sid, &tdma->sid_m2d_reserved);
+ break;
+ case DMA_DEV_TO_MEM:
+ clear_bit(sid, &tdma->sid_d2m_reserved);
+ break;
+ case DMA_MEM_TO_MEM:
+ clear_bit(sid, &tdma->sid_m2m_reserved);
+ break;
+ }
+
+ tdc->sid_reserved = false;
+ tdc->sid_dir = DMA_TRANS_NONE;
+}
+
+static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
+{
+ tegra_dma_sid_free(tdc);
+ kfree(tdc->dma_desc);
+}
+
+static void tegra_dma_isr_callback(struct tegra_dma_channel *tdc,
+ bool to_terminate)
+{
+ struct tegra_dma_desc *dma_desc;
+
+ tdc->busy = false;
+ dma_desc = tdc->dma_desc;
+ dma_desc->bytes_transferred += dma_desc->bytes_requested;
+
+ vchan_cookie_complete(&tdc->dma_desc->vd);
+
+ if (to_terminate)
+ return;
+
+ tegra_dma_start(tdc);
+}
+
+static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
+ unsigned int err_status)
+{
+ switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
+ case TEGRA_DMA_BM_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d bm fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d peripheral fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal peripheral id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_STREAM_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal stream id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MC_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mc slave error\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MMIO_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mmio slave error\n", tdc->id);
+ break;
+
+ default:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d security violation %x\n", tdc->id,
+ err_status);
+ }
+}
+
+static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ unsigned int err_status;
+ unsigned long status;
+
+ raw_spin_lock(&tdc->lock);
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ err_status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+
+ if (err_status) {
+ tegra_dma_chan_decode_error(tdc, err_status);
+ tegra_dma_dump_chan_regs(tdc);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ }
+
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ TEGRA_GPCDMA_STATUS_ISE_EOC);
+ tegra_dma_isr_callback(tdc, false);
+
+ ret = IRQ_HANDLED;
+ }
+
+ raw_spin_unlock(&tdc->lock);
+ return ret;
+}
+
+static void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->busy)
+ if (vchan_issue_pending(&tdc->vc))
+ tegra_dma_start(tdc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
+{
+ u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
+ csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+}
+
+static void tegra_dma_stop_client(struct tegra_dma_channel *tdc)
+{
+ int ret;
+ unsigned long status;
+
+ /* Before Reading DMA status to figure out number
+ * of bytes transferred by DMA channel:
+ * Change the client associated with the DMA channel
+ * to stop DMA engine from starting any more bursts for
+ * the given client and wait for in flight bursts to complete
+ */
+ tegra_dma_reset_client(tdc);
+
+ /* Wait for in flight data transfer to finish */
+ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
+
+ /* If TX/RX path is still active wait till it becomes
+ * inactive
+ */
+
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset +
+ TEGRA_GPCDMA_CHAN_STATUS,
+ status,
+ !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
+ TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
+ 5,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+ if (ret) {
+ dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
+ tegra_dma_dump_chan_regs(tdc);
+ }
+}
+
+static int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long wcount = 0;
+ unsigned long status;
+ unsigned long flags;
+ bool was_busy;
+ int err;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->dma_desc) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ if (tdc->tdma->chip_data->hw_support_pause) {
+ err = tegra_dma_pause(tdc);
+ if (err) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return err;
+ }
+ } else {
+ tegra_dma_stop_client(tdc);
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tegra_dma_isr_callback(tdc, true);
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ }
+
+ was_busy = tdc->busy;
+
+ tegra_dma_stop(tdc);
+ if (tdc->dma_desc && was_busy)
+ tdc->dma_desc->bytes_transferred +=
+ tdc->dma_desc->bytes_requested - (wcount * 4);
+
+skip_dma_stop:
+ tegra_dma_abort_all(tdc);
+ vchan_free_chan_resources(&tdc->vc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc = NULL;
+ struct virt_dma_desc *vd;
+ unsigned int residual;
+ enum dma_status ret;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+
+ vd = vchan_find_desc(&tdc->vc, cookie);
+ if (vd)
+ dma_desc = vd_to_tegra_dma_desc(vd);
+
+ if (dma_desc) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ kfree(dma_desc);
+ } else {
+ dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+static inline int get_bus_width(struct tegra_dma_channel *tdc,
+ enum dma_slave_buswidth slave_bw)
+{
+ switch (slave_bw) {
+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ default:
+ dev_err(tdc2dev(tdc), "given slave bw is not supported\n");
+ return -EINVAL;
+ }
+}
+
+static inline int get_burst_size_by_len(int len)
+{
+ int ret;
+
+ switch (len) {
+ case BIT(0) ... BIT(2):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ break;
+ case BIT(3):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ break;
+ case BIT(4):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ break;
+ case BIT(5):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ break;
+ default:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ break;
+ }
+
+ return ret;
+}
+
+static inline int get_burst_size(struct tegra_dma_channel *tdc,
+ u32 burst_size,
+ enum dma_slave_buswidth slave_bw,
+ int len)
+{
+ int burst_mmio_width, burst_byte, ret;
+
+ /*
+ * burst_size from client is in terms of the bus_width.
+ * convert that into words.
+ */
+ burst_byte = burst_size * slave_bw;
+ burst_mmio_width = burst_byte / 4;
+
+ switch (burst_mmio_width) {
+ case 0:
+ ret = get_burst_size_by_len(len);
+ break;
+ case 1:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ break;
+ case 2 ... 3:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ break;
+ case 4 ... 7:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ break;
+ case 8 ... 15:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ break;
+ default:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ break;
+ }
+
+ return ret;
+}
+
+static int tegra_dma_reserve_sid(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ if (tdc->sid_reserved)
+ return tdc->sid_dir == direction ? 0 : -EINVAL;
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ case DMA_DEV_TO_MEM:
+ if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ case DMA_MEM_TO_MEM:
+ if (test_and_set_bit(sid, &tdma->sid_m2m_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ }
+
+ tdc->sid_reserved = true;
+ tdc->sid_dir = direction;
+
+ return 0;
+}
+
+static int get_transfer_param(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction,
+ unsigned long *apb_addr,
+ unsigned long *mmio_seq,
+ unsigned long *csr,
+ unsigned int *burst_size,
+ enum dma_slave_buswidth *slave_bw)
+{
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ *apb_addr = tdc->dma_sconfig.dst_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
+ *burst_size = tdc->dma_sconfig.dst_maxburst;
+ *slave_bw = tdc->dma_sconfig.dst_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
+ return 0;
+ case DMA_DEV_TO_MEM:
+ *apb_addr = tdc->dma_sconfig.src_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
+ *burst_size = tdc->dma_sconfig.src_maxburst;
+ *slave_bw = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
+ return 0;
+ case DMA_MEM_TO_MEM:
+ *burst_size = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ return 0;
+ default:
+ dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
+ return -EINVAL;
+ }
+ return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
+ size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ /* Set dma mode to fixed pattern */
+ csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ dma_desc->ch_regs.src_ptr = 0;
+ dma_desc->ch_regs.dst_ptr = dest;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ dma_desc->ch_regs.fixed_pattern = value;
+ /* Word count reg takes value as (N +1) words */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = 0;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+
+ tdc->dma_desc = dma_desc;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
+ dma_addr_t src, size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ /* Set dma mode to memory to memory transfer */
+ csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
+ (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (src & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ dma_desc->ch_regs.src_ptr = src;
+ dma_desc->ch_regs.dst_ptr = dest;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
+ dma_desc->ch_regs.high_addr_ptr |=
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ /* Word count reg takes value as (N +1) words */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = 0;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_desc *dma_desc;
+ struct scatterlist *sg;
+ u32 burst_size;
+ unsigned int i;
+ int ret;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "dma channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ ret = tegra_dma_reserve_sid(tdc, direction);
+ if (ret)
+ return NULL;
+
+ ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
+ &burst_size, &slave_bw);
+ if (ret < 0)
+ return NULL;
+
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Program the slave id in requestor select */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Configure default priority weight for the channel*/
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping on both MC and MMIO side */
+
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
+
+ /* Program 2 MC outstanding requests by default. */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+
+ /* Setting MC burst size depending on MMIO burst size */
+ if (burst_size == 64)
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+ else
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len;
+ dma_addr_t mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
+ dma_desc->bytes_requested += len;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ dma_desc->ch_regs.src_ptr = mem;
+ dma_desc->ch_regs.dst_ptr = apb_ptr;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
+ } else if (direction == DMA_DEV_TO_MEM) {
+ dma_desc->ch_regs.src_ptr = apb_ptr;
+ dma_desc->ch_regs.dst_ptr = mem;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
+ }
+
+ /*
+ * Word count register takes input in words. Writing a value
+ * of N into word count register means a req of (N+1) words.
+ */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = mmio_seq;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+ tdc->dma_desc = dma_desc;
+ }
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ dma_cookie_init(&tdc->vc.chan);
+ tdc->config_init = false;
+ return 0;
+}
+
+static void tegra_dma_chan_synchronize(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ vchan_synchronize(&tdc->vc);
+}
+
+static void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ if (tdc->busy)
+ tegra_dma_terminate_all(dc);
+
+ tegra_dma_chan_synchronize(dc);
+
+ tasklet_kill(&tdc->vc.task);
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ tdc->config_init = false;
+ tdc->slave_id = -1;
+ tdc->sid_reserved = false;
+ tdc->sid_dir = DMA_TRANS_NONE;
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct tegra_dma_channel *tdc;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ tdc = to_tegra_dma_chan(chan);
+ tdc->slave_id = dma_spec->args[0];
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = false,
+};
+
+static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+};
+
+static const struct of_device_id tegra_dma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra186-gpcdma",
+ .data = &tegra186_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra194-gpcdma",
+ .data = &tegra194_dma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+
+static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
+ int chan, int stream_id)
+{
+ unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ return 0;
+}
+
+static int tegra_dma_probe(struct platform_device *pdev)
+{
+ const struct tegra_dma_chip_data *cdata = NULL;
+ unsigned int stream_id, i;
+ struct tegra_dma *tdma;
+ struct resource *res;
+ int ret;
+
+ cdata = of_device_get_match_data(&pdev->dev);
+
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "nvidia,stream-id", &stream_id);
+ if (ret)
+ stream_id = TEGRA186_SID_GPCDMA_0;
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ if (IS_ERR(tdma->rst)) {
+ dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
+ "Missing controller reset\n");
+ return PTR_ERR(tdma->rst);
+ }
+ reset_control_reset(tdma->rst);
+
+ tdma->dma_dev.dev = &pdev->dev;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
+ i * cdata->channel_reg_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ if (!res) {
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ return -EINVAL;
+ }
+ tdc->irq = res->start;
+ snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+
+ tdc->tdma = tdma;
+ tdc->id = i;
+ tdc->slave_id = -1;
+
+ vchan_init(&tdc->vc, &tdma->dma_dev);
+ tdc->vc.desc_free = tegra_dma_desc_free;
+ raw_spin_lock_init(&tdc->lock);
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, i, stream_id);
+ tdc->stream_id = stream_id;
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
+
+ /*
+ * Only word aligned transfers are supported. Set the copy
+ * alignment shift.
+ */
+ tdma->dma_dev.copy_align = 2;
+ tdma->dma_dev.fill_align = 2;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
+ tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
+ tdma->dma_dev.device_config = tegra_dma_slave_config;
+ tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ /* Register DMA channel interrupt handlers after everything is setup */
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret,
+ "request_irq failed for channel %d\n", i);
+ return ret;
+ }
+ }
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA driver registration failed\n");
+ return ret;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA OF registration failed\n");
+
+ dma_async_device_unregister(&tdma->dma_dev);
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
+ cdata->nr_channels);
+
+ return 0;
+}
+
+static int tegra_dma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ return 0;
+}
+
+/*
+ * Save and restore csr and channel register on pm_suspend
+ * and pm_resume respectively
+ */
+static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned long flags;
+ unsigned int i;
+ bool busy;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ busy = tdc->busy;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+
+ if (busy) {
+ dev_err(tdma->dev, "channel %u busy\n", i);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned int i;
+
+ reset_control_reset(tdma->rst);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tegra_dma_program_sid(tdc, i, tdc->stream_id);
+ }
+
+ return 0;
+}
+
+static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
+};
+
+static struct platform_driver tegra_dmac_driver = {
+ .driver = {
+ .name = "tegra-gpcdma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_dma_dev_pm_ops,
+ .of_match_table = tegra_dma_of_match,
+ },
+ .probe = tegra_dma_probe,
+ .remove = tegra_dma_remove,
+};
+
+module_platform_driver(tegra_dmac_driver);
+
+MODULE_ALIAS("platform:tegra-gpc-dma");
+MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
+MODULE_AUTHOR("Pavan Kunapuli <[email protected]>");
+MODULE_AUTHOR("Rajesh Gumasta <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
dma controller driver
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f423d08..54770c8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -930,6 +930,7 @@ CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
+CONFIG_TEGRA186_GPC_DMA=m
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
--
2.7.4
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 ++++++++++++++++++++++++++
3 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index fcd71bf..71dd10e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -56,6 +56,10 @@
};
};
+ dma@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index d02f6bf..f68291c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -73,6 +73,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ nvidia,start-dma-channel-index = <1>;
+ dma-channels = <31>;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index b7d5328..bc85c91 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -72,6 +72,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
--
2.7.4
On 08/09/2021 15:32, Akhil R wrote:
> Add support for Nvida Tegra general purpose DMA driver for
> Tegra186 and Tegra194 platform.
>
> Changes in patch v4:
> Addressed review comments in patch v3
Would be good to be specific, because not all the comments from V3 have
been addressed :-)
Jon
--
nvpublic
On 08/09/2021 15:32, Akhil R wrote:
> Add device tree node for GPCDMA controller on Tegra186 target
> and Tegra194 target.
>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 ++++++++++++++++++++++++++
> 3 files changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index fcd71bf..71dd10e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -56,6 +56,10 @@
> };
> };
>
> + dma@2600000 {
> + status = "okay";
> + };
> +
> memory-controller@2c00000 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index d02f6bf..f68291c 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -73,6 +73,52 @@
> snps,rxpbl = <8>;
> };
>
> + gpcdma: dma@2600000 {
> + compatible = "nvidia,tegra186-gpcdma";
> + reg = <0x2600000 0x210000>;
> + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> + dma-coherent;
> + nvidia,start-dma-channel-index = <1>;
> + dma-channels = <31>;
> + status = "disabled";
Looks like the comments from the previous version are not addressed in
this version.
Jon
--
nvpublic
>> Add support for Nvida Tegra general purpose DMA driver for
>> Tegra186 and Tegra194 platform.
>>
>> Changes in patch v4:
>> Addressed review comments in patch v3
>
> Would be good to be specific, because not all the comments from V3 have been addressed :-)
>
> Jon
Hi Jon,
I am sorry that I totally missed the comments from PATCH v3 4/4 and thought I addressed all the comments. Would correct those as well and send out a new version.
Thanks,
Akhil
--
nvpublic
Add support for Nvida Tegra general purpose DMA driver for
Tegra186 and Tegra194 platform.
Changes in patch v5:
* Corrections/indentation in nvidia,tegra186-gpc-dma.yaml
* Enabled gpcdma in dts for tegra194
v4 - https://lkml.org/lkml/2021/9/8/513
v3 - https://lkml.org/lkml/2021/8/27/34
v2 - https://lkml.org/lkml/2020/8/6/90
v1 - https://lkml.org/lkml/2020/7/20/96
Akhil R (4):
dt-bindings: dmaengine: Add doc for tegra gpcdma
dmaengine: tegra: Add tegra gpcdma driver
arm64: defconfig: tegra: Enable GPCDMA
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 107 ++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 +
arch/arm64/configs/defconfig | 1 +
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1371 ++++++++++++++++++++
9 files changed, 1588 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
create mode 100644 drivers/dma/tegra186-gpc-dma.c
--
2.7.4
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
supports dma transfers between memory to memory, IO peripheral to memory
and memory to IO peripheral.
Signed-off-by: Pavan Kunapuli <[email protected]>
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1371 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 1384 insertions(+)
create mode 100644 drivers/dma/tegra186-gpc-dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 39b5b46..7d7f69f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -632,6 +632,18 @@ config TEGRA210_ADMA
peripheral and vice versa. It does not support memory to
memory data transfer.
+config TEGRA186_GPC_DMA
+ tristate "NVIDIA Tegra GPC DMA support"
+ depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
+ driver. The DMA controller has multiple DMA channels which can
+ be configured for different peripherals like UART, SPI, etc
+ which are on APB bus.
+ This DMA controller transfers data from memory to peripheral FIFO
+ or vice versa. It also supports memory to memory data transfer.
+
config TIMB_DMA
tristate "Timberdale FPGA DMA support"
depends on MFD_TIMBERDALE || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index aa69094..d3941ec 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
+obj-$(CONFIG_TEGRA186_GPC_DMA) += tegra186-gpc-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
new file mode 100644
index 0000000..dcdec7b
--- /dev/null
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -0,0 +1,1371 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller.
+ *
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <dt-bindings/memory/tegra186-mc.h>
+#include "virt-dma.h"
+
+/* CSR register */
+#define TEGRA_GPCDMA_CHAN_CSR 0x00
+#define TEGRA_GPCDMA_CSR_ENB BIT(31)
+#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
+#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
+
+#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
+#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
+#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
+#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
+
+#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
+#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
+
+#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
+#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
+#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
+
+/* STATUS register */
+#define TEGRA_GPCDMA_CHAN_STATUS 0x004
+#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
+#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
+#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
+#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
+#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
+#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
+#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
+
+#define TEGRA_GPCDMA_CHAN_CSRE 0x008
+#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
+
+/* Source address */
+#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
+
+/* Destination address */
+#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
+
+/* High address pointer */
+#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
+#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
+
+/* MC sequence register */
+#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
+#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
+#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
+#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
+#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
+#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
+#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
+
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
+
+/* MMIO sequence register */
+#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
+#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
+#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST GENMASK(26, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_1 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_4 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 7)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BURST, 15)
+#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
+#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
+#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
+
+/* Channel WCOUNT */
+#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
+
+/* Transfer count */
+#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
+
+/* DMA byte count status */
+#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
+
+/* Error Status Register */
+#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT (8)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK (0xF)
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
+ ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
+ TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
+#define TEGRA_DMA_BM_FIFO_FULL_ERR (0xF)
+#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR (0xE)
+#define TEGRA_DMA_PERIPH_ID_ERR (0xD)
+#define TEGRA_DMA_STREAM_ID_ERR (0xC)
+#define TEGRA_DMA_MC_SLAVE_ERR (0xB)
+#define TEGRA_DMA_MMIO_SLAVE_ERR (0xA)
+
+/* Fixed Pattern */
+#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
+
+#define TEGRA_GPCDMA_CHAN_TZ 0x38
+#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
+#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
+
+#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
+#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
+
+/*
+ * If any burst is in flight and DMA paused then this is the time to complete
+ * on-flight burst and update DMA status register.
+ */
+#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
+#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
+
+/* Channel base address offset from GPCDMA base address */
+#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
+
+struct tegra_dma;
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @hw_support_pause: DMA HW engine support pause of the channel.
+ */
+struct tegra_dma_chip_data {
+ int nr_channels;
+ int channel_reg_size;
+ int max_dma_count;
+ bool hw_support_pause;
+};
+
+/* DMA channel registers */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long src_ptr;
+ unsigned long dst_ptr;
+ unsigned long high_addr_ptr;
+ unsigned long mc_seq;
+ unsigned long mmio_seq;
+ unsigned long wcount;
+ unsigned long fixed_pattern;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
+ * manage client request and keep track of transfer status, callbacks
+ * and request counts etc.
+ */
+struct tegra_dma_desc {
+ struct virt_dma_desc vd;
+ int bytes_requested;
+ int bytes_transferred;
+ struct tegra_dma_channel *tdc;
+ struct tegra_dma_channel_regs ch_regs;
+};
+
+struct tegra_dma_channel;
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct virt_dma_chan vc;
+ struct tegra_dma_desc *dma_desc;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ unsigned int stream_id;
+ unsigned long chan_base_offset;
+ raw_spinlock_t lock;
+ bool busy;
+ struct tegra_dma *tdma;
+ int slave_id;
+ bool sid_reserved;
+ enum dma_transfer_direction sid_dir;
+ struct dma_slave_config dma_sconfig;
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ struct reset_control *rst;
+ unsigned long sid_m2d_reserved;
+ unsigned long sid_d2m_reserved;
+ unsigned long sid_m2m_reserved;
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, vc.chan);
+}
+
+static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct tegra_dma_desc, vd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return tdc->vc.chan.device->dev;
+}
+
+static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
+{
+ dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
+ tdc->id, tdc->name);
+ dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
+ );
+ dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
+ );
+ dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+}
+
+static void tegra_dma_desc_free(struct virt_dma_desc *vd)
+{
+ kfree(container_of(vd, struct tegra_dma_desc, vd));
+}
+
+static int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ if (tdc->dma_desc) {
+ dev_err(tdc2dev(tdc), "Configuration not allowed\n");
+ return -EBUSY;
+ }
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ if (tdc->slave_id == -1)
+ tdc->slave_id = sconfig->slave_id;
+
+ tdc->config_init = true;
+ return 0;
+}
+
+static int tegra_dma_pause(struct tegra_dma_channel *tdc)
+{
+ u32 val;
+ int ret;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
+
+ /* Wait until busy bit is de-asserted */
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ val,
+ !(val & TEGRA_GPCDMA_STATUS_BUSY),
+ TEGRA_GPCDMA_BURST_COMPLETE_TIME,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+
+ if (ret)
+ dev_err(tdc2dev(tdc), "DMA pause timed out\n");
+
+ return ret;
+}
+
+static void tegra_dma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 csr, status;
+
+ csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ /* Disable interrupts */
+ csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
+
+ /* Disable DMA */
+ csr &= ~TEGRA_GPCDMA_CSR_ENB;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+
+ /* Clear interrupt status if it is there */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ }
+ tdc->busy = false;
+}
+
+static void tegra_dma_start(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_channel_regs *ch_regs;
+ struct virt_dma_desc *vdesc;
+
+ if (tdc->busy)
+ return;
+
+ vdesc = vchan_next_desc(&tdc->vc);
+ if (!vdesc)
+ return;
+
+ tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
+ if (!tdc->dma_desc)
+ return;
+
+ list_del(&vdesc->node);
+
+ tdc->dma_desc->tdc = tdc;
+ ch_regs = &tdc->dma_desc->ch_regs;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+
+ /* Start DMA */
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+
+ tdc->busy = true;
+}
+
+static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ switch (tdc->sid_dir) {
+ case DMA_MEM_TO_DEV:
+ clear_bit(sid, &tdma->sid_m2d_reserved);
+ break;
+ case DMA_DEV_TO_MEM:
+ clear_bit(sid, &tdma->sid_d2m_reserved);
+ break;
+ case DMA_MEM_TO_MEM:
+ clear_bit(sid, &tdma->sid_m2m_reserved);
+ break;
+ }
+
+ tdc->sid_reserved = false;
+ tdc->sid_dir = DMA_TRANS_NONE;
+}
+
+static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
+{
+ tegra_dma_sid_free(tdc);
+ kfree(tdc->dma_desc);
+}
+
+static void tegra_dma_isr_callback(struct tegra_dma_channel *tdc,
+ bool to_terminate)
+{
+ struct tegra_dma_desc *dma_desc;
+
+ tdc->busy = false;
+ dma_desc = tdc->dma_desc;
+ dma_desc->bytes_transferred += dma_desc->bytes_requested;
+
+ vchan_cookie_complete(&tdc->dma_desc->vd);
+
+ if (to_terminate)
+ return;
+
+ tegra_dma_start(tdc);
+}
+
+static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
+ unsigned int err_status)
+{
+ switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
+ case TEGRA_DMA_BM_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d bm fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d peripheral fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal peripheral id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_STREAM_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal stream id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MC_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mc slave error\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MMIO_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mmio slave error\n", tdc->id);
+ break;
+
+ default:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d security violation %x\n", tdc->id,
+ err_status);
+ }
+}
+
+static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ unsigned int err_status;
+ unsigned long status;
+
+ raw_spin_lock(&tdc->lock);
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ err_status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+
+ if (err_status) {
+ tegra_dma_chan_decode_error(tdc, err_status);
+ tegra_dma_dump_chan_regs(tdc);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ }
+
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ TEGRA_GPCDMA_STATUS_ISE_EOC);
+ tegra_dma_isr_callback(tdc, false);
+
+ ret = IRQ_HANDLED;
+ }
+
+ raw_spin_unlock(&tdc->lock);
+ return ret;
+}
+
+static void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->busy)
+ if (vchan_issue_pending(&tdc->vc))
+ tegra_dma_start(tdc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
+{
+ u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
+ csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+}
+
+static void tegra_dma_stop_client(struct tegra_dma_channel *tdc)
+{
+ int ret;
+ unsigned long status;
+
+ /* Before Reading DMA status to figure out number
+ * of bytes transferred by DMA channel:
+ * Change the client associated with the DMA channel
+ * to stop DMA engine from starting any more bursts for
+ * the given client and wait for in flight bursts to complete
+ */
+ tegra_dma_reset_client(tdc);
+
+ /* Wait for in flight data transfer to finish */
+ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
+
+ /* If TX/RX path is still active wait till it becomes
+ * inactive
+ */
+
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset +
+ TEGRA_GPCDMA_CHAN_STATUS,
+ status,
+ !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
+ TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
+ 5,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+ if (ret) {
+ dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
+ tegra_dma_dump_chan_regs(tdc);
+ }
+}
+
+static int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long wcount = 0;
+ unsigned long status;
+ unsigned long flags;
+ bool was_busy;
+ int err;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->dma_desc) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ if (tdc->tdma->chip_data->hw_support_pause) {
+ err = tegra_dma_pause(tdc);
+ if (err) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return err;
+ }
+ } else {
+ tegra_dma_stop_client(tdc);
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tegra_dma_isr_callback(tdc, true);
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ }
+
+ was_busy = tdc->busy;
+
+ tegra_dma_stop(tdc);
+ if (tdc->dma_desc && was_busy)
+ tdc->dma_desc->bytes_transferred +=
+ tdc->dma_desc->bytes_requested - (wcount * 4);
+
+skip_dma_stop:
+ tegra_dma_abort_all(tdc);
+ vchan_free_chan_resources(&tdc->vc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc = NULL;
+ struct virt_dma_desc *vd;
+ unsigned int residual;
+ enum dma_status ret;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+
+ vd = vchan_find_desc(&tdc->vc, cookie);
+ if (vd)
+ dma_desc = vd_to_tegra_dma_desc(vd);
+
+ if (dma_desc) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ kfree(dma_desc);
+ } else {
+ dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+static inline int get_bus_width(struct tegra_dma_channel *tdc,
+ enum dma_slave_buswidth slave_bw)
+{
+ switch (slave_bw) {
+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ default:
+ dev_err(tdc2dev(tdc), "given slave bw is not supported\n");
+ return -EINVAL;
+ }
+}
+
+static inline int get_burst_size_by_len(int len)
+{
+ int ret;
+
+ switch (len) {
+ case BIT(0) ... BIT(2):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ break;
+ case BIT(3):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ break;
+ case BIT(4):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ break;
+ case BIT(5):
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ break;
+ default:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ break;
+ }
+
+ return ret;
+}
+
+static inline int get_burst_size(struct tegra_dma_channel *tdc,
+ u32 burst_size,
+ enum dma_slave_buswidth slave_bw,
+ int len)
+{
+ int burst_mmio_width, burst_byte, ret;
+
+ /*
+ * burst_size from client is in terms of the bus_width.
+ * convert that into words.
+ */
+ burst_byte = burst_size * slave_bw;
+ burst_mmio_width = burst_byte / 4;
+
+ switch (burst_mmio_width) {
+ case 0:
+ ret = get_burst_size_by_len(len);
+ break;
+ case 1:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
+ break;
+ case 2 ... 3:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
+ break;
+ case 4 ... 7:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
+ break;
+ case 8 ... 15:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
+ break;
+ default:
+ ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
+ break;
+ }
+
+ return ret;
+}
+
+static int tegra_dma_reserve_sid(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ if (tdc->sid_reserved)
+ return tdc->sid_dir == direction ? 0 : -EINVAL;
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ case DMA_DEV_TO_MEM:
+ if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ case DMA_MEM_TO_MEM:
+ if (test_and_set_bit(sid, &tdma->sid_m2m_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ }
+
+ tdc->sid_reserved = true;
+ tdc->sid_dir = direction;
+
+ return 0;
+}
+
+static int get_transfer_param(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction,
+ unsigned long *apb_addr,
+ unsigned long *mmio_seq,
+ unsigned long *csr,
+ unsigned int *burst_size,
+ enum dma_slave_buswidth *slave_bw)
+{
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ *apb_addr = tdc->dma_sconfig.dst_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
+ *burst_size = tdc->dma_sconfig.dst_maxburst;
+ *slave_bw = tdc->dma_sconfig.dst_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
+ return 0;
+ case DMA_DEV_TO_MEM:
+ *apb_addr = tdc->dma_sconfig.src_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
+ *burst_size = tdc->dma_sconfig.src_maxburst;
+ *slave_bw = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
+ return 0;
+ case DMA_MEM_TO_MEM:
+ *burst_size = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ return 0;
+ default:
+ dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
+ return -EINVAL;
+ }
+ return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
+ size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ /* Set dma mode to fixed pattern */
+ csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ dma_desc->ch_regs.src_ptr = 0;
+ dma_desc->ch_regs.dst_ptr = dest;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ dma_desc->ch_regs.fixed_pattern = value;
+ /* Word count reg takes value as (N +1) words */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = 0;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+
+ tdc->dma_desc = dma_desc;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
+ dma_addr_t src, size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ /* Set dma mode to memory to memory transfer */
+ csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
+ (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ if ((len & 3) || (src & 3) || (dest & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+ dma_desc->ch_regs.src_ptr = src;
+ dma_desc->ch_regs.dst_ptr = dest;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
+ dma_desc->ch_regs.high_addr_ptr |=
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ /* Word count reg takes value as (N +1) words */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = 0;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_desc *dma_desc;
+ struct scatterlist *sg;
+ u32 burst_size;
+ unsigned int i;
+ int ret;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "dma channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ ret = tegra_dma_reserve_sid(tdc, direction);
+ if (ret)
+ return NULL;
+
+ ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
+ &burst_size, &slave_bw);
+ if (ret < 0)
+ return NULL;
+
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Program the slave id in requestor select */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Configure default priority weight for the channel*/
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping on both MC and MMIO side */
+
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
+
+ /* Program 2 MC outstanding requests by default. */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+
+ /* Setting MC burst size depending on MMIO burst size */
+ if (burst_size == 64)
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+ else
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len;
+ dma_addr_t mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
+ dma_desc->bytes_requested += len;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ dma_desc->ch_regs.src_ptr = mem;
+ dma_desc->ch_regs.dst_ptr = apb_ptr;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
+ } else if (direction == DMA_DEV_TO_MEM) {
+ dma_desc->ch_regs.src_ptr = apb_ptr;
+ dma_desc->ch_regs.dst_ptr = mem;
+ dma_desc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
+ }
+
+ /*
+ * Word count register takes input in words. Writing a value
+ * of N into word count register means a req of (N+1) words.
+ */
+ dma_desc->ch_regs.wcount = ((len - 4) >> 2);
+ dma_desc->ch_regs.csr = csr;
+ dma_desc->ch_regs.mmio_seq = mmio_seq;
+ dma_desc->ch_regs.mc_seq = mc_seq;
+ tdc->dma_desc = dma_desc;
+ }
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ dma_cookie_init(&tdc->vc.chan);
+ tdc->config_init = false;
+ return 0;
+}
+
+static void tegra_dma_chan_synchronize(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ vchan_synchronize(&tdc->vc);
+}
+
+static void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ if (tdc->busy)
+ tegra_dma_terminate_all(dc);
+
+ tegra_dma_chan_synchronize(dc);
+
+ tasklet_kill(&tdc->vc.task);
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ tdc->config_init = false;
+ tdc->slave_id = -1;
+ tdc->sid_reserved = false;
+ tdc->sid_dir = DMA_TRANS_NONE;
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct tegra_dma_channel *tdc;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ tdc = to_tegra_dma_chan(chan);
+ tdc->slave_id = dma_spec->args[0];
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
+ .nr_channels = 31,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = false,
+};
+
+static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
+ .nr_channels = 31,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+};
+
+static const struct of_device_id tegra_dma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra186-gpcdma",
+ .data = &tegra186_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra194-gpcdma",
+ .data = &tegra194_dma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+
+static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
+ int chan, int stream_id)
+{
+ unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ return 0;
+}
+
+static int tegra_dma_probe(struct platform_device *pdev)
+{
+ const struct tegra_dma_chip_data *cdata = NULL;
+ unsigned int stream_id, i;
+ struct tegra_dma *tdma;
+ struct resource *res;
+ int ret;
+
+ cdata = of_device_get_match_data(&pdev->dev);
+
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "nvidia,stream-id", &stream_id);
+ if (ret)
+ stream_id = TEGRA186_SID_GPCDMA_0;
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ if (IS_ERR(tdma->rst)) {
+ dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
+ "Missing controller reset\n");
+ return PTR_ERR(tdma->rst);
+ }
+ reset_control_reset(tdma->rst);
+
+ tdma->dma_dev.dev = &pdev->dev;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
+ i * cdata->channel_reg_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ if (!res) {
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ return -EINVAL;
+ }
+ tdc->irq = res->start;
+ snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+
+ tdc->tdma = tdma;
+ tdc->id = i;
+ tdc->slave_id = -1;
+
+ vchan_init(&tdc->vc, &tdma->dma_dev);
+ tdc->vc.desc_free = tegra_dma_desc_free;
+ raw_spin_lock_init(&tdc->lock);
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, i, stream_id);
+ tdc->stream_id = stream_id;
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
+
+ /*
+ * Only word aligned transfers are supported. Set the copy
+ * alignment shift.
+ */
+ tdma->dma_dev.copy_align = 2;
+ tdma->dma_dev.fill_align = 2;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
+ tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
+ tdma->dma_dev.device_config = tegra_dma_slave_config;
+ tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ /* Register DMA channel interrupt handlers after everything is setup */
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret,
+ "request_irq failed for channel %d\n", i);
+ return ret;
+ }
+ }
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA driver registration failed\n");
+ return ret;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA OF registration failed\n");
+
+ dma_async_device_unregister(&tdma->dma_dev);
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
+ cdata->nr_channels);
+
+ return 0;
+}
+
+static int tegra_dma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ return 0;
+}
+
+/*
+ * Save and restore csr and channel register on pm_suspend
+ * and pm_resume respectively
+ */
+static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned long flags;
+ unsigned int i;
+ bool busy;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ busy = tdc->busy;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+
+ if (busy) {
+ dev_err(tdma->dev, "channel %u busy\n", i);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned int i;
+
+ reset_control_reset(tdma->rst);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tegra_dma_program_sid(tdc, i, tdc->stream_id);
+ }
+
+ return 0;
+}
+
+static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
+};
+
+static struct platform_driver tegra_dmac_driver = {
+ .driver = {
+ .name = "tegra-gpcdma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_dma_dev_pm_ops,
+ .of_match_table = tegra_dma_of_match,
+ },
+ .probe = tegra_dma_probe,
+ .remove = tegra_dma_remove,
+};
+
+module_platform_driver(tegra_dmac_driver);
+
+MODULE_ALIAS("platform:tegra-gpc-dma");
+MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
+MODULE_AUTHOR("Pavan Kunapuli <[email protected]>");
+MODULE_AUTHOR("Rajesh Gumasta <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
dma controller driver
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f423d08..54770c8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -930,6 +930,7 @@ CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
+CONFIG_TEGRA186_GPC_DMA=m
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
--
2.7.4
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <[email protected]>
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++++
4 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index fcd71bf..71dd10e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -56,6 +56,10 @@
};
};
+ dma@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index d02f6bf..efa6945 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -73,6 +73,50 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 7e7b0eb..2d4ead1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -49,6 +49,10 @@
};
};
+ dma@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index b7d5328..e100606 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -72,6 +72,50 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@2600000 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
--
2.7.4
On 16/09/2021 13:18, Akhil R wrote:
> Add device tree node for GPCDMA controller on Tegra186 target
> and Tegra194 target.
>
> Signed-off-by: Rajesh Gumasta <[email protected]>
> Signed-off-by: Akhil R <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++++
> 4 files changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index fcd71bf..71dd10e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -56,6 +56,10 @@
> };
> };
>
> + dma@2600000 {
> + status = "okay";
> + };
> +
> memory-controller@2c00000 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index d02f6bf..efa6945 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -73,6 +73,50 @@
> snps,rxpbl = <8>;
> };
>
> + gpcdma: dma@2600000 {
> + compatible = "nvidia,tegra186-gpcdma";
> + reg = <0x2600000 0x210000>;
> + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
This is not typically how we fix the indentation. You just need to align
the subsequent lines with the first line in the property using spaces.
Jon
--
nvpublic