This changeset applies on top of the previous updates series
available here [0].
Most of the changes proposed here are related to the plls of meson
SoCs. Details can be found in each patches but, in nutshell, there
is :
* a bit of clean-up,
* improved pll capabilities using the frac parameter,
* several clocks added to model the tree more accurately.
Beware: patch #10 depends on this core clock framework fix: [1]
As explained in the description on the patch, if the gates are
added w/o this fix, the system will crash when
clk_disable_unused() is called.
[0]: https://lkml.kernel.org/r/[email protected]
[1]: https://lkml.kernel.org/r/[email protected]
Jerome Brunet (11):
clk: meson: add fractional part of meson8b fixed_pll
clk: meson: poke pll CNTL last
clk: meson: remove special gp0 lock loop
clk: meson: improve pll driver results with frac
clk: meson: add gp0 frac parameter for axg and gxl
clk: meson: add ROUND_CLOSEST to the pll driver
clk: meson: axg: add hifi clock bindings
clk: meson: axg: add hifi pll clock
clk: meson: add mpll pre-divider
clk: meson: add fdiv clock gates
clk: meson: clean-up clk81 clocks
drivers/clk/meson/axg.c | 184 +++++++++++++++++++++++++++++++----
drivers/clk/meson/axg.h | 8 +-
drivers/clk/meson/clk-pll.c | 154 ++++++++++++++++++-----------
drivers/clk/meson/clkc.h | 15 +--
drivers/clk/meson/gxbb.c | 141 +++++++++++++++++++++++----
drivers/clk/meson/gxbb.h | 10 +-
drivers/clk/meson/meson8b.c | 128 ++++++++++++++++++++----
drivers/clk/meson/meson8b.h | 8 +-
include/dt-bindings/clock/axg-clkc.h | 1 +
9 files changed, 521 insertions(+), 128 deletions(-)
--
2.14.3
Add the new HIFI pll to axg clock bindings
Signed-off-by: Jerome Brunet <[email protected]>
---
include/dt-bindings/clock/axg-clkc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 941ac70e7f30..555937a25504 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -67,5 +67,6 @@
#define CLKID_AO_I2C 58
#define CLKID_SD_EMMC_B_CLK0 59
#define CLKID_SD_EMMC_C_CLK0 60
+#define CLKID_HIFI_PLL 69
#endif /* __AXG_CLKC_H */
--
2.14.3
Fdiv fixed dividers clocks of the fixed_pll can actually gate
independently. We never had an issue so far because these clocks
were provided 'enabled' by the bootloader.
Add these gates to enable/disable the clocks when required.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/axg.c | 95 ++++++++++++++++++++++++++++++++++++-----
drivers/clk/meson/axg.h | 7 +++-
drivers/clk/meson/gxbb.c | 100 +++++++++++++++++++++++++++++++++++++++-----
drivers/clk/meson/gxbb.h | 7 +++-
drivers/clk/meson/meson8b.c | 95 ++++++++++++++++++++++++++++++++++++-----
drivers/clk/meson/meson8b.h | 7 +++-
6 files changed, 278 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2989087fb52d..99b2738c204f 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -299,61 +299,126 @@ static struct clk_regmap axg_hifi_pll = {
},
};
-static struct clk_fixed_factor axg_fclk_div2 = {
+static struct clk_fixed_factor axg_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div2",
+ .name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor axg_fclk_div3 = {
+static struct clk_regmap axg_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 27,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div2_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div3",
+ .name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor axg_fclk_div4 = {
+static struct clk_regmap axg_fclk_div3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 28,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div3_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div4_div = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div4",
+ .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor axg_fclk_div5 = {
+static struct clk_regmap axg_fclk_div4 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div4_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div5_div = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div5",
+ .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor axg_fclk_div7 = {
+static struct clk_regmap axg_fclk_div5 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div5_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div7_div = {
.mult = 1,
.div = 7,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div7",
+ .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
+static struct clk_regmap axg_fclk_div7 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div7_div" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap axg_mpll_prediv = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_MPLL_CNTL5,
@@ -836,6 +901,11 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -909,6 +979,11 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_gp0_pll,
&axg_hifi_pll,
&axg_mpll_prediv,
+ &axg_fclk_div2,
+ &axg_fclk_div3,
+ &axg_fclk_div4,
+ &axg_fclk_div5,
+ &axg_fclk_div7,
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 6e5dc65041b5..b421df6a7ea0 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -122,8 +122,13 @@
#define CLKID_MPLL2_DIV 67
#define CLKID_MPLL3_DIV 68
#define CLKID_MPLL_PREDIV 70
+#define CLKID_FCLK_DIV2_DIV 71
+#define CLKID_FCLK_DIV3_DIV 72
+#define CLKID_FCLK_DIV4_DIV 73
+#define CLKID_FCLK_DIV5_DIV 74
+#define CLKID_FCLK_DIV7_DIV 75
-#define NR_CLKS 71
+#define NR_CLKS 76
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b62d181a6d33..70b4669cf7d6 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -490,61 +490,126 @@ static struct clk_regmap gxl_gp0_pll = {
},
};
-static struct clk_fixed_factor gxbb_fclk_div2 = {
+static struct clk_fixed_factor gxbb_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div2",
+ .name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor gxbb_fclk_div3 = {
+static struct clk_regmap gxbb_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 27,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div2_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor gxbb_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div3",
+ .name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor gxbb_fclk_div4 = {
+static struct clk_regmap gxbb_fclk_div3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 28,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div3_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor gxbb_fclk_div4_div = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div4",
+ .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor gxbb_fclk_div5 = {
+static struct clk_regmap gxbb_fclk_div4 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div4_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor gxbb_fclk_div5_div = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div5",
+ .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor gxbb_fclk_div7 = {
+static struct clk_regmap gxbb_fclk_div5 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div5_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor gxbb_fclk_div7_div = {
.mult = 1,
.div = 7,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div7",
+ .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
+static struct clk_regmap gxbb_fclk_div7 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div7_div" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap gxbb_mpll_prediv = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_MPLL_CNTL5,
@@ -1718,6 +1783,11 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -1869,6 +1939,11 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2022,6 +2097,11 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
&gxbb_fixed_pll,
&gxbb_sys_pll,
&gxbb_mpll_prediv,
+ &gxbb_fclk_div2,
+ &gxbb_fclk_div3,
+ &gxbb_fclk_div4,
+ &gxbb_fclk_div5,
+ &gxbb_fclk_div7,
};
struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index afae007ae1ec..9febf3f03739 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -199,8 +199,13 @@
#define CLKID_MPLL1_DIV 143
#define CLKID_MPLL2_DIV 144
#define CLKID_MPLL_PREDIV 145
+#define CLKID_FCLK_DIV2_DIV 146
+#define CLKID_FCLK_DIV3_DIV 147
+#define CLKID_FCLK_DIV4_DIV 148
+#define CLKID_FCLK_DIV5_DIV 149
+#define CLKID_FCLK_DIV7_DIV 150
-#define NR_CLKS 146
+#define NR_CLKS 151
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index f8b2f23c49de..9c9e3d180120 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -225,61 +225,126 @@ static struct clk_regmap meson8b_sys_pll = {
},
};
-static struct clk_fixed_factor meson8b_fclk_div2 = {
+static struct clk_fixed_factor meson8b_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div2",
+ .name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor meson8b_fclk_div3 = {
+static struct clk_regmap meson8b_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 27,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div2_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor meson8b_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div3",
+ .name = "fclk_div_div3",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor meson8b_fclk_div4 = {
+static struct clk_regmap meson8b_fclk_div3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 28,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div3_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor meson8b_fclk_div4_div = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div4",
+ .name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor meson8b_fclk_div5 = {
+static struct clk_regmap meson8b_fclk_div4 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div4_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor meson8b_fclk_div5_div = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div5",
+ .name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
-static struct clk_fixed_factor meson8b_fclk_div7 = {
+static struct clk_regmap meson8b_fclk_div5 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div5_div" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor meson8b_fclk_div7_div = {
.mult = 1,
.div = 7,
.hw.init = &(struct clk_init_data){
- .name = "fclk_div7",
+ .name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
};
+static struct clk_regmap meson8b_fclk_div7 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL6,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div7_div" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap meson8b_mpll_prediv = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_MPLL_CNTL5,
@@ -766,6 +831,11 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
[CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
[CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -866,6 +936,11 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_cpu_scale_out_sel,
&meson8b_cpu_clk,
&meson8b_mpll_prediv,
+ &meson8b_fclk_div2,
+ &meson8b_fclk_div3,
+ &meson8b_fclk_div4,
+ &meson8b_fclk_div5,
+ &meson8b_fclk_div7,
};
static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 839ffc9da5f7..6e414bd36981 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -78,8 +78,13 @@
#define CLKID_CPU_SCALE_DIV 102
#define CLKID_CPU_SCALE_OUT_SEL 103
#define CLKID_MPLL_PREDIV 104
+#define CLKID_FCLK_DIV2_DIV 105
+#define CLKID_FCLK_DIV3_DIV 106
+#define CLKID_FCLK_DIV4_DIV 107
+#define CLKID_FCLK_DIV5_DIV 108
+#define CLKID_FCLK_DIV7_DIV 109
-#define CLK_NR_CLKS 105
+#define CLK_NR_CLKS 110
/*
* include the CLKID and RESETID that have
--
2.14.3
mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/axg.c | 24 ++++++++++++++++++++----
drivers/clk/meson/axg.h | 3 ++-
drivers/clk/meson/gxbb.c | 23 ++++++++++++++++++++---
drivers/clk/meson/gxbb.h | 3 ++-
drivers/clk/meson/meson8b.c | 22 +++++++++++++++++++---
drivers/clk/meson/meson8b.h | 3 ++-
6 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index ed4a645753c4..2989087fb52d 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -354,6 +354,20 @@ static struct clk_fixed_factor axg_fclk_div7 = {
},
};
+static struct clk_regmap axg_mpll_prediv = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_MPLL_CNTL5,
+ .shift = 12,
+ .width = 1,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap axg_mpll0_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -386,7 +400,7 @@ static struct clk_regmap axg_mpll0_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -432,7 +446,7 @@ static struct clk_regmap axg_mpll1_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -478,7 +492,7 @@ static struct clk_regmap axg_mpll2_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -524,7 +538,7 @@ static struct clk_regmap axg_mpll3_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll3_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -821,6 +835,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
+ [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -893,6 +908,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_sys_pll,
&axg_gp0_pll,
&axg_hifi_pll,
+ &axg_mpll_prediv,
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 4916c7045c48..6e5dc65041b5 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -121,8 +121,9 @@
#define CLKID_MPLL1_DIV 66
#define CLKID_MPLL2_DIV 67
#define CLKID_MPLL3_DIV 68
+#define CLKID_MPLL_PREDIV 70
-#define NR_CLKS 70
+#define NR_CLKS 71
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index fdeb372863de..b62d181a6d33 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -545,6 +545,20 @@ static struct clk_fixed_factor gxbb_fclk_div7 = {
},
};
+static struct clk_regmap gxbb_mpll_prediv = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_MPLL_CNTL5,
+ .shift = 12,
+ .width = 1,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap gxbb_mpll0_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -572,7 +586,7 @@ static struct clk_regmap gxbb_mpll0_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -613,7 +627,7 @@ static struct clk_regmap gxbb_mpll1_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -654,7 +668,7 @@ static struct clk_regmap gxbb_mpll2_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -1703,6 +1717,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -1853,6 +1868,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2005,6 +2021,7 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
&gxbb_cts_amclk_div,
&gxbb_fixed_pll,
&gxbb_sys_pll,
+ &gxbb_mpll_prediv,
};
struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index a8e7b8884e95..afae007ae1ec 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -198,8 +198,9 @@
#define CLKID_MPLL0_DIV 142
#define CLKID_MPLL1_DIV 143
#define CLKID_MPLL2_DIV 144
+#define CLKID_MPLL_PREDIV 145
-#define NR_CLKS 145
+#define NR_CLKS 146
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 62c54a75a1d2..f8b2f23c49de 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -280,6 +280,20 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
},
};
+static struct clk_regmap meson8b_mpll_prediv = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_MPLL_CNTL5,
+ .shift = 12,
+ .width = 1,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap meson8b_mpll0_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -307,7 +321,7 @@ static struct clk_regmap meson8b_mpll0_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -348,7 +362,7 @@ static struct clk_regmap meson8b_mpll1_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -389,7 +403,7 @@ static struct clk_regmap meson8b_mpll2_div = {
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
.ops = &meson_clk_mpll_ops,
- .parent_names = (const char *[]){ "fixed_pll" },
+ .parent_names = (const char *[]){ "mpll_prediv" },
.num_parents = 1,
},
};
@@ -751,6 +765,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw,
[CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
[CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -850,6 +865,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_cpu_scale_div,
&meson8b_cpu_scale_out_sel,
&meson8b_cpu_clk,
+ &meson8b_mpll_prediv,
};
static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 73dae83d9932..839ffc9da5f7 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -77,8 +77,9 @@
#define CLKID_CPU_DIV3 101
#define CLKID_CPU_SCALE_DIV 102
#define CLKID_CPU_SCALE_OUT_SEL 103
+#define CLKID_MPLL_PREDIV 104
-#define CLK_NR_CLKS 104
+#define CLK_NR_CLKS 105
/*
* include the CLKID and RESETID that have
--
2.14.3
clk81 is a composite clock which parents all the peripheral clocks of the
platform. It is a critical clock which is used as provided by the
bootloader. We don't want to change its rate or reparent it, ever.
Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't
gate so the flag is useless, and the gate is already critical, so the
clock won't ever be unused.
Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is
read-only.
Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for
the divider. A peripheral clock should not try to change the rate of
clk81. Stopping the rate propagation is good way to make sure such request
would be ignored.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/gxbb.c | 6 ++----
drivers/clk/meson/meson8b.c | 6 ++----
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 70b4669cf7d6..db5e0dcbb5aa 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -775,7 +775,6 @@ static struct clk_regmap gxbb_mpeg_clk_sel = {
*/
.parent_names = clk81_parent_names,
.num_parents = ARRAY_SIZE(clk81_parent_names),
- .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
},
};
@@ -787,10 +786,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = {
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
- .ops = &clk_regmap_divider_ops,
+ .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" },
.num_parents = 1,
- .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
},
};
@@ -805,7 +803,7 @@ static struct clk_regmap gxbb_clk81 = {
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" },
.num_parents = 1,
- .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+ .flags = CLK_IS_CRITICAL,
},
};
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 9c9e3d180120..b324c44d36eb 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -506,7 +506,6 @@ static struct clk_regmap meson8b_mpeg_clk_sel = {
.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
"fclk_div5" },
.num_parents = 3,
- .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
},
};
@@ -518,10 +517,9 @@ struct clk_regmap meson8b_mpeg_clk_div = {
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
- .ops = &clk_regmap_divider_ops,
+ .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" },
.num_parents = 1,
- .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
},
};
@@ -535,7 +533,7 @@ struct clk_regmap meson8b_clk81 = {
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" },
.num_parents = 1,
- .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+ .flags = CLK_IS_CRITICAL,
},
};
--
2.14.3
Add the hifi pll to the axg clock controller. This clock maybe used as an
input of the axg audio clock controller. It uses the same settings table
as the gp0 pll but has a frac parameter allowing more precision.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/axg.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/axg.h | 2 +-
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 892572a2d70f..ed4a645753c4 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -245,6 +245,59 @@ static struct clk_regmap axg_gp0_pll = {
},
};
+const struct reg_sequence axg_hifi_init_regs[] = {
+ { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
+ { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
+ { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
+ { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
+ { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
+ { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
+};
+
+static struct clk_regmap axg_hifi_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_HIFI_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_HIFI_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_HIFI_PLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ },
+ .frac = {
+ .reg_off = HHI_HIFI_PLL_CNTL5,
+ .shift = 0,
+ .width = 13,
+ },
+ .l = {
+ .reg_off = HHI_HIFI_PLL_CNTL,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_HIFI_PLL_CNTL,
+ .shift = 29,
+ .width = 1,
+ },
+ .table = axg_gp0_pll_rate_table,
+ .init_regs = axg_hifi_init_regs,
+ .init_count = ARRAY_SIZE(axg_hifi_init_regs),
+ .flags = CLK_MESON_PLL_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll",
+ .ops = &meson_clk_pll_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
static struct clk_fixed_factor axg_fclk_div2 = {
.mult = 1,
@@ -767,6 +820,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
+ [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -838,6 +892,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_fixed_pll,
&axg_sys_pll,
&axg_gp0_pll,
+ &axg_hifi_pll,
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 4c1502a8b8c9..4916c7045c48 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -122,7 +122,7 @@
#define CLKID_MPLL2_DIV 67
#define CLKID_MPLL3_DIV 68
-#define NR_CLKS 69
+#define NR_CLKS 70
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
--
2.14.3
Provide an option for the pll driver to round to the rate closest to the
requested rate, instead of systematically rounding down.
This may allow the provided rate to be closer to the requested rate when
rounding up is not an issue
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/clk-pll.c | 17 +++++++++++++----
drivers/clk/meson/clkc.h | 2 ++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index d58961f35b71..65a7bd903551 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -105,7 +105,12 @@ static u16 __pll_params_with_frac(unsigned long rate,
u64 val = (u64)rate * pllt->n;
val <<= pllt->od + pllt->od2 + pllt->od3;
- val = div_u64(val * frac_max, parent_rate);
+
+ if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
+ val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
+ else
+ val = div_u64(val * frac_max, parent_rate);
+
val -= pllt->m * frac_max;
return min((u16)val, (u16)(frac_max - 1));
@@ -125,9 +130,13 @@ meson_clk_get_pll_settings(unsigned long rate,
while (table[i].rate && table[i].rate <= rate)
i++;
- /* Select the setting of the rounded down rate */
- if (i != 0)
- i--;
+ if (i != 0) {
+ if (MESON_PARM_APPLICABLE(&pll->frac) ||
+ !(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) ||
+ (abs(rate - table[i - 1].rate) <
+ abs(rate - table[i].rate)))
+ i--;
+ }
return (struct pll_rate_table *)&table[i];
}
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 9cdcd9b6c16c..8fe73c4edca8 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -71,6 +71,8 @@ struct pll_rate_table {
.od = (_od), \
}
+#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
+
struct meson_clk_pll_data {
struct parm m;
struct parm n;
--
2.14.3
Poking CNTL first may take the PLL out of reset while we are still
applying the initial settings, including the filter values
initialization. This is the case for the axg and gxl gp0 pll.
Doing this poke last ensures the pll stays in reset while the initial
settings are applied.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/axg.c | 2 +-
drivers/clk/meson/gxbb.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index acb63c8e0fd8..8226b82c67fd 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -193,12 +193,12 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
};
const struct reg_sequence axg_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
{ .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
+ { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
};
static struct clk_regmap axg_gp0_pll = {
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index bb0b0529ca81..3cd07f960489 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -390,10 +390,10 @@ static struct clk_regmap gxbb_sys_pll = {
};
const struct reg_sequence gxbb_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL, .def = 0x6a000228 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
+ { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 },
};
static struct clk_regmap gxbb_gp0_pll = {
@@ -437,12 +437,12 @@ static struct clk_regmap gxbb_gp0_pll = {
};
const struct reg_sequence gxl_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
{ .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
+ { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
};
static struct clk_regmap gxl_gp0_pll = {
--
2.14.3
Add the frac parameter for the gp0 pll of the axg and gxl.
This allows to achieve rates between the fixed settings provided
by the table.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/axg.c | 7 ++++++-
drivers/clk/meson/gxbb.c | 7 ++++++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 4f13929cd594..892572a2d70f 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -193,7 +193,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
};
const struct reg_sequence axg_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
+ { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
@@ -218,6 +218,11 @@ static struct clk_regmap axg_gp0_pll = {
.shift = 16,
.width = 2,
},
+ .frac = {
+ .reg_off = HHI_GP0_PLL_CNTL1,
+ .shift = 0,
+ .width = 10,
+ },
.l = {
.reg_off = HHI_GP0_PLL_CNTL,
.shift = 31,
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index ac48eef0f490..fdeb372863de 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -437,7 +437,7 @@ static struct clk_regmap gxbb_gp0_pll = {
};
const struct reg_sequence gxl_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
+ { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
@@ -462,6 +462,11 @@ static struct clk_regmap gxl_gp0_pll = {
.shift = 16,
.width = 2,
},
+ .frac = {
+ .reg_off = HHI_GP0_PLL_CNTL1,
+ .shift = 0,
+ .width = 10,
+ },
.l = {
.reg_off = HHI_GP0_PLL_CNTL,
.shift = 31,
--
2.14.3
Finding the appropriate settings of meson plls is too tricky to be done
entirely at runtime, using calculation only. Many combination of m, n
and od won't lock which is why we are using a table for this. However,
for plls having a fractional parameters, it is possible to improve on
the result provided by the table by calculating the frac parameter.
This change adds the calculation of frac when the parameter is available
and the rate provided by the table is not an exact match for the
requested rate.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/clk-pll.c | 137 +++++++++++++++++++++++++++++---------------
drivers/clk/meson/clkc.h | 13 +----
2 files changed, 91 insertions(+), 59 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 0b9b4422c968..d58961f35b71 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -2,6 +2,9 @@
* Copyright (c) 2015 Endless Mobile, Inc.
* Author: Carlo Caione <[email protected]>
*
+ * Copyright (c) 2018 Baylibre, SAS.
+ * Author: Jerome Brunet <[email protected]>
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
@@ -27,7 +30,7 @@
* | |
* FREF VCO
*
- * out = (in * M / N) >> OD
+ * out = in * (m + frac / frac_max) / (n << sum(ods))
*/
#include <linux/clk-provider.h>
@@ -48,73 +51,110 @@ meson_clk_pll_data(struct clk_regmap *clk)
return (struct meson_clk_pll_data *)clk->data;
}
+static unsigned long __pll_params_to_rate(unsigned long parent_rate,
+ const struct pll_rate_table *pllt,
+ u16 frac,
+ struct meson_clk_pll_data *pll)
+{
+ u64 rate = (u64)parent_rate * pllt->m;
+ unsigned int od = pllt->od + pllt->od2 + pllt->od3;
+
+ if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
+ u64 frac_rate = (u64)parent_rate * frac;
+
+ rate += DIV_ROUND_UP_ULL(frac_rate,
+ (1 << pll->frac.width));
+ }
+
+ return DIV_ROUND_UP_ULL(rate, pllt->n << od);
+}
+
static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
- u64 rate;
- u16 n, m, frac = 0, od, od2 = 0, od3 = 0;
-
- n = meson_parm_read(clk->map, &pll->n);
- m = meson_parm_read(clk->map, &pll->m);
- od = meson_parm_read(clk->map, &pll->od);
-
- if (MESON_PARM_APPLICABLE(&pll->od2))
- od2 = meson_parm_read(clk->map, &pll->od2);
+ struct pll_rate_table pllt;
+ u16 frac;
- if (MESON_PARM_APPLICABLE(&pll->od3))
- od3 = meson_parm_read(clk->map, &pll->od3);
+ pllt.n = meson_parm_read(clk->map, &pll->n);
+ pllt.m = meson_parm_read(clk->map, &pll->m);
+ pllt.od = meson_parm_read(clk->map, &pll->od);
- rate = (u64)m * parent_rate;
+ pllt.od2 = MESON_PARM_APPLICABLE(&pll->od2) ?
+ meson_parm_read(clk->map, &pll->od2) :
+ 0;
- if (MESON_PARM_APPLICABLE(&pll->frac)) {
- frac = meson_parm_read(clk->map, &pll->frac);
+ pllt.od3 = MESON_PARM_APPLICABLE(&pll->od3) ?
+ meson_parm_read(clk->map, &pll->od3) :
+ 0;
- rate += mul_u64_u32_shr(parent_rate, frac, pll->frac.width);
- }
+ frac = MESON_PARM_APPLICABLE(&pll->frac) ?
+ meson_parm_read(clk->map, &pll->frac) :
+ 0;
- return div_u64(rate, n) >> od >> od2 >> od3;
+ return __pll_params_to_rate(parent_rate, &pllt, frac, pll);
}
-static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static u16 __pll_params_with_frac(unsigned long rate,
+ unsigned long parent_rate,
+ const struct pll_rate_table *pllt,
+ struct meson_clk_pll_data *pll)
{
- struct clk_regmap *clk = to_clk_regmap(hw);
- struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
- const struct pll_rate_table *pllt;
-
- /*
- * if the table is missing, just return the current rate
- * since we don't have the other available frequencies
- */
- if (!pll->table)
- return meson_clk_pll_recalc_rate(hw, *parent_rate);
+ u16 frac_max = (1 << pll->frac.width);
+ u64 val = (u64)rate * pllt->n;
- for (pllt = pll->table; pllt->rate; pllt++) {
- if (rate <= pllt->rate)
- return pllt->rate;
- }
+ val <<= pllt->od + pllt->od2 + pllt->od3;
+ val = div_u64(val * frac_max, parent_rate);
+ val -= pllt->m * frac_max;
- /* else return the smallest value */
- return pll->table[0].rate;
+ return min((u16)val, (u16)(frac_max - 1));
}
static const struct pll_rate_table *
-meson_clk_get_pll_settings(const struct pll_rate_table *table,
- unsigned long rate)
+meson_clk_get_pll_settings(unsigned long rate,
+ struct meson_clk_pll_data *pll)
{
- const struct pll_rate_table *pllt;
+ const struct pll_rate_table *table = pll->table;
+ unsigned int i = 0;
if (!table)
return NULL;
- for (pllt = table; pllt->rate; pllt++) {
- if (rate == pllt->rate)
- return pllt;
- }
+ /* Find the first table element exceeding rate */
+ while (table[i].rate && table[i].rate <= rate)
+ i++;
+
+ /* Select the setting of the rounded down rate */
+ if (i != 0)
+ i--;
+
+ return (struct pll_rate_table *)&table[i];
+}
+
+static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+ const struct pll_rate_table *pllt =
+ meson_clk_get_pll_settings(rate, pll);
+ u16 frac;
+
+ if (!pllt)
+ return meson_clk_pll_recalc_rate(hw, *parent_rate);
+
+ if (!MESON_PARM_APPLICABLE(&pll->frac)
+ || rate == pllt->rate)
+ return pllt->rate;
- return NULL;
+ /*
+ * The rate provided by the setting is not an exact match, let's
+ * try to improve the result using the fractional parameter
+ */
+ frac = __pll_params_with_frac(rate, *parent_rate, pllt, pll);
+
+ return __pll_params_to_rate(*parent_rate, pllt, frac, pll);
}
static int meson_clk_pll_wait_lock(struct clk_hw *hw)
@@ -154,13 +194,14 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
const struct pll_rate_table *pllt;
unsigned long old_rate;
+ u16 frac = 0;
if (parent_rate == 0 || rate == 0)
return -EINVAL;
old_rate = rate;
- pllt = meson_clk_get_pll_settings(pll->table, rate);
+ pllt = meson_clk_get_pll_settings(rate, pll);
if (!pllt)
return -EINVAL;
@@ -177,8 +218,10 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
if (MESON_PARM_APPLICABLE(&pll->od3))
meson_parm_write(clk->map, &pll->od3, pllt->od3);
- if (MESON_PARM_APPLICABLE(&pll->frac))
- meson_parm_write(clk->map, &pll->frac, pllt->frac);
+ if (MESON_PARM_APPLICABLE(&pll->frac)) {
+ frac = __pll_params_with_frac(rate, parent_rate, pllt, pll);
+ meson_parm_write(clk->map, &pll->frac, frac);
+ }
/* make sure the reset is cleared at this point */
meson_parm_write(clk->map, &pll->rst, 0);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index ebd88afe1eb5..9cdcd9b6c16c 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -61,7 +61,6 @@ struct pll_rate_table {
u16 od;
u16 od2;
u16 od3;
- u16 frac;
};
#define PLL_RATE(_r, _m, _n, _od) \
@@ -70,17 +69,7 @@ struct pll_rate_table {
.m = (_m), \
.n = (_n), \
.od = (_od), \
- } \
-
-#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \
- { \
- .rate = (_r), \
- .m = (_m), \
- .n = (_n), \
- .od = (_od), \
- .od2 = (_od2), \
- .frac = (_frac), \
- } \
+ }
struct meson_clk_pll_data {
struct parm m;
--
2.14.3
After testing, it appears that the gxl (and axg) does not require the
special locking/reset loop which was initially added for it.
All the values present in the gxl table can locked with the simple lock
checking loop.
The change switches the gxl and axg gp0 back to the simple lock checking
loop and removes the code no longer required.
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/axg.c | 1 -
drivers/clk/meson/clk-pll.c | 12 +-----------
drivers/clk/meson/clkc.h | 2 --
drivers/clk/meson/gxbb.c | 1 -
4 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 8226b82c67fd..4f13929cd594 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -231,7 +231,6 @@ static struct clk_regmap axg_gp0_pll = {
.table = axg_gp0_pll_rate_table,
.init_regs = axg_gp0_init_regs,
.init_count = ARRAY_SIZE(axg_gp0_init_regs),
- .flags = CLK_MESON_PLL_LOCK_LOOP_RST,
},
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index f3d909719111..0b9b4422c968 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -121,19 +121,9 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
- int delay = pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST ?
- 100 : 24000000;
+ int delay = 24000000;
do {
- /* Specific wait loop for GXL/GXM GP0 PLL */
- if (pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST) {
- /* Procedure taken from the vendor kernel */
- meson_parm_write(clk->map, &pll->rst, 1);
- udelay(10);
- meson_parm_write(clk->map, &pll->rst, 0);
- mdelay(1);
- }
-
/* Is the clock locked now ? */
if (meson_parm_read(clk->map, &pll->l))
return 0;
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 8d8fe608cff4..ebd88afe1eb5 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -82,8 +82,6 @@ struct pll_rate_table {
.frac = (_frac), \
} \
-#define CLK_MESON_PLL_LOCK_LOOP_RST BIT(0)
-
struct meson_clk_pll_data {
struct parm m;
struct parm n;
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 3cd07f960489..ac48eef0f490 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -475,7 +475,6 @@ static struct clk_regmap gxl_gp0_pll = {
.table = gxl_gp0_pll_rate_table,
.init_regs = gxl_gp0_init_regs,
.init_count = ARRAY_SIZE(gxl_gp0_init_regs),
- .flags = CLK_MESON_PLL_LOCK_LOOP_RST,
},
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
--
2.14.3
Add the missing frac parameter to the meson8b fixed_pll. It seems to be
always on this platform, so the rate remains unchanged
Signed-off-by: Jerome Brunet <[email protected]>
---
drivers/clk/meson/meson8b.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index ea73b5de9672..62c54a75a1d2 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -125,6 +125,11 @@ static struct clk_regmap meson8b_fixed_pll = {
.shift = 16,
.width = 2,
},
+ .frac = {
+ .reg_off = HHI_MPLL_CNTL2,
+ .shift = 0,
+ .width = 12,
+ },
.l = {
.reg_off = HHI_MPLL_CNTL,
.shift = 31,
--
2.14.3
On 19/02/2018 12:21, Jerome Brunet wrote:
> This changeset applies on top of the previous updates series
> available here [0].
>
> Most of the changes proposed here are related to the plls of meson
> SoCs. Details can be found in each patches but, in nutshell, there
> is :
> * a bit of clean-up,
> * improved pll capabilities using the frac parameter,
> * several clocks added to model the tree more accurately.
>
> Beware: patch #10 depends on this core clock framework fix: [1]
> As explained in the description on the patch, if the gates are
> added w/o this fix, the system will crash when
> clk_disable_unused() is called.
>
> [0]: https://lkml.kernel.org/r/[email protected]
> [1]: https://lkml.kernel.org/r/[email protected]
>
> Jerome Brunet (11):
> clk: meson: add fractional part of meson8b fixed_pll
> clk: meson: poke pll CNTL last
> clk: meson: remove special gp0 lock loop
> clk: meson: improve pll driver results with frac
> clk: meson: add gp0 frac parameter for axg and gxl
> clk: meson: add ROUND_CLOSEST to the pll driver
> clk: meson: axg: add hifi clock bindings
> clk: meson: axg: add hifi pll clock
> clk: meson: add mpll pre-divider
> clk: meson: add fdiv clock gates
> clk: meson: clean-up clk81 clocks
>
> drivers/clk/meson/axg.c | 184 +++++++++++++++++++++++++++++++----
> drivers/clk/meson/axg.h | 8 +-
> drivers/clk/meson/clk-pll.c | 154 ++++++++++++++++++-----------
> drivers/clk/meson/clkc.h | 15 +--
> drivers/clk/meson/gxbb.c | 141 +++++++++++++++++++++++----
> drivers/clk/meson/gxbb.h | 10 +-
> drivers/clk/meson/meson8b.c | 128 ++++++++++++++++++++----
> drivers/clk/meson/meson8b.h | 8 +-
> include/dt-bindings/clock/axg-clkc.h | 1 +
> 9 files changed, 521 insertions(+), 128 deletions(-)
>
Tested on Odroid-C2 & LibreTech-CC,
Applied to meson's next/drivers tree.
Neil