This patch series add the qca8081 ethernet phy driver support, which
improve the wol feature, leverage at803x phy driver and add the fast
retrain, master/slave seed and CDT feature.
Changes in v3:
* correct a typo "excpet".
* remove the suffix "PHY" from phy name.
Changes in v2:
* add definitions of fast retrain related registers in mdio.h.
* break up the patch into small patches.
* improve the at803x legacy code.
Changes in v1:
* merge qca8081 phy driver into at803x.
* add cdt feature.
* leverage at803x phy driver helpers.
Luo Jie (13):
net: phy: at803x: replace AT803X_DEVICE_ADDR with MDIO_MMD_PCS
net: phy: at803x: use phy_modify()
net: phy: at803x: improve the WOL feature
net: phy: at803x: use GENMASK() for speed status
net: phy: add qca8081 ethernet phy driver
net: phy: add qca8081 read_status
net: phy: add qca8081 get_features
net: phy: add qca8081 config_aneg
net: phy: add constants for fast retrain related register
net: phy: add qca8081 config_init
net: phy: add qca8081 soft_reset and enable master/slave seed
net: phy: adjust qca8081 master/slave seed value if link down
net: phy: add qca8081 cdt feature
drivers/net/phy/at803x.c | 572 +++++++++++++++++++++++++++++++++++---
include/uapi/linux/mdio.h | 10 +
2 files changed, 536 insertions(+), 46 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Replace AT803X_DEVICE_ADDR with MDIO_MMD_PCS defined in mdio.h.
Signed-off-by: Luo Jie <[email protected]>
---
drivers/net/phy/at803x.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index bdac087058b2..5843b5b742f8 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -70,7 +70,6 @@
#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
#define AT803X_LED_CONTROL 0x18
-#define AT803X_DEVICE_ADDR 0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
@@ -329,7 +328,8 @@ static int at803x_set_wol(struct phy_device *phydev,
const u8 *mac;
int ret;
u32 value;
- unsigned int i, offsets[] = {
+ unsigned int i;
+ const unsigned int offsets[] = {
AT803X_LOC_MAC_ADDR_32_47_OFFSET,
AT803X_LOC_MAC_ADDR_16_31_OFFSET,
AT803X_LOC_MAC_ADDR_0_15_OFFSET,
@@ -345,7 +345,7 @@ static int at803x_set_wol(struct phy_device *phydev,
return -EINVAL;
for (i = 0; i < 3; i++)
- phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
+ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
value = phy_read(phydev, AT803X_INTR_ENABLE);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Use GENMASK() for the current speed value.
Signed-off-by: Luo Jie <[email protected]>
---
drivers/net/phy/at803x.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 2f7d96bd1be8..0b69e77a0510 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -33,10 +33,10 @@
#define AT803X_SFC_DISABLE_JABBER BIT(0)
#define AT803X_SPECIFIC_STATUS 0x11
-#define AT803X_SS_SPEED_MASK (3 << 14)
-#define AT803X_SS_SPEED_1000 (2 << 14)
-#define AT803X_SS_SPEED_100 (1 << 14)
-#define AT803X_SS_SPEED_10 (0 << 14)
+#define AT803X_SS_SPEED_MASK GENMASK(15, 14)
+#define AT803X_SS_SPEED_1000 2
+#define AT803X_SS_SPEED_100 1
+#define AT803X_SS_SPEED_10 0
#define AT803X_SS_DUPLEX BIT(13)
#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
#define AT803X_SS_MDIX BIT(6)
@@ -969,7 +969,7 @@ static int at803x_read_status(struct phy_device *phydev)
if (sfc < 0)
return sfc;
- switch (ss & AT803X_SS_SPEED_MASK) {
+ switch (FIELD_GET(AT803X_SS_SPEED_MASK, ss)) {
case AT803X_SS_SPEED_10:
phydev->speed = SPEED_10;
break;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Reuse at803x phy driver config_aneg excepting
adding 2500M auto-negotiation.
Signed-off-by: Luo Jie <[email protected]>
---
drivers/net/phy/at803x.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 0c22ef735230..c124d3fe40fb 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -1084,7 +1084,30 @@ static int at803x_config_aneg(struct phy_device *phydev)
return ret;
}
- return genphy_config_aneg(phydev);
+ /* Do not restart auto-negotiation by setting ret to 0 defautly,
+ * when calling __genphy_config_aneg later.
+ */
+ ret = 0;
+
+ if (phydev->drv->phy_id == QCA8081_PHY_ID) {
+ int phy_ctrl = 0;
+
+ /* The reg MII_BMCR also needs to be configured for force mode, the
+ * genphy_config_aneg is also needed.
+ */
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ genphy_c45_pma_setup_forced(phydev);
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
+ phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
+
+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
+ MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
+ if (ret < 0)
+ return ret;
+ }
+
+ return __genphy_config_aneg(phydev, ret);
}
static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
@@ -1503,6 +1526,7 @@ static struct phy_driver at803x_driver[] = {
.set_wol = at803x_set_wol,
.get_wol = at803x_get_wol,
.get_features = at803x_get_features,
+ .config_aneg = at803x_config_aneg,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_status = qca808x_read_status,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
On Mon, Oct 18, 2021 at 11:33:21AM +0800, Luo Jie wrote:
> Replace AT803X_DEVICE_ADDR with MDIO_MMD_PCS defined in mdio.h.
>
> Signed-off-by: Luo Jie <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
On Mon, Oct 18, 2021 at 11:33:24AM +0800, Luo Jie wrote:
> Use GENMASK() for the current speed value.
>
> Signed-off-by: Luo Jie <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
On Mon, Oct 18, 2021 at 11:33:28AM +0800, Luo Jie wrote:
> Reuse at803x phy driver config_aneg excepting
> adding 2500M auto-negotiation.
>
> Signed-off-by: Luo Jie <[email protected]>
> ---
> drivers/net/phy/at803x.c | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
> index 0c22ef735230..c124d3fe40fb 100644
> --- a/drivers/net/phy/at803x.c
> +++ b/drivers/net/phy/at803x.c
> @@ -1084,7 +1084,30 @@ static int at803x_config_aneg(struct phy_device *phydev)
> return ret;
> }
>
> - return genphy_config_aneg(phydev);
> + /* Do not restart auto-negotiation by setting ret to 0 defautly,
> + * when calling __genphy_config_aneg later.
> + */
> + ret = 0;
> +
> + if (phydev->drv->phy_id == QCA8081_PHY_ID) {
> + int phy_ctrl = 0;
> +
> + /* The reg MII_BMCR also needs to be configured for force mode, the
> + * genphy_config_aneg is also needed.
> + */
> + if (phydev->autoneg == AUTONEG_DISABLE)
> + genphy_c45_pma_setup_forced(phydev);
> +
> + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
> + phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
> +
> + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
> + MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
Does the PHY also have MDIO_MMD_AN, MDIO_AN_ADVERTISE ? I'm wondering
if you can use genphy_c45_an_config_aneg()
Andrew
On 10/19/2021 5:37 AM, Andrew Lunn wrote:
> On Mon, Oct 18, 2021 at 11:33:28AM +0800, Luo Jie wrote:
>> Reuse at803x phy driver config_aneg excepting
>> adding 2500M auto-negotiation.
>>
>> Signed-off-by: Luo Jie <[email protected]>
>> ---
>> drivers/net/phy/at803x.c | 26 +++++++++++++++++++++++++-
>> 1 file changed, 25 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
>> index 0c22ef735230..c124d3fe40fb 100644
>> --- a/drivers/net/phy/at803x.c
>> +++ b/drivers/net/phy/at803x.c
>> @@ -1084,7 +1084,30 @@ static int at803x_config_aneg(struct phy_device *phydev)
>> return ret;
>> }
>>
>> - return genphy_config_aneg(phydev);
>> + /* Do not restart auto-negotiation by setting ret to 0 defautly,
>> + * when calling __genphy_config_aneg later.
>> + */
>> + ret = 0;
>> +
>> + if (phydev->drv->phy_id == QCA8081_PHY_ID) {
>> + int phy_ctrl = 0;
>> +
>> + /* The reg MII_BMCR also needs to be configured for force mode, the
>> + * genphy_config_aneg is also needed.
>> + */
>> + if (phydev->autoneg == AUTONEG_DISABLE)
>> + genphy_c45_pma_setup_forced(phydev);
>> +
>> + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
>> + phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
>> +
>> + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
>> + MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
> Does the PHY also have MDIO_MMD_AN, MDIO_AN_ADVERTISE ? I'm wondering
> if you can use genphy_c45_an_config_aneg()
>
> Andrew
Thanks Andrew for this comments, since the PHY does not have the regiser
MDIO_AN_ADVERTISE,
genphy_c45_an_config_aneg can't be used here.