PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2,
with all SW communication to ADC going through PMK8550 which
communicates with other PMICs through PBS. The major difference is
that the register interface used here is that of an SDAM present on
PMK8550, rather than a dedicated ADC peripheral. There may be more than one
SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may
be used for either immediate reads (same functionality as previous PMIC5 and
PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5
Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality
combined into the same driver.
Patches 1-5 update the name of the previous generation of PMIC5 ADC peripherals
from ADC7 to ADC5 Gen2, as this is the correct name and it makes more sense now
to update it, with the addition of the latest ADC5 Gen3 peripheral support.
Patches 6 and 7 add bindings and driver support respectively for ADC5 Gen3.
Patches 8-11 are for an additional change, where the QCOM ADC dt-bindings files
are moved from dt-bindings/iio to dt-bindings/iio/adc folder, as they are
specifically for ADC devices.
Jishnu Prakash (11):
iio: adc: Update bindings for ADC7 name used on QCOM PMICs
iio: adc: Update driver files for ADC7 rename for QCOM PMICs
ARM: dts: qcom: Update devicetree for ADC7 rename for QCOM PMICs
iio: adc: Update bindings to remove support for ADC7 name used on QCOM
PMICs
iio: adc: qcom-spmi-adc5: remove support for ADC7 compatible string
iio: adc: Add QCOM PMIC5 Gen3 ADC bindings
iio: adc: Add support for QCOM PMIC5 Gen3 ADC
dt-bindings: iio: adc: Copy QCOM ADC bindings files
iio: adc: Update QCOM ADC drivers for bindings path change
ARM: dts: qcom: Update devicetree for QCOM ADC bindings path change
dt-bindings: iio: remove QCOM ADC files from iio folder
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 131 +-
.../bindings/thermal/qcom-spmi-adc-tm5.yaml | 19 +-
arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmk8350.dtsi | 4 +-
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 8 +-
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 48 +-
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +-
.../boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 +-
drivers/iio/adc/Kconfig | 25 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/qcom-spmi-adc5-gen3.c | 1193 +++++++++++++++++
drivers/iio/adc/qcom-spmi-adc5.c | 93 +-
drivers/iio/adc/qcom-spmi-vadc.c | 2 +-
drivers/iio/adc/qcom-vadc-common.c | 36 +-
.../iio/adc/qcom,spmi-adc5-gen2-pm8350.h | 64 +
.../iio/adc/qcom,spmi-adc5-gen2-pm8350b.h | 89 ++
.../iio/adc/qcom,spmi-adc5-gen2-pmk8350.h | 47 +
.../iio/adc/qcom,spmi-adc5-gen2-pmr735a.h | 29 +
.../iio/adc/qcom,spmi-adc5-gen2-pmr735b.h | 28 +
.../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 48 +
.../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 97 ++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +
.../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 54 +
.../iio/{ => adc}/qcom,spmi-vadc.h | 209 ++-
.../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 63 -
.../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 --
.../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 -
.../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 -
.../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 -
include/linux/iio/adc/qcom-vadc-common.h | 12 +-
50 files changed, 2088 insertions(+), 474 deletions(-)
create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (59%)
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
--
2.25.1
Now that usage of "ADC7" name has been replaced with usage of "ADC5
Gen2" name everywhere, remove the "qcom,spmi-adc7" compatible string.
Signed-off-by: Jishnu Prakash <[email protected]>
---
drivers/iio/adc/qcom-spmi-adc5.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c
index 3ac1ee500a67..6cebeaa69a75 100644
--- a/drivers/iio/adc/qcom-spmi-adc5.c
+++ b/drivers/iio/adc/qcom-spmi-adc5.c
@@ -807,10 +807,6 @@ static const struct of_device_id adc5_match_table[] = {
.compatible = "qcom,spmi-adc5",
.data = &adc5_data_pmic,
},
- {
- .compatible = "qcom,spmi-adc7",
- .data = &adc5_gen2_data_pmic,
- },
{
.compatible = "qcom,spmi-adc5-gen2",
.data = &adc5_gen2_data_pmic,
--
2.25.1
For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
going through PBS firmware through a single register interface. This
interface is implemented on an SDAM peripheral on the master PMIC PMK8550
rather than a dedicated ADC peripheral.
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++--
.../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++
.../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++
.../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++
.../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++
include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++
6 files changed, 402 insertions(+), 12 deletions(-)
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index eb7d16e385ad..090113e62d52 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -13,8 +13,8 @@ maintainers:
description: |
SPMI PMIC voltage ADC (VADC) provides interface to clients to read
voltage. The VADC is a 15-bit sigma-delta ADC.
- SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read
- voltage. The VADC is a 16-bit sigma-delta ADC.
+ SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to
+ clients to read voltage. The VADC is a 16-bit sigma-delta ADC.
properties:
compatible:
@@ -27,10 +27,11 @@ properties:
- qcom,spmi-adc5
- qcom,spmi-adc-rev2
- qcom,spmi-adc5-gen2
+ - qcom,spmi-adc5-gen3
reg:
description: VADC base address in the SPMI PMIC register map
- maxItems: 1
+ minItems: 1
'#address-cells':
const: 1
@@ -38,6 +39,12 @@ properties:
'#size-cells':
const: 0
+ "#thermal-sensor-cells":
+ const: 1
+ description:
+ Number of cells required to uniquely identify the thermal sensors. Since
+ we have multiple sensors this is set to 1.
+
'#io-channel-cells':
const: 1
@@ -71,8 +78,8 @@ patternProperties:
description: |
ADC channel number.
See include/dt-bindings/iio/qcom,spmi-vadc.h
- For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
- in the PMIC-specific files in include/dt-bindings/iio/.
+ For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per
+ PMIC in the PMIC-specific files in include/dt-bindings/iio/.
label:
$ref: /schemas/types.yaml#/definitions/string
@@ -114,11 +121,12 @@ patternProperties:
channel calibration. If property is not found, channel will be
calibrated with 0.625V and 1.25V reference channels, also
known as absolute calibration.
- - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
- "qcom,spmi-adc-rev2", if this property is specified VADC will use
- the VDD reference (1.875V) and GND for channel calibration. If
- property is not found, channel will be calibrated with 0V and 1.25V
- reference channels, also known as absolute calibration.
+ - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2",
+ "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property
+ is specified VADC will use the VDD reference (1.875V) and GND for
+ channel calibration. If property is not found, channel will be
+ calibrated with 0V and 1.25V reference channels, also known as
+ absolute calibration.
type: boolean
qcom,hw-settle-time:
@@ -136,6 +144,12 @@ patternProperties:
from the ADC that is an average of multiple samples. The value
selected is 2^(value).
+ qcom,adc-tm-type:
+ description: |
+ Indicates if ADC_TM monitoring is done on this channel.
+ Defined for compatible property "qcom,spmi-adc5-gen3".
+ type: boolean
+
required:
- reg
@@ -213,7 +227,9 @@ allOf:
properties:
compatible:
contains:
- const: qcom,spmi-adc5-gen2
+ enum:
+ - qcom,spmi-adc5-gen2
+ - qcom,spmi-adc5-gen3
then:
patternProperties:
@@ -299,7 +315,7 @@ examples:
label = "xo_therm";
};
- channel@47 {
+ channel@147 {
reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
@@ -307,3 +323,80 @@ examples:
};
};
};
+
+ - |
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
+
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VADC node */
+ pmk8550_vadc: vadc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
+
+ /* PMK8550 Channel nodes */
+ channel@3 {
+ reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
+ label = "pmk8550_xo_therm";
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm-type;
+ };
+
+ /* PM8550 Channel nodes */
+ channel@103 {
+ reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@18e {
+ reg = <PM8550_ADC5_GEN3_VPH_PWR>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@703 {
+ reg = <PM8550B_ADC5_GEN3_DIE_TEMP>;
+ label = "pm8550b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@78e {
+ reg = <PM8550B_ADC5_GEN3_VPH_PWR>;
+ label = "pm8550b_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@78f {
+ reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
new file mode 100644
index 000000000000..74e6e2f6f9ed
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+
+#ifndef PM8550_SID
+#define PM8550_SID 1
+#endif
+
+/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
+#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
+#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
+#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
+#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
+
+#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04)
+#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05)
+#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06)
+#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07)
+#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d)
+
+/* 100k pull-up */
+#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44)
+#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45)
+#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46)
+#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47)
+#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d)
+
+/* 1/3 Divider */
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d)
+
+#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
new file mode 100644
index 000000000000..35483dfd970e
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+
+#ifndef PM8550B_SID
+#define PM8550B_SID 7
+#endif
+
+/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
+#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00)
+#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01)
+#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02)
+#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03)
+
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d)
+
+#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10)
+#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11)
+#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12)
+#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13)
+#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15)
+#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17)
+#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18)
+#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19)
+#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a)
+#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b)
+#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e)
+#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f)
+#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1)
+
+/* 30k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d)
+
+#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33)
+
+/* 100k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d)
+
+#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53)
+
+/* 400k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d)
+
+#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73)
+
+/* 1/3 Divider */
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c)
+
+#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
new file mode 100644
index 000000000000..337e13f7f56f
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+
+/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
+#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00)
+#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01)
+#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02)
+#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03)
+
+#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00)
+#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01)
+#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02)
+#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
new file mode 100644
index 000000000000..126fc16d5b20
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+
+#ifndef PMK8550_SID
+#define PMK8550_SID 0
+#endif
+
+/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
+#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00)
+#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01)
+#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02)
+#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03)
+
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a)
+
+/* 30k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a)
+
+/* 100k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a)
+
+/* 400k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
index b1413c62ad27..ca5a0a947b3b 100644
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -298,4 +298,82 @@
#define ADC5_GEN2_SBUx 0x94
#define ADC5_GEN2_VBAT_2S_MID 0x96
+/* ADC channels for PMIC5 Gen3 */
+
+#define ADC5_GEN3_OFFSET_REF 0x00
+#define ADC5_GEN3_1P25VREF 0x01
+#define ADC5_GEN3_VREF_VADC 0x02
+#define ADC5_GEN3_DIE_TEMP 0x03
+
+#define ADC5_GEN3_AMUX1_THM 0x04
+#define ADC5_GEN3_AMUX2_THM 0x05
+#define ADC5_GEN3_AMUX3_THM 0x06
+#define ADC5_GEN3_AMUX4_THM 0x07
+#define ADC5_GEN3_AMUX5_THM 0x08
+#define ADC5_GEN3_AMUX6_THM 0x09
+#define ADC5_GEN3_AMUX1_GPIO 0x0a
+#define ADC5_GEN3_AMUX2_GPIO 0x0b
+#define ADC5_GEN3_AMUX3_GPIO 0x0c
+#define ADC5_GEN3_AMUX4_GPIO 0x0d
+
+#define ADC5_GEN3_CHG_TEMP 0x10
+#define ADC5_GEN3_USB_SNS_V_16 0x11
+#define ADC5_GEN3_VIN_DIV16_MUX 0x12
+#define ADC5_GEN3_VREF_BAT_THERM 0x15
+#define ADC5_GEN3_IIN_FB 0x17
+#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
+#define ADC5_GEN3_IIN_SMB 0x19
+#define ADC5_GEN3_ICHG_SMB 0x1b
+#define ADC5_GEN3_ICHG_FB 0xa1
+
+/* 30k pull-up1 */
+#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
+#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
+#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
+#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
+#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
+#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
+#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
+#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
+#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
+#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
+
+/* 100k pull-up2 */
+#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
+#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
+#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
+#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
+#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
+#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
+#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
+#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
+#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
+#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
+
+/* 400k pull-up3 */
+#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
+#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
+#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
+#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
+#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
+#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
+#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
+#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
+#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
+#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
+
+/* 1/3 Divider */
+#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
+#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
+#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
+
+#define ADC5_GEN3_VPH_PWR 0x8e
+#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
+
+#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
+#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
+#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
+
+#define ADC5_GEN3_OFFSET_EXT2 0xf8
+
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
--
2.25.1
The name "ADC7" needs to be replaced with the name "ADC5_GEN2"
everywhere to match the convention used for these ADC peripherals
on Qualcomm Technologies, Inc. PMICs. Update devicetree files for
the corresponding name change done in bindings and driver.
Signed-off-by: Jishnu Prakash <[email protected]>
---
arch/arm64/boot/dts/qcom/pmk8350.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 8 ++--
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 48 +++++++++----------
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +-
.../boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 +-
7 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
index bc6297e7253e..149d2bb43d2d 100644
--- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
@@ -50,7 +50,7 @@ pon_resin: resin {
};
pmk8350_vadc: adc@3100 {
- compatible = "qcom,spmi-adc7";
+ compatible = "qcom,spmi-adc5-gen2";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
@@ -59,7 +59,7 @@ pmk8350_vadc: adc@3100 {
};
pmk8350_adc_tm: adc-tm@3400 {
- compatible = "qcom,adc-tm7";
+ compatible = "qcom,spmi-adc-tm5-gen2";
reg = <0x3400>;
interrupts = <PMK8350_SID 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 15222e92e3f5..bc65e6c6232f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -7,7 +7,7 @@
/dts-v1/;
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h>
#include "sc7280-idp.dtsi"
#include "pmr735a.dtsi"
@@ -74,7 +74,7 @@ &nvme_3v3_regulator {
&pmk8350_vadc {
pmr735a-die-temp@403 {
- reg = <PMR735A_ADC7_DIE_TEMP>;
+ reg = <PMR735A_ADC5_GEN2_DIE_TEMP>;
label = "pmr735a_die_temp";
qcom,pre-scaling = <1 1>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 21027042cf13..da413694e230 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
@@ -433,7 +433,7 @@ &pcie1_phy {
&pmk8350_vadc {
pmk8350-die-temp@3 {
- reg = <PMK8350_ADC7_DIE_TEMP>;
+ reg = <PMK8350_ADC5_GEN2_DIE_TEMP>;
label = "pmk8350_die_temp";
qcom,pre-scaling = <1 1>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index 9137db066d9e..ed26bff7432d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -11,8 +11,8 @@
* Copyright 2022 Google LLC.
*/
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@@ -384,13 +384,13 @@ &pm8350c_pwm {
&pmk8350_vadc {
pmk8350-die-temp@3 {
- reg = <PMK8350_ADC7_DIE_TEMP>;
+ reg = <PMK8350_ADC5_GEN2_DIE_TEMP>;
label = "pmk8350_die_temp";
qcom,pre-scaling = <1 1>;
};
pmr735a-die-temp@403 {
- reg = <PMR735A_ADC7_DIE_TEMP>;
+ reg = <PMR735A_ADC5_GEN2_DIE_TEMP>;
label = "pmr735a_die_temp";
qcom,pre-scaling = <1 1>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 7cc3028440b6..cfd5dbbacdcb 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -7,9 +7,9 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@@ -747,7 +747,7 @@ &pmk8280_adc_tm {
sys-therm@0 {
reg = <0>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(1)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -755,7 +755,7 @@ sys-therm@0 {
sys-therm@1 {
reg = <1>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(1)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -763,7 +763,7 @@ sys-therm@1 {
sys-therm@2 {
reg = <2>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(1)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -771,7 +771,7 @@ sys-therm@2 {
sys-therm@3 {
reg = <3>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -779,7 +779,7 @@ sys-therm@3 {
sys-therm@4 {
reg = <4>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(3)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -787,7 +787,7 @@ sys-therm@4 {
sys-therm@5 {
reg = <5>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(3)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -795,7 +795,7 @@ sys-therm@5 {
sys-therm@6 {
reg = <6>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(3)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -803,7 +803,7 @@ sys-therm@6 {
sys-therm@7 {
reg = <7>;
- io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+ io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(3)>;
qcom,hw-settle-time-us = <200>;
qcom,avg-samples = <2>;
qcom,ratiometric;
@@ -837,88 +837,88 @@ &pmk8280_vadc {
status = "okay";
pmic-die-temp@3 {
- reg = <PMK8350_ADC7_DIE_TEMP>;
+ reg = <PMK8350_ADC5_GEN2_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmk8350_die_temp";
};
xo-therm@44 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ reg = <PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "pmk8350_xo_therm";
};
pmic-die-temp@103 {
- reg = <PM8350_ADC7_DIE_TEMP(1)>;
+ reg = <PM8350_ADC5_GEN2_DIE_TEMP(1)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_1_die_temp";
};
sys-therm@144 {
- reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm1";
};
sys-therm@145 {
- reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm2";
};
sys-therm@146 {
- reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm3";
};
sys-therm@147 {
- reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm4";
};
pmic-die-temp@303 {
- reg = <PM8350_ADC7_DIE_TEMP(3)>;
+ reg = <PM8350_ADC5_GEN2_DIE_TEMP(3)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_2_die_temp";
};
sys-therm@344 {
- reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm5";
};
sys-therm@345 {
- reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm6";
};
sys-therm@346 {
- reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm7";
};
sys-therm@347 {
- reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm8";
};
pmic-die-temp@403 {
- reg = <PMR735A_ADC7_DIE_TEMP>;
+ reg = <PMR735A_ADC5_GEN2_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmr735a_die_temp";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
index a0ba535bb6c9..ae9491adaa6a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
@@ -78,7 +78,7 @@ pmk8280_pon_resin: resin {
};
pmk8280_vadc: adc@3100 {
- compatible = "qcom,spmi-adc7";
+ compatible = "qcom,spmi-adc5-gen2";
reg = <0x3100>;
interrupts-extended = <&spmi_bus 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index e3dc49951523..52119cc1250e 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -9,7 +9,7 @@
#define PMK8350_SID 6
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -517,7 +517,7 @@ &pmk8350_rtc {
&pmk8350_vadc {
adc-chan@644 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ reg = <PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
--
2.25.1
The name used initially for this version of Qualcomm Technologies, Inc.
PMIC ADC was ADC7, following the convention of calling the PMIC generation
PMIC7. However, the names were later amended internally to ADC5 Gen2 and
PMIC5 Gen2. In addition, the latest PMIC generation now is known as
PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more
sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7.
Since this affects ADC devices across some PMICs, update the names accordingly.
In order to avoid breaking the existing implementations of ADC7, add
support for ADC5 Gen2 first now and remove the ADC7 support in a later
patch.
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 21 +++--
.../bindings/thermal/qcom-spmi-adc-tm5.yaml | 16 ++--
.../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 +++++++++++++
.../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 +++++++++++++++++++
.../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 ++++++++++
.../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++++++
.../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++++++
include/dt-bindings/iio/qcom,spmi-vadc.h | 77 ++++++++++++++++
8 files changed, 354 insertions(+), 17 deletions(-)
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index ad7d6fc49de5..f886977de165 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -13,7 +13,7 @@ maintainers:
description: |
SPMI PMIC voltage ADC (VADC) provides interface to clients to read
voltage. The VADC is a 15-bit sigma-delta ADC.
- SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read
+ SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read
voltage. The VADC is a 16-bit sigma-delta ADC.
properties:
@@ -27,6 +27,7 @@ properties:
- qcom,spmi-adc5
- qcom,spmi-adc-rev2
- qcom,spmi-adc7
+ - qcom,spmi-adc5-gen2
reg:
description: VADC base address in the SPMI PMIC register map
@@ -71,7 +72,7 @@ patternProperties:
description: |
ADC channel number.
See include/dt-bindings/iio/qcom,spmi-vadc.h
- For PMIC7 ADC, the channel numbers are specified separately per PMIC
+ For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
in the PMIC-specific files in include/dt-bindings/iio/.
label:
@@ -114,7 +115,7 @@ patternProperties:
channel calibration. If property is not found, channel will be
calibrated with 0.625V and 1.25V reference channels, also
known as absolute calibration.
- - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
+ - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
"qcom,spmi-adc-rev2", if this property is specified VADC will use
the VDD reference (1.875V) and GND for channel calibration. If
property is not found, channel will be calibrated with 0V and 1.25V
@@ -213,7 +214,9 @@ allOf:
properties:
compatible:
contains:
- const: qcom,spmi-adc7
+ enum :
+ - qcom,spmi-adc7
+ - qcom,spmi-adc5-gen2
then:
patternProperties:
@@ -277,8 +280,8 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
spmi {
@@ -286,21 +289,21 @@ examples:
#size-cells = <0>;
adc@3100 {
reg = <0x3100>;
- compatible = "qcom,spmi-adc7";
+ compatible = "qcom,spmi-adc5-gen2";
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
/* Other properties are omitted */
channel@44 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ reg = <PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm";
};
channel@47 {
- reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "conn_therm";
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
index 3c81def03c84..01d57f13d254 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -204,29 +204,29 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
+ #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
spmi_bus {
#address-cells = <1>;
#size-cells = <0>;
pmk8350_vadc: adc@3100 {
reg = <0x3100>;
- compatible = "qcom,spmi-adc7";
+ compatible = "qcom,spmi-adc5-gen2";
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
/* Other properties are omitted */
channel@44 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ reg = <PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm";
};
channel@147 {
- reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "conn_therm";
@@ -241,9 +241,9 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- pmk8350-xo-therm@0 {
+ xo-therm@0 {
reg = <0>;
- io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>;
qcom,decimation = <340>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
@@ -251,7 +251,7 @@ examples:
conn-therm@1 {
reg = <1>;
- io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ io-channels = <&pmk8350_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
qcom,avg-samples = <2>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
new file mode 100644
index 000000000000..77259beaf6e9
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
+
+/* ADC channels for PM8350_ADC for PMIC5 Gen2 */
+#define PM8350_ADC5_GEN2_REF_GND(sid) ((sid) << 8 | 0x0)
+#define PM8350_ADC5_GEN2_1P25VREF(sid) ((sid) << 8 | 0x01)
+#define PM8350_ADC5_GEN2_VREF_VADC(sid) ((sid) << 8 | 0x02)
+#define PM8350_ADC5_GEN2_DIE_TEMP(sid) ((sid) << 8 | 0x03)
+
+#define PM8350_ADC5_GEN2_AMUX_THM1(sid) ((sid) << 8 | 0x04)
+#define PM8350_ADC5_GEN2_AMUX_THM2(sid) ((sid) << 8 | 0x05)
+#define PM8350_ADC5_GEN2_AMUX_THM3(sid) ((sid) << 8 | 0x06)
+#define PM8350_ADC5_GEN2_AMUX_THM4(sid) ((sid) << 8 | 0x07)
+#define PM8350_ADC5_GEN2_AMUX_THM5(sid) ((sid) << 8 | 0x08)
+#define PM8350_ADC5_GEN2_GPIO1(sid) ((sid) << 8 | 0x0a)
+#define PM8350_ADC5_GEN2_GPIO2(sid) ((sid) << 8 | 0x0b)
+#define PM8350_ADC5_GEN2_GPIO3(sid) ((sid) << 8 | 0x0c)
+#define PM8350_ADC5_GEN2_GPIO4(sid) ((sid) << 8 | 0x0d)
+
+/* 30k pull-up1 */
+#define PM8350_ADC5_GEN2_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24)
+#define PM8350_ADC5_GEN2_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25)
+#define PM8350_ADC5_GEN2_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26)
+#define PM8350_ADC5_GEN2_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27)
+#define PM8350_ADC5_GEN2_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28)
+#define PM8350_ADC5_GEN2_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a)
+#define PM8350_ADC5_GEN2_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b)
+#define PM8350_ADC5_GEN2_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c)
+#define PM8350_ADC5_GEN2_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d)
+
+/* 100k pull-up2 */
+#define PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44)
+#define PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45)
+#define PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46)
+#define PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47)
+#define PM8350_ADC5_GEN2_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48)
+#define PM8350_ADC5_GEN2_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a)
+#define PM8350_ADC5_GEN2_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b)
+#define PM8350_ADC5_GEN2_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c)
+#define PM8350_ADC5_GEN2_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d)
+
+/* 400k pull-up3 */
+#define PM8350_ADC5_GEN2_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64)
+#define PM8350_ADC5_GEN2_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65)
+#define PM8350_ADC5_GEN2_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66)
+#define PM8350_ADC5_GEN2_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67)
+#define PM8350_ADC5_GEN2_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68)
+#define PM8350_ADC5_GEN2_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a)
+#define PM8350_ADC5_GEN2_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b)
+#define PM8350_ADC5_GEN2_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c)
+#define PM8350_ADC5_GEN2_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d)
+
+/* 1/3 Divider */
+#define PM8350_ADC5_GEN2_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d)
+
+#define PM8350_ADC5_GEN2_VPH_PWR(sid) ((sid) << 8 | 0x8e)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
new file mode 100644
index 000000000000..c7bb54e0b6a6
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
+
+#ifndef PM8350B_SID
+#define PM8350B_SID 3
+#endif
+
+/* ADC channels for PM8350B_ADC for PMIC5 Gen2 */
+#define PM8350B_ADC5_GEN2_REF_GND (PM8350B_SID << 8 | 0x0)
+#define PM8350B_ADC5_GEN2_1P25VREF (PM8350B_SID << 8 | 0x01)
+#define PM8350B_ADC5_GEN2_VREF_VADC (PM8350B_SID << 8 | 0x02)
+#define PM8350B_ADC5_GEN2_DIE_TEMP (PM8350B_SID << 8 | 0x03)
+
+#define PM8350B_ADC5_GEN2_AMUX_THM1 (PM8350B_SID << 8 | 0x04)
+#define PM8350B_ADC5_GEN2_AMUX_THM2 (PM8350B_SID << 8 | 0x05)
+#define PM8350B_ADC5_GEN2_AMUX_THM3 (PM8350B_SID << 8 | 0x06)
+#define PM8350B_ADC5_GEN2_AMUX_THM4 (PM8350B_SID << 8 | 0x07)
+#define PM8350B_ADC5_GEN2_AMUX_THM5 (PM8350B_SID << 8 | 0x08)
+#define PM8350B_ADC5_GEN2_AMUX_THM6 (PM8350B_SID << 8 | 0x09)
+#define PM8350B_ADC5_GEN2_GPIO1 (PM8350B_SID << 8 | 0x0a)
+#define PM8350B_ADC5_GEN2_GPIO2 (PM8350B_SID << 8 | 0x0b)
+#define PM8350B_ADC5_GEN2_GPIO3 (PM8350B_SID << 8 | 0x0c)
+#define PM8350B_ADC5_GEN2_GPIO4 (PM8350B_SID << 8 | 0x0d)
+
+#define PM8350B_ADC5_GEN2_CHG_TEMP (PM8350B_SID << 8 | 0x10)
+#define PM8350B_ADC5_GEN2_USB_IN_V_16 (PM8350B_SID << 8 | 0x11)
+#define PM8350B_ADC5_GEN2_VDC_16 (PM8350B_SID << 8 | 0x12)
+#define PM8350B_ADC5_GEN2_CC1_ID (PM8350B_SID << 8 | 0x13)
+#define PM8350B_ADC5_GEN2_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15)
+#define PM8350B_ADC5_GEN2_IIN_FB (PM8350B_SID << 8 | 0x17)
+
+/* 30k pull-up1 */
+#define PM8350B_ADC5_GEN2_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24)
+#define PM8350B_ADC5_GEN2_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25)
+#define PM8350B_ADC5_GEN2_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26)
+#define PM8350B_ADC5_GEN2_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27)
+#define PM8350B_ADC5_GEN2_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28)
+#define PM8350B_ADC5_GEN2_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29)
+#define PM8350B_ADC5_GEN2_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a)
+#define PM8350B_ADC5_GEN2_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b)
+#define PM8350B_ADC5_GEN2_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c)
+#define PM8350B_ADC5_GEN2_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d)
+#define PM8350B_ADC5_GEN2_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33)
+
+/* 100k pull-up2 */
+#define PM8350B_ADC5_GEN2_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44)
+#define PM8350B_ADC5_GEN2_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45)
+#define PM8350B_ADC5_GEN2_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46)
+#define PM8350B_ADC5_GEN2_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47)
+#define PM8350B_ADC5_GEN2_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48)
+#define PM8350B_ADC5_GEN2_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49)
+#define PM8350B_ADC5_GEN2_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a)
+#define PM8350B_ADC5_GEN2_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b)
+#define PM8350B_ADC5_GEN2_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c)
+#define PM8350B_ADC5_GEN2_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d)
+#define PM8350B_ADC5_GEN2_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53)
+
+/* 400k pull-up3 */
+#define PM8350B_ADC5_GEN2_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64)
+#define PM8350B_ADC5_GEN2_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65)
+#define PM8350B_ADC5_GEN2_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66)
+#define PM8350B_ADC5_GEN2_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67)
+#define PM8350B_ADC5_GEN2_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68)
+#define PM8350B_ADC5_GEN2_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69)
+#define PM8350B_ADC5_GEN2_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a)
+#define PM8350B_ADC5_GEN2_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b)
+#define PM8350B_ADC5_GEN2_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c)
+#define PM8350B_ADC5_GEN2_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d)
+#define PM8350B_ADC5_GEN2_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73)
+
+/* 1/3 Divider */
+#define PM8350B_ADC5_GEN2_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a)
+#define PM8350B_ADC5_GEN2_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b)
+#define PM8350B_ADC5_GEN2_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c)
+#define PM8350B_ADC5_GEN2_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d)
+
+#define PM8350B_ADC5_GEN2_VPH_PWR (PM8350B_SID << 8 | 0x8e)
+#define PM8350B_ADC5_GEN2_VBAT_SNS (PM8350B_SID << 8 | 0x8f)
+
+#define PM8350B_ADC5_GEN2_SBUx (PM8350B_SID << 8 | 0x94)
+#define PM8350B_ADC5_GEN2_VBAT_2S_MID (PM8350B_SID << 8 | 0x96)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
new file mode 100644
index 000000000000..8de4ee86f875
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
+
+#ifndef PMK8350_SID
+#define PMK8350_SID 0
+#endif
+
+/* ADC channels for PMK8350_ADC for PMIC5 Gen2 */
+#define PMK8350_ADC5_GEN2_REF_GND (PMK8350_SID << 8 | 0x0)
+#define PMK8350_ADC5_GEN2_1P25VREF (PMK8350_SID << 8 | 0x01)
+#define PMK8350_ADC5_GEN2_VREF_VADC (PMK8350_SID << 8 | 0x02)
+#define PMK8350_ADC5_GEN2_DIE_TEMP (PMK8350_SID << 8 | 0x03)
+
+#define PMK8350_ADC5_GEN2_AMUX_THM1 (PMK8350_SID << 8 | 0x04)
+#define PMK8350_ADC5_GEN2_AMUX_THM2 (PMK8350_SID << 8 | 0x05)
+#define PMK8350_ADC5_GEN2_AMUX_THM3 (PMK8350_SID << 8 | 0x06)
+#define PMK8350_ADC5_GEN2_AMUX_THM4 (PMK8350_SID << 8 | 0x07)
+#define PMK8350_ADC5_GEN2_AMUX_THM5 (PMK8350_SID << 8 | 0x08)
+
+/* 30k pull-up1 */
+#define PMK8350_ADC5_GEN2_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24)
+#define PMK8350_ADC5_GEN2_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25)
+#define PMK8350_ADC5_GEN2_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26)
+#define PMK8350_ADC5_GEN2_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27)
+#define PMK8350_ADC5_GEN2_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28)
+
+/* 100k pull-up2 */
+#define PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44)
+#define PMK8350_ADC5_GEN2_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45)
+#define PMK8350_ADC5_GEN2_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46)
+#define PMK8350_ADC5_GEN2_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47)
+#define PMK8350_ADC5_GEN2_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48)
+
+/* 400k pull-up3 */
+#define PMK8350_ADC5_GEN2_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64)
+#define PMK8350_ADC5_GEN2_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65)
+#define PMK8350_ADC5_GEN2_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66)
+#define PMK8350_ADC5_GEN2_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67)
+#define PMK8350_ADC5_GEN2_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
new file mode 100644
index 000000000000..0f8ad745845b
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
+
+#ifndef PMR735A_SID
+#define PMR735A_SID 4
+#endif
+
+/* ADC channels for PMR735A_ADC for PMIC5 Gen2 */
+#define PMR735A_ADC5_GEN2_REF_GND (PMR735A_SID << 8 | 0x0)
+#define PMR735A_ADC5_GEN2_1P25VREF (PMR735A_SID << 8 | 0x01)
+#define PMR735A_ADC5_GEN2_VREF_VADC (PMR735A_SID << 8 | 0x02)
+#define PMR735A_ADC5_GEN2_DIE_TEMP (PMR735A_SID << 8 | 0x03)
+
+#define PMR735A_ADC5_GEN2_GPIO1 (PMR735A_SID << 8 | 0x0a)
+#define PMR735A_ADC5_GEN2_GPIO2 (PMR735A_SID << 8 | 0x0b)
+#define PMR735A_ADC5_GEN2_GPIO3 (PMR735A_SID << 8 | 0x0c)
+
+/* 100k pull-up2 */
+#define PMR735A_ADC5_GEN2_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a)
+#define PMR735A_ADC5_GEN2_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b)
+#define PMR735A_ADC5_GEN2_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
new file mode 100644
index 000000000000..d05d057276e3
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
+
+#ifndef PMR735B_SID
+#define PMR735B_SID 5
+#endif
+
+/* ADC channels for PMR735B_ADC for PMIC5 Gen2 */
+#define PMR735B_ADC5_GEN2_REF_GND (PMR735B_SID << 8 | 0x0)
+#define PMR735B_ADC5_GEN2_1P25VREF (PMR735B_SID << 8 | 0x01)
+#define PMR735B_ADC5_GEN2_VREF_VADC (PMR735B_SID << 8 | 0x02)
+#define PMR735B_ADC5_GEN2_DIE_TEMP (PMR735B_SID << 8 | 0x03)
+
+#define PMR735B_ADC5_GEN2_GPIO1 (PMR735B_SID << 8 | 0x0a)
+#define PMR735B_ADC5_GEN2_GPIO2 (PMR735B_SID << 8 | 0x0b)
+#define PMR735B_ADC5_GEN2_GPIO3 (PMR735B_SID << 8 | 0x0c)
+
+/* 100k pull-up2 */
+#define PMR735B_ADC5_GEN2_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a)
+#define PMR735B_ADC5_GEN2_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b)
+#define PMR735B_ADC5_GEN2_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
index 08adfe25964c..92a064ada796 100644
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -297,4 +298,80 @@
#define ADC7_SBUx 0x94
#define ADC7_VBAT_2S_MID 0x96
+/* ADC channels for ADC for PMIC5 Gen2 */
+
+#define ADC5_GEN2_REF_GND 0x00
+#define ADC5_GEN2_1P25VREF 0x01
+#define ADC5_GEN2_VREF_VADC 0x02
+#define ADC5_GEN2_DIE_TEMP 0x03
+
+#define ADC5_GEN2_AMUX_THM1 0x04
+#define ADC5_GEN2_AMUX_THM2 0x05
+#define ADC5_GEN2_AMUX_THM3 0x06
+#define ADC5_GEN2_AMUX_THM4 0x07
+#define ADC5_GEN2_AMUX_THM5 0x08
+#define ADC5_GEN2_AMUX_THM6 0x09
+#define ADC5_GEN2_GPIO1 0x0a
+#define ADC5_GEN2_GPIO2 0x0b
+#define ADC5_GEN2_GPIO3 0x0c
+#define ADC5_GEN2_GPIO4 0x0d
+
+#define ADC5_GEN2_CHG_TEMP 0x10
+#define ADC5_GEN2_USB_IN_V_16 0x11
+#define ADC5_GEN2_VDC_16 0x12
+#define ADC5_GEN2_CC1_ID 0x13
+#define ADC5_GEN2_VREF_BAT_THERM 0x15
+#define ADC5_GEN2_IIN_FB 0x17
+
+/* 30k pull-up1 */
+#define ADC5_GEN2_AMUX_THM1_30K_PU 0x24
+#define ADC5_GEN2_AMUX_THM2_30K_PU 0x25
+#define ADC5_GEN2_AMUX_THM3_30K_PU 0x26
+#define ADC5_GEN2_AMUX_THM4_30K_PU 0x27
+#define ADC5_GEN2_AMUX_THM5_30K_PU 0x28
+#define ADC5_GEN2_AMUX_THM6_30K_PU 0x29
+#define ADC5_GEN2_GPIO1_30K_PU 0x2a
+#define ADC5_GEN2_GPIO2_30K_PU 0x2b
+#define ADC5_GEN2_GPIO3_30K_PU 0x2c
+#define ADC5_GEN2_GPIO4_30K_PU 0x2d
+#define ADC5_GEN2_CC1_ID_30K_PU 0x33
+
+/* 100k pull-up2 */
+#define ADC5_GEN2_AMUX_THM1_100K_PU 0x44
+#define ADC5_GEN2_AMUX_THM2_100K_PU 0x45
+#define ADC5_GEN2_AMUX_THM3_100K_PU 0x46
+#define ADC5_GEN2_AMUX_THM4_100K_PU 0x47
+#define ADC5_GEN2_AMUX_THM5_100K_PU 0x48
+#define ADC5_GEN2_AMUX_THM6_100K_PU 0x49
+#define ADC5_GEN2_GPIO1_100K_PU 0x4a
+#define ADC5_GEN2_GPIO2_100K_PU 0x4b
+#define ADC5_GEN2_GPIO3_100K_PU 0x4c
+#define ADC5_GEN2_GPIO4_100K_PU 0x4d
+#define ADC5_GEN2_CC1_ID_100K_PU 0x53
+
+/* 400k pull-up3 */
+#define ADC5_GEN2_AMUX_THM1_400K_PU 0x64
+#define ADC5_GEN2_AMUX_THM2_400K_PU 0x65
+#define ADC5_GEN2_AMUX_THM3_400K_PU 0x66
+#define ADC5_GEN2_AMUX_THM4_400K_PU 0x67
+#define ADC5_GEN2_AMUX_THM5_400K_PU 0x68
+#define ADC5_GEN2_AMUX_THM6_400K_PU 0x69
+#define ADC5_GEN2_GPIO1_400K_PU 0x6a
+#define ADC5_GEN2_GPIO2_400K_PU 0x6b
+#define ADC5_GEN2_GPIO3_400K_PU 0x6c
+#define ADC5_GEN2_GPIO4_400K_PU 0x6d
+#define ADC5_GEN2_CC1_ID_400K_PU 0x73
+
+/* 1/3 Divider */
+#define ADC5_GEN2_GPIO1_DIV3 0x8a
+#define ADC5_GEN2_GPIO2_DIV3 0x8b
+#define ADC5_GEN2_GPIO3_DIV3 0x8c
+#define ADC5_GEN2_GPIO4_DIV3 0x8d
+
+#define ADC5_GEN2_VPH_PWR 0x8e
+#define ADC5_GEN2_VBAT_SNS 0x8f
+
+#define ADC5_GEN2_SBUx 0x94
+#define ADC5_GEN2_VBAT_2S_MID 0x96
+
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
--
2.25.1
The correct name for this version of ADCs should be ADC5 Gen2
instead of ADC7. Update the driver files for this name change.
Signed-off-by: Jishnu Prakash <[email protected]>
---
drivers/iio/adc/qcom-spmi-adc5.c | 93 +++++++++++++-----------
drivers/iio/adc/qcom-vadc-common.c | 36 ++++-----
include/linux/iio/adc/qcom-vadc-common.h | 12 +--
3 files changed, 73 insertions(+), 68 deletions(-)
diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c
index 0a4fd3a46113..3ac1ee500a67 100644
--- a/drivers/iio/adc/qcom-spmi-adc5.c
+++ b/drivers/iio/adc/qcom-spmi-adc5.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/bitops.h>
@@ -87,7 +88,7 @@
/* For PMIC7 */
#define ADC_APP_SID 0x40
#define ADC_APP_SID_MASK GENMASK(3, 0)
-#define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
+#define ADC5_GEN2_CONV_TIMEOUT msecs_to_jiffies(10)
enum adc5_cal_method {
ADC5_NO_CAL = 0,
@@ -270,7 +271,7 @@ static int adc5_configure(struct adc5_chip *adc,
return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
}
-static int adc7_configure(struct adc5_chip *adc,
+static int adc5_gen2_configure(struct adc5_chip *adc,
struct adc5_channel_prop *prop)
{
int ret;
@@ -352,7 +353,7 @@ static int adc5_do_conversion(struct adc5_chip *adc,
return ret;
}
-static int adc7_do_conversion(struct adc5_chip *adc,
+static int adc5_gen2_do_conversion(struct adc5_chip *adc,
struct adc5_channel_prop *prop,
struct iio_chan_spec const *chan,
u16 *data_volt, u16 *data_cur)
@@ -362,14 +363,14 @@ static int adc7_do_conversion(struct adc5_chip *adc,
mutex_lock(&adc->lock);
- ret = adc7_configure(adc, prop);
+ ret = adc5_gen2_configure(adc, prop);
if (ret) {
dev_err(adc->dev, "ADC configure failed with %d\n", ret);
goto unlock;
}
/* No support for polling mode at present */
- wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
+ wait_for_completion_timeout(&adc->complete, ADC5_GEN2_CONV_TIMEOUT);
ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
if (ret)
@@ -416,7 +417,7 @@ static int adc5_fwnode_xlate(struct iio_dev *indio_dev,
return -EINVAL;
}
-static int adc7_fwnode_xlate(struct iio_dev *indio_dev,
+static int adc5_gen2_fwnode_xlate(struct iio_dev *indio_dev,
const struct fwnode_reference_args *iiospec)
{
struct adc5_chip *adc = iio_priv(indio_dev);
@@ -471,12 +472,12 @@ static int adc5_read_raw(struct iio_dev *indio_dev,
mask, adc5_do_conversion);
}
-static int adc7_read_raw(struct iio_dev *indio_dev,
+static int adc5_gen2_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2,
long mask)
{
return adc_read_raw_common(indio_dev, chan, val, val2,
- mask, adc7_do_conversion);
+ mask, adc5_gen2_do_conversion);
}
static const struct iio_info adc5_info = {
@@ -484,9 +485,9 @@ static const struct iio_info adc5_info = {
.fwnode_xlate = adc5_fwnode_xlate,
};
-static const struct iio_info adc7_info = {
- .read_raw = adc7_read_raw,
- .fwnode_xlate = adc7_fwnode_xlate,
+static const struct iio_info adc5_gen2_info = {
+ .read_raw = adc5_gen2_read_raw,
+ .fwnode_xlate = adc5_gen2_fwnode_xlate,
};
struct adc5_channels {
@@ -561,37 +562,37 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
SCALE_HW_CALIB_THERM_100K_PULLUP)
};
-static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
- [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
+static const struct adc5_channels adc5_gen2_chans_pmic[ADC5_MAX_CHANNEL] = {
+ [ADC5_GEN2_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
SCALE_HW_CALIB_DEFAULT)
- [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
+ [ADC5_GEN2_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
SCALE_HW_CALIB_DEFAULT)
- [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
+ [ADC5_GEN2_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
SCALE_HW_CALIB_DEFAULT)
- [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
+ [ADC5_GEN2_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
SCALE_HW_CALIB_DEFAULT)
- [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
- SCALE_HW_CALIB_PMIC_THERM_PM7)
- [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
- [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
- SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN2_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
+ SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2)
+ [ADC5_GEN2_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
+ [ADC5_GEN2_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2)
};
static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
@@ -652,7 +653,7 @@ static int adc5_get_fw_channel_data(struct adc5_chip *adc,
/* virtual channel number = sid << 8 | channel number */
- if (adc->data->info == &adc7_info) {
+ if (adc->data->info == &adc5_gen2_info) {
sid = chan >> ADC_CHANNEL_OFFSET;
chan = chan & ADC_CHANNEL_MASK;
}
@@ -715,7 +716,7 @@ static int adc5_get_fw_channel_data(struct adc5_chip *adc,
/* Digital controller >= 5.3 have hw_settle_2 option */
if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
- adc->data->info == &adc7_info)
+ adc->data->info == &adc5_gen2_info)
ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2);
else
ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1);
@@ -774,10 +775,10 @@ static const struct adc5_data adc5_data_pmic = {
1, 2, 4, 8, 16, 32, 64, 128},
};
-static const struct adc5_data adc7_data_pmic = {
+static const struct adc5_data adc5_gen2_data_pmic = {
.full_scale_code_volt = 0x70e4,
- .adc_chans = adc7_chans_pmic,
- .info = &adc7_info,
+ .adc_chans = adc5_gen2_chans_pmic,
+ .info = &adc5_gen2_info,
.decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
{85, 340, 1360},
.hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
@@ -808,7 +809,11 @@ static const struct of_device_id adc5_match_table[] = {
},
{
.compatible = "qcom,spmi-adc7",
- .data = &adc7_data_pmic,
+ .data = &adc5_gen2_data_pmic,
+ },
+ {
+ .compatible = "qcom,spmi-adc5-gen2",
+ .data = &adc5_gen2_data_pmic,
},
{
.compatible = "qcom,spmi-adc-rev2",
diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c
index d5209f32adb3..1f4cd3be68fa 100644
--- a/drivers/iio/adc/qcom-vadc-common.c
+++ b/drivers/iio/adc/qcom-vadc-common.c
@@ -100,7 +100,7 @@ static const struct vadc_map_pt adcmap_100k_104ef_104fb_1875_vref[] = {
{ 46, 125000 },
};
-static const struct vadc_map_pt adcmap7_die_temp[] = {
+static const struct vadc_map_pt adcmap5_gen2_die_temp[] = {
{ 857300, 160000 },
{ 820100, 140000 },
{ 782500, 120000 },
@@ -118,7 +118,7 @@ static const struct vadc_map_pt adcmap7_die_temp[] = {
/*
* Resistance to temperature table for 100k pull up for NTCG104EF104.
*/
-static const struct vadc_map_pt adcmap7_100k[] = {
+static const struct vadc_map_pt adcmap5_gen2_100k[] = {
{ 4250657, -40960 },
{ 3962085, -39936 },
{ 3694875, -38912 },
@@ -309,7 +309,7 @@ static int qcom_vadc_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
-static int qcom_vadc7_scale_hw_calib_therm(
+static int qcom_vadc5_gen2_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
@@ -325,7 +325,7 @@ static int qcom_vadc_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
-static int qcom_vadc7_scale_hw_calib_die_temp(
+static int qcom_vadc5_gen2_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
@@ -334,11 +334,11 @@ static struct qcom_adc5_scale_type scale_adc5_fn[] = {
[SCALE_HW_CALIB_DEFAULT] = {qcom_vadc_scale_hw_calib_volt},
[SCALE_HW_CALIB_THERM_100K_PULLUP] = {qcom_vadc_scale_hw_calib_therm},
[SCALE_HW_CALIB_XOTHERM] = {qcom_vadc_scale_hw_calib_therm},
- [SCALE_HW_CALIB_THERM_100K_PU_PM7] = {
- qcom_vadc7_scale_hw_calib_therm},
+ [SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2] = {
+ qcom_vadc5_gen2_scale_hw_calib_therm},
[SCALE_HW_CALIB_PMIC_THERM] = {qcom_vadc_scale_hw_calib_die_temp},
- [SCALE_HW_CALIB_PMIC_THERM_PM7] = {
- qcom_vadc7_scale_hw_calib_die_temp},
+ [SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2] = {
+ qcom_vadc5_gen2_scale_hw_calib_die_temp},
[SCALE_HW_CALIB_PM5_CHG_TEMP] = {qcom_vadc_scale_hw_chg5_temp},
[SCALE_HW_CALIB_PM5_SMB_TEMP] = {qcom_vadc_scale_hw_smb_temp},
};
@@ -530,7 +530,7 @@ static int qcom_vadc_scale_code_voltage_factor(u16 adc_code,
return (int) voltage;
}
-static int qcom_vadc7_scale_hw_calib_therm(
+static int qcom_vadc5_gen2_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
@@ -538,15 +538,15 @@ static int qcom_vadc7_scale_hw_calib_therm(
s64 resistance = adc_code;
int ret, result;
- if (adc_code >= RATIO_MAX_ADC7)
+ if (adc_code >= RATIO_MAX_ADC5_GEN2)
return -EINVAL;
/* (ADC code * R_PULLUP (100Kohm)) / (full_scale_code - ADC code)*/
resistance *= R_PU_100K;
- resistance = div64_s64(resistance, RATIO_MAX_ADC7 - adc_code);
+ resistance = div64_s64(resistance, RATIO_MAX_ADC5_GEN2 - adc_code);
- ret = qcom_vadc_map_voltage_temp(adcmap7_100k,
- ARRAY_SIZE(adcmap7_100k),
+ ret = qcom_vadc_map_voltage_temp(adcmap5_gen2_100k,
+ ARRAY_SIZE(adcmap5_gen2_100k),
resistance, &result);
if (ret)
return ret;
@@ -595,7 +595,7 @@ static int qcom_vadc_scale_hw_calib_die_temp(
return 0;
}
-static int qcom_vadc7_scale_hw_calib_die_temp(
+static int qcom_vadc5_gen2_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
@@ -606,7 +606,7 @@ static int qcom_vadc7_scale_hw_calib_die_temp(
voltage = qcom_vadc_scale_code_voltage_factor(adc_code,
prescale, data, 1);
- return qcom_vadc_map_voltage_temp(adcmap7_die_temp, ARRAY_SIZE(adcmap7_die_temp),
+ return qcom_vadc_map_voltage_temp(adcmap5_gen2_die_temp, ARRAY_SIZE(adcmap5_gen2_die_temp),
voltage, result_mdec);
}
@@ -681,10 +681,10 @@ u16 qcom_adc_tm5_gen2_temp_res_scale(int temp)
{
int64_t resistance;
- resistance = qcom_vadc_map_temp_voltage(adcmap7_100k,
- ARRAY_SIZE(adcmap7_100k), temp);
+ resistance = qcom_vadc_map_temp_voltage(adcmap5_gen2_100k,
+ ARRAY_SIZE(adcmap5_gen2_100k), temp);
- return div64_s64(resistance * RATIO_MAX_ADC7, resistance + R_PU_100K);
+ return div64_s64(resistance * RATIO_MAX_ADC5_GEN2, resistance + R_PU_100K);
}
EXPORT_SYMBOL(qcom_adc_tm5_gen2_temp_res_scale);
diff --git a/include/linux/iio/adc/qcom-vadc-common.h b/include/linux/iio/adc/qcom-vadc-common.h
index aa21b032e861..a926e369a3ca 100644
--- a/include/linux/iio/adc/qcom-vadc-common.h
+++ b/include/linux/iio/adc/qcom-vadc-common.h
@@ -53,7 +53,7 @@
#define ADC5_USR_DATA_CHECK 0x8000
#define R_PU_100K 100000
-#define RATIO_MAX_ADC7 BIT(14)
+#define RATIO_MAX_ADC5_GEN2 BIT(14)
/*
* VADC_CALIB_ABSOLUTE: uses the 625mV and 1.25V as reference channels.
@@ -95,12 +95,12 @@ struct vadc_linear_graph {
* lookup table. The hardware applies offset/slope to adc code.
* SCALE_HW_CALIB_XOTHERM: Returns XO thermistor voltage in millidegC using
* 100k pullup. The hardware applies offset/slope to adc code.
- * SCALE_HW_CALIB_THERM_100K_PU_PM7: Returns temperature in millidegC using
- * lookup table for PMIC7. The hardware applies offset/slope to adc code.
+ * SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2: Returns temperature in millidegC using
+ * lookup table for PMIC5 Gen2. The hardware applies offset/slope to adc code.
* SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade.
* The hardware applies offset/slope to adc code.
* SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade.
- * The hardware applies offset/slope to adc code. This is for PMIC7.
+ * The hardware applies offset/slope to adc code. This is for PMIC5 Gen2.
* SCALE_HW_CALIB_PM5_CHG_TEMP: Returns result in millidegrees for PMIC5
* charger temperature.
* SCALE_HW_CALIB_PM5_SMB_TEMP: Returns result in millidegrees for PMIC5
@@ -115,9 +115,9 @@ enum vadc_scale_fn_type {
SCALE_HW_CALIB_DEFAULT,
SCALE_HW_CALIB_THERM_100K_PULLUP,
SCALE_HW_CALIB_XOTHERM,
- SCALE_HW_CALIB_THERM_100K_PU_PM7,
+ SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2,
SCALE_HW_CALIB_PMIC_THERM,
- SCALE_HW_CALIB_PMIC_THERM_PM7,
+ SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2,
SCALE_HW_CALIB_PM5_CHG_TEMP,
SCALE_HW_CALIB_PM5_SMB_TEMP,
SCALE_HW_CALIB_INVALID,
--
2.25.1
Now that usage of "ADC7" name has been replaced with usage of "ADC5
Gen2" name everywhere, remove all support for "ADC7" name.
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 5 +-
.../bindings/thermal/qcom-spmi-adc-tm5.yaml | 1 -
.../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 63 -------------
.../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 -------------------
.../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 ----------
.../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 ------
.../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 ------
include/dt-bindings/iio/qcom,spmi-vadc.h | 76 ----------------
8 files changed, 1 insertion(+), 334 deletions(-)
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index f886977de165..eb7d16e385ad 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -26,7 +26,6 @@ properties:
- qcom,spmi-vadc
- qcom,spmi-adc5
- qcom,spmi-adc-rev2
- - qcom,spmi-adc7
- qcom,spmi-adc5-gen2
reg:
@@ -214,9 +213,7 @@ allOf:
properties:
compatible:
contains:
- enum :
- - qcom,spmi-adc7
- - qcom,spmi-adc5-gen2
+ const: qcom,spmi-adc5-gen2
then:
patternProperties:
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
index 01d57f13d254..019f18a2b9e7 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -13,7 +13,6 @@ properties:
enum:
- qcom,spmi-adc-tm5
- qcom,spmi-adc-tm5-gen2
- - qcom,adc-tm7 # Incomplete / subject to change
reg:
maxItems: 1
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
deleted file mode 100644
index 09fd169ad18e..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
-
-/* ADC channels for PM8350_ADC for PMIC7 */
-#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | 0x0)
-#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | 0x01)
-#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | 0x02)
-#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | 0x03)
-
-#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | 0x04)
-#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | 0x05)
-#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | 0x06)
-#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | 0x07)
-#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | 0x08)
-#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | 0x0a)
-#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | 0x0b)
-#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | 0x0c)
-#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | 0x0d)
-
-/* 30k pull-up1 */
-#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24)
-#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25)
-#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26)
-#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27)
-#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28)
-#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a)
-#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b)
-#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c)
-#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d)
-
-/* 100k pull-up2 */
-#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44)
-#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45)
-#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46)
-#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47)
-#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48)
-#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a)
-#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b)
-#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c)
-#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d)
-
-/* 400k pull-up3 */
-#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64)
-#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65)
-#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66)
-#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67)
-#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68)
-#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a)
-#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b)
-#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c)
-#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d)
-
-/* 1/3 Divider */
-#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d)
-
-#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | 0x8e)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
deleted file mode 100644
index dc2497c27e16..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
-
-#ifndef PM8350B_SID
-#define PM8350B_SID 3
-#endif
-
-/* ADC channels for PM8350B_ADC for PMIC7 */
-#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0)
-#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01)
-#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02)
-#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03)
-
-#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04)
-#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05)
-#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06)
-#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07)
-#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08)
-#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09)
-#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a)
-#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b)
-#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c)
-#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d)
-
-#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10)
-#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11)
-#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12)
-#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13)
-#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15)
-#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17)
-
-/* 30k pull-up1 */
-#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24)
-#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25)
-#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26)
-#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27)
-#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28)
-#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29)
-#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a)
-#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b)
-#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c)
-#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d)
-#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33)
-
-/* 100k pull-up2 */
-#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44)
-#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45)
-#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46)
-#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47)
-#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48)
-#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49)
-#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a)
-#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b)
-#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c)
-#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d)
-#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53)
-
-/* 400k pull-up3 */
-#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64)
-#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65)
-#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66)
-#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67)
-#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68)
-#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69)
-#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a)
-#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b)
-#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c)
-#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d)
-#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73)
-
-/* 1/3 Divider */
-#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a)
-#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b)
-#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c)
-#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d)
-
-#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e)
-#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f)
-
-#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94)
-#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
deleted file mode 100644
index 6c296870e95b..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
-
-#ifndef PMK8350_SID
-#define PMK8350_SID 0
-#endif
-
-/* ADC channels for PMK8350_ADC for PMIC7 */
-#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0)
-#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01)
-#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02)
-#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03)
-
-#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04)
-#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05)
-#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06)
-#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07)
-#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08)
-
-/* 30k pull-up1 */
-#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24)
-#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25)
-#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26)
-#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27)
-#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28)
-
-/* 100k pull-up2 */
-#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44)
-#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45)
-#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46)
-#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47)
-#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48)
-
-/* 400k pull-up3 */
-#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64)
-#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65)
-#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66)
-#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67)
-#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
deleted file mode 100644
index d6df1b19e5ff..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
-
-#ifndef PMR735A_SID
-#define PMR735A_SID 4
-#endif
-
-/* ADC channels for PMR735A_ADC for PMIC7 */
-#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0)
-#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01)
-#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02)
-#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03)
-
-#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a)
-#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b)
-#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c)
-
-/* 100k pull-up2 */
-#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a)
-#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b)
-#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
deleted file mode 100644
index 8da0e7dab315..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
-
-#ifndef PMR735B_SID
-#define PMR735B_SID 5
-#endif
-
-/* ADC channels for PMR735B_ADC for PMIC7 */
-#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0)
-#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01)
-#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02)
-#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03)
-
-#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a)
-#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b)
-#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c)
-
-/* 100k pull-up2 */
-#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a)
-#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b)
-#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
index 92a064ada796..b1413c62ad27 100644
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -222,82 +222,6 @@
#define ADC5_MAX_CHANNEL 0xc0
-/* ADC channels for ADC for PMIC7 */
-
-#define ADC7_REF_GND 0x00
-#define ADC7_1P25VREF 0x01
-#define ADC7_VREF_VADC 0x02
-#define ADC7_DIE_TEMP 0x03
-
-#define ADC7_AMUX_THM1 0x04
-#define ADC7_AMUX_THM2 0x05
-#define ADC7_AMUX_THM3 0x06
-#define ADC7_AMUX_THM4 0x07
-#define ADC7_AMUX_THM5 0x08
-#define ADC7_AMUX_THM6 0x09
-#define ADC7_GPIO1 0x0a
-#define ADC7_GPIO2 0x0b
-#define ADC7_GPIO3 0x0c
-#define ADC7_GPIO4 0x0d
-
-#define ADC7_CHG_TEMP 0x10
-#define ADC7_USB_IN_V_16 0x11
-#define ADC7_VDC_16 0x12
-#define ADC7_CC1_ID 0x13
-#define ADC7_VREF_BAT_THERM 0x15
-#define ADC7_IIN_FB 0x17
-
-/* 30k pull-up1 */
-#define ADC7_AMUX_THM1_30K_PU 0x24
-#define ADC7_AMUX_THM2_30K_PU 0x25
-#define ADC7_AMUX_THM3_30K_PU 0x26
-#define ADC7_AMUX_THM4_30K_PU 0x27
-#define ADC7_AMUX_THM5_30K_PU 0x28
-#define ADC7_AMUX_THM6_30K_PU 0x29
-#define ADC7_GPIO1_30K_PU 0x2a
-#define ADC7_GPIO2_30K_PU 0x2b
-#define ADC7_GPIO3_30K_PU 0x2c
-#define ADC7_GPIO4_30K_PU 0x2d
-#define ADC7_CC1_ID_30K_PU 0x33
-
-/* 100k pull-up2 */
-#define ADC7_AMUX_THM1_100K_PU 0x44
-#define ADC7_AMUX_THM2_100K_PU 0x45
-#define ADC7_AMUX_THM3_100K_PU 0x46
-#define ADC7_AMUX_THM4_100K_PU 0x47
-#define ADC7_AMUX_THM5_100K_PU 0x48
-#define ADC7_AMUX_THM6_100K_PU 0x49
-#define ADC7_GPIO1_100K_PU 0x4a
-#define ADC7_GPIO2_100K_PU 0x4b
-#define ADC7_GPIO3_100K_PU 0x4c
-#define ADC7_GPIO4_100K_PU 0x4d
-#define ADC7_CC1_ID_100K_PU 0x53
-
-/* 400k pull-up3 */
-#define ADC7_AMUX_THM1_400K_PU 0x64
-#define ADC7_AMUX_THM2_400K_PU 0x65
-#define ADC7_AMUX_THM3_400K_PU 0x66
-#define ADC7_AMUX_THM4_400K_PU 0x67
-#define ADC7_AMUX_THM5_400K_PU 0x68
-#define ADC7_AMUX_THM6_400K_PU 0x69
-#define ADC7_GPIO1_400K_PU 0x6a
-#define ADC7_GPIO2_400K_PU 0x6b
-#define ADC7_GPIO3_400K_PU 0x6c
-#define ADC7_GPIO4_400K_PU 0x6d
-#define ADC7_CC1_ID_400K_PU 0x73
-
-/* 1/3 Divider */
-#define ADC7_GPIO1_DIV3 0x8a
-#define ADC7_GPIO2_DIV3 0x8b
-#define ADC7_GPIO3_DIV3 0x8c
-#define ADC7_GPIO4_DIV3 0x8d
-
-#define ADC7_VPH_PWR 0x8e
-#define ADC7_VBAT_SNS 0x8f
-
-#define ADC7_SBUx 0x94
-#define ADC7_VBAT_2S_MID 0x96
-
/* ADC channels for ADC for PMIC5 Gen2 */
#define ADC5_GEN2_REF_GND 0x00
--
2.25.1
Update ADC dt-bindings file paths in QCOM devicetree files to
match the dt-bindings change moving the files from 'iio' to
'iio/adc' folder.
Signed-off-by: Jishnu Prakash <[email protected]>
---
arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +-
24 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi
index 59092a551a16..f7f716dfcbd1 100644
--- a/arch/arm64/boot/dts/qcom/pm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index 2e6afa296141..673bbcd69538 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
index 6f7aa67501e2..d606520e05b7 100644
--- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi
index 4bc717917f44..e9cf14fef96d 100644
--- a/arch/arm64/boot/dts/qcom/pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2020, Konrad Dybcio
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi
index 87b71b7205b8..dfbe9bb0d25c 100644
--- a/arch/arm64/boot/dts/qcom/pm660l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2020, Konrad Dybcio
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
index daa6f1d30efa..f5d14bde5300 100644
--- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2022 Luca Weiss <[email protected]>
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index db90c55fa2cf..a2d0168f4a2c 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -7,7 +7,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
index 66752cc063d6..9cb9603180d9 100644
--- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -4,7 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
index cca45fad75ac..5a7cf8947dc4 100644
--- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
@@ -4,7 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 1ea8920ff369..91990a7175b1 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
index 5ec38b7e335a..e8d707edc4cd 100644
--- a/arch/arm64/boot/dts/qcom/pm8950.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2022, Marijn Suijten <[email protected]>
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi
index 2268daf27fa7..025e851a6d2c 100644
--- a/arch/arm64/boot/dts/qcom/pm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index 672094c8ca58..8d150358b6ac 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index 695d79116cde..34462b5172da 100644
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright 2018 Google LLC. */
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi
index 4eb79e0ce40a..09f7af85d39b 100644
--- a/arch/arm64/boot/dts/qcom/pmi632.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2023 Luca Weiss <[email protected]>
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
index 4891be3cd68a..ce6f79c14015 100644
--- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, AngeloGioacchino Del Regno <[email protected]>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
index ee1e428d3a6e..35838492ea99 100644
--- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
@@ -6,7 +6,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
index 580684411d74..76438b4cda14 100644
--- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
&spmi_bus {
pmic@0 {
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi
index 22edb47c6a84..2c87eae3d140 100644
--- a/arch/arm64/boot/dts/qcom/pms405.dtsi
+++ b/arch/arm64/boot/dts/qcom/pms405.dtsi
@@ -5,7 +5,7 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index bc65e6c6232f..e4afb554ba66 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -7,7 +7,7 @@
/dts-v1/;
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h>
#include "sc7280-idp.dtsi"
#include "pmr735a.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index da413694e230..ac8922a222e7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index ed26bff7432d..2abe5ce2af74 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -11,8 +11,8 @@
* Copyright 2022 Google LLC.
*/
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index cfd5dbbacdcb..dedfefd94a63 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -7,9 +7,9 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index 52119cc1250e..e9c06953a490 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -9,7 +9,7 @@
#define PMK8350_SID 6
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
--
2.25.1
At present, the QCOM ADC bindings files are located in the
dt-bindings/iio folder. As they are all specifically for
ADC, copy them into the dt-bindings/iio/adc folder.
Also update documentation to reflect the change in paths.
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 16 +-
.../bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +-
.../iio/adc/qcom,spmi-adc5-gen2-pm8350.h | 64 +++
.../iio/adc/qcom,spmi-adc5-gen2-pm8350b.h | 89 ++++
.../iio/adc/qcom,spmi-adc5-gen2-pmk8350.h | 47 +++
.../iio/adc/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++
.../iio/adc/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 48 +++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +
.../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 54 +++
include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 379 ++++++++++++++++++
12 files changed, 866 insertions(+), 11 deletions(-)
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-vadc.h
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index 090113e62d52..b6a545aae9d2 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -77,9 +77,9 @@ patternProperties:
maxItems: 1
description: |
ADC channel number.
- See include/dt-bindings/iio/qcom,spmi-vadc.h
+ See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per
- PMIC in the PMIC-specific files in include/dt-bindings/iio/.
+ PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
label:
$ref: /schemas/types.yaml#/definitions/string
@@ -293,8 +293,8 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
spmi {
@@ -325,10 +325,10 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
- #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
- #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
- #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h>
pmic {
#address-cells = <1>;
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
index 019f18a2b9e7..50a5308e3c6b 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -164,7 +164,7 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
spmi_bus {
#address-cells = <1>;
@@ -203,8 +203,8 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
spmi_bus {
#address-cells = <1>;
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h
new file mode 100644
index 000000000000..77259beaf6e9
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
+
+/* ADC channels for PM8350_ADC for PMIC5 Gen2 */
+#define PM8350_ADC5_GEN2_REF_GND(sid) ((sid) << 8 | 0x0)
+#define PM8350_ADC5_GEN2_1P25VREF(sid) ((sid) << 8 | 0x01)
+#define PM8350_ADC5_GEN2_VREF_VADC(sid) ((sid) << 8 | 0x02)
+#define PM8350_ADC5_GEN2_DIE_TEMP(sid) ((sid) << 8 | 0x03)
+
+#define PM8350_ADC5_GEN2_AMUX_THM1(sid) ((sid) << 8 | 0x04)
+#define PM8350_ADC5_GEN2_AMUX_THM2(sid) ((sid) << 8 | 0x05)
+#define PM8350_ADC5_GEN2_AMUX_THM3(sid) ((sid) << 8 | 0x06)
+#define PM8350_ADC5_GEN2_AMUX_THM4(sid) ((sid) << 8 | 0x07)
+#define PM8350_ADC5_GEN2_AMUX_THM5(sid) ((sid) << 8 | 0x08)
+#define PM8350_ADC5_GEN2_GPIO1(sid) ((sid) << 8 | 0x0a)
+#define PM8350_ADC5_GEN2_GPIO2(sid) ((sid) << 8 | 0x0b)
+#define PM8350_ADC5_GEN2_GPIO3(sid) ((sid) << 8 | 0x0c)
+#define PM8350_ADC5_GEN2_GPIO4(sid) ((sid) << 8 | 0x0d)
+
+/* 30k pull-up1 */
+#define PM8350_ADC5_GEN2_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24)
+#define PM8350_ADC5_GEN2_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25)
+#define PM8350_ADC5_GEN2_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26)
+#define PM8350_ADC5_GEN2_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27)
+#define PM8350_ADC5_GEN2_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28)
+#define PM8350_ADC5_GEN2_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a)
+#define PM8350_ADC5_GEN2_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b)
+#define PM8350_ADC5_GEN2_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c)
+#define PM8350_ADC5_GEN2_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d)
+
+/* 100k pull-up2 */
+#define PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44)
+#define PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45)
+#define PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46)
+#define PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47)
+#define PM8350_ADC5_GEN2_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48)
+#define PM8350_ADC5_GEN2_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a)
+#define PM8350_ADC5_GEN2_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b)
+#define PM8350_ADC5_GEN2_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c)
+#define PM8350_ADC5_GEN2_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d)
+
+/* 400k pull-up3 */
+#define PM8350_ADC5_GEN2_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64)
+#define PM8350_ADC5_GEN2_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65)
+#define PM8350_ADC5_GEN2_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66)
+#define PM8350_ADC5_GEN2_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67)
+#define PM8350_ADC5_GEN2_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68)
+#define PM8350_ADC5_GEN2_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a)
+#define PM8350_ADC5_GEN2_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b)
+#define PM8350_ADC5_GEN2_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c)
+#define PM8350_ADC5_GEN2_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d)
+
+/* 1/3 Divider */
+#define PM8350_ADC5_GEN2_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d)
+
+#define PM8350_ADC5_GEN2_VPH_PWR(sid) ((sid) << 8 | 0x8e)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h
new file mode 100644
index 000000000000..c7bb54e0b6a6
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
+
+#ifndef PM8350B_SID
+#define PM8350B_SID 3
+#endif
+
+/* ADC channels for PM8350B_ADC for PMIC5 Gen2 */
+#define PM8350B_ADC5_GEN2_REF_GND (PM8350B_SID << 8 | 0x0)
+#define PM8350B_ADC5_GEN2_1P25VREF (PM8350B_SID << 8 | 0x01)
+#define PM8350B_ADC5_GEN2_VREF_VADC (PM8350B_SID << 8 | 0x02)
+#define PM8350B_ADC5_GEN2_DIE_TEMP (PM8350B_SID << 8 | 0x03)
+
+#define PM8350B_ADC5_GEN2_AMUX_THM1 (PM8350B_SID << 8 | 0x04)
+#define PM8350B_ADC5_GEN2_AMUX_THM2 (PM8350B_SID << 8 | 0x05)
+#define PM8350B_ADC5_GEN2_AMUX_THM3 (PM8350B_SID << 8 | 0x06)
+#define PM8350B_ADC5_GEN2_AMUX_THM4 (PM8350B_SID << 8 | 0x07)
+#define PM8350B_ADC5_GEN2_AMUX_THM5 (PM8350B_SID << 8 | 0x08)
+#define PM8350B_ADC5_GEN2_AMUX_THM6 (PM8350B_SID << 8 | 0x09)
+#define PM8350B_ADC5_GEN2_GPIO1 (PM8350B_SID << 8 | 0x0a)
+#define PM8350B_ADC5_GEN2_GPIO2 (PM8350B_SID << 8 | 0x0b)
+#define PM8350B_ADC5_GEN2_GPIO3 (PM8350B_SID << 8 | 0x0c)
+#define PM8350B_ADC5_GEN2_GPIO4 (PM8350B_SID << 8 | 0x0d)
+
+#define PM8350B_ADC5_GEN2_CHG_TEMP (PM8350B_SID << 8 | 0x10)
+#define PM8350B_ADC5_GEN2_USB_IN_V_16 (PM8350B_SID << 8 | 0x11)
+#define PM8350B_ADC5_GEN2_VDC_16 (PM8350B_SID << 8 | 0x12)
+#define PM8350B_ADC5_GEN2_CC1_ID (PM8350B_SID << 8 | 0x13)
+#define PM8350B_ADC5_GEN2_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15)
+#define PM8350B_ADC5_GEN2_IIN_FB (PM8350B_SID << 8 | 0x17)
+
+/* 30k pull-up1 */
+#define PM8350B_ADC5_GEN2_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24)
+#define PM8350B_ADC5_GEN2_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25)
+#define PM8350B_ADC5_GEN2_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26)
+#define PM8350B_ADC5_GEN2_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27)
+#define PM8350B_ADC5_GEN2_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28)
+#define PM8350B_ADC5_GEN2_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29)
+#define PM8350B_ADC5_GEN2_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a)
+#define PM8350B_ADC5_GEN2_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b)
+#define PM8350B_ADC5_GEN2_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c)
+#define PM8350B_ADC5_GEN2_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d)
+#define PM8350B_ADC5_GEN2_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33)
+
+/* 100k pull-up2 */
+#define PM8350B_ADC5_GEN2_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44)
+#define PM8350B_ADC5_GEN2_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45)
+#define PM8350B_ADC5_GEN2_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46)
+#define PM8350B_ADC5_GEN2_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47)
+#define PM8350B_ADC5_GEN2_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48)
+#define PM8350B_ADC5_GEN2_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49)
+#define PM8350B_ADC5_GEN2_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a)
+#define PM8350B_ADC5_GEN2_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b)
+#define PM8350B_ADC5_GEN2_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c)
+#define PM8350B_ADC5_GEN2_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d)
+#define PM8350B_ADC5_GEN2_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53)
+
+/* 400k pull-up3 */
+#define PM8350B_ADC5_GEN2_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64)
+#define PM8350B_ADC5_GEN2_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65)
+#define PM8350B_ADC5_GEN2_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66)
+#define PM8350B_ADC5_GEN2_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67)
+#define PM8350B_ADC5_GEN2_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68)
+#define PM8350B_ADC5_GEN2_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69)
+#define PM8350B_ADC5_GEN2_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a)
+#define PM8350B_ADC5_GEN2_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b)
+#define PM8350B_ADC5_GEN2_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c)
+#define PM8350B_ADC5_GEN2_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d)
+#define PM8350B_ADC5_GEN2_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73)
+
+/* 1/3 Divider */
+#define PM8350B_ADC5_GEN2_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a)
+#define PM8350B_ADC5_GEN2_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b)
+#define PM8350B_ADC5_GEN2_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c)
+#define PM8350B_ADC5_GEN2_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d)
+
+#define PM8350B_ADC5_GEN2_VPH_PWR (PM8350B_SID << 8 | 0x8e)
+#define PM8350B_ADC5_GEN2_VBAT_SNS (PM8350B_SID << 8 | 0x8f)
+
+#define PM8350B_ADC5_GEN2_SBUx (PM8350B_SID << 8 | 0x94)
+#define PM8350B_ADC5_GEN2_VBAT_2S_MID (PM8350B_SID << 8 | 0x96)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h
new file mode 100644
index 000000000000..8de4ee86f875
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
+
+#ifndef PMK8350_SID
+#define PMK8350_SID 0
+#endif
+
+/* ADC channels for PMK8350_ADC for PMIC5 Gen2 */
+#define PMK8350_ADC5_GEN2_REF_GND (PMK8350_SID << 8 | 0x0)
+#define PMK8350_ADC5_GEN2_1P25VREF (PMK8350_SID << 8 | 0x01)
+#define PMK8350_ADC5_GEN2_VREF_VADC (PMK8350_SID << 8 | 0x02)
+#define PMK8350_ADC5_GEN2_DIE_TEMP (PMK8350_SID << 8 | 0x03)
+
+#define PMK8350_ADC5_GEN2_AMUX_THM1 (PMK8350_SID << 8 | 0x04)
+#define PMK8350_ADC5_GEN2_AMUX_THM2 (PMK8350_SID << 8 | 0x05)
+#define PMK8350_ADC5_GEN2_AMUX_THM3 (PMK8350_SID << 8 | 0x06)
+#define PMK8350_ADC5_GEN2_AMUX_THM4 (PMK8350_SID << 8 | 0x07)
+#define PMK8350_ADC5_GEN2_AMUX_THM5 (PMK8350_SID << 8 | 0x08)
+
+/* 30k pull-up1 */
+#define PMK8350_ADC5_GEN2_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24)
+#define PMK8350_ADC5_GEN2_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25)
+#define PMK8350_ADC5_GEN2_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26)
+#define PMK8350_ADC5_GEN2_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27)
+#define PMK8350_ADC5_GEN2_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28)
+
+/* 100k pull-up2 */
+#define PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44)
+#define PMK8350_ADC5_GEN2_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45)
+#define PMK8350_ADC5_GEN2_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46)
+#define PMK8350_ADC5_GEN2_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47)
+#define PMK8350_ADC5_GEN2_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48)
+
+/* 400k pull-up3 */
+#define PMK8350_ADC5_GEN2_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64)
+#define PMK8350_ADC5_GEN2_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65)
+#define PMK8350_ADC5_GEN2_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66)
+#define PMK8350_ADC5_GEN2_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67)
+#define PMK8350_ADC5_GEN2_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h
new file mode 100644
index 000000000000..0f8ad745845b
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
+
+#ifndef PMR735A_SID
+#define PMR735A_SID 4
+#endif
+
+/* ADC channels for PMR735A_ADC for PMIC5 Gen2 */
+#define PMR735A_ADC5_GEN2_REF_GND (PMR735A_SID << 8 | 0x0)
+#define PMR735A_ADC5_GEN2_1P25VREF (PMR735A_SID << 8 | 0x01)
+#define PMR735A_ADC5_GEN2_VREF_VADC (PMR735A_SID << 8 | 0x02)
+#define PMR735A_ADC5_GEN2_DIE_TEMP (PMR735A_SID << 8 | 0x03)
+
+#define PMR735A_ADC5_GEN2_GPIO1 (PMR735A_SID << 8 | 0x0a)
+#define PMR735A_ADC5_GEN2_GPIO2 (PMR735A_SID << 8 | 0x0b)
+#define PMR735A_ADC5_GEN2_GPIO3 (PMR735A_SID << 8 | 0x0c)
+
+/* 100k pull-up2 */
+#define PMR735A_ADC5_GEN2_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a)
+#define PMR735A_ADC5_GEN2_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b)
+#define PMR735A_ADC5_GEN2_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h
new file mode 100644
index 000000000000..d05d057276e3
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
+
+#ifndef PMR735B_SID
+#define PMR735B_SID 5
+#endif
+
+/* ADC channels for PMR735B_ADC for PMIC5 Gen2 */
+#define PMR735B_ADC5_GEN2_REF_GND (PMR735B_SID << 8 | 0x0)
+#define PMR735B_ADC5_GEN2_1P25VREF (PMR735B_SID << 8 | 0x01)
+#define PMR735B_ADC5_GEN2_VREF_VADC (PMR735B_SID << 8 | 0x02)
+#define PMR735B_ADC5_GEN2_DIE_TEMP (PMR735B_SID << 8 | 0x03)
+
+#define PMR735B_ADC5_GEN2_GPIO1 (PMR735B_SID << 8 | 0x0a)
+#define PMR735B_ADC5_GEN2_GPIO2 (PMR735B_SID << 8 | 0x0b)
+#define PMR735B_ADC5_GEN2_GPIO3 (PMR735B_SID << 8 | 0x0c)
+
+/* 100k pull-up2 */
+#define PMR735B_ADC5_GEN2_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a)
+#define PMR735B_ADC5_GEN2_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b)
+#define PMR735B_ADC5_GEN2_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
new file mode 100644
index 000000000000..74e6e2f6f9ed
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+
+#ifndef PM8550_SID
+#define PM8550_SID 1
+#endif
+
+/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
+#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
+#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
+#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
+#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
+
+#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04)
+#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05)
+#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06)
+#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07)
+#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d)
+
+/* 100k pull-up */
+#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44)
+#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45)
+#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46)
+#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47)
+#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d)
+
+/* 1/3 Divider */
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d)
+
+#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
new file mode 100644
index 000000000000..35483dfd970e
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+
+#ifndef PM8550B_SID
+#define PM8550B_SID 7
+#endif
+
+/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
+#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00)
+#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01)
+#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02)
+#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03)
+
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d)
+
+#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10)
+#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11)
+#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12)
+#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13)
+#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15)
+#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17)
+#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18)
+#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19)
+#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a)
+#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b)
+#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e)
+#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f)
+#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1)
+
+/* 30k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d)
+
+#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33)
+
+/* 100k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d)
+
+#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53)
+
+/* 400k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d)
+
+#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73)
+
+/* 1/3 Divider */
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c)
+
+#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
new file mode 100644
index 000000000000..337e13f7f56f
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+
+/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
+#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00)
+#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01)
+#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02)
+#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03)
+
+#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00)
+#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01)
+#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02)
+#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
new file mode 100644
index 000000000000..126fc16d5b20
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+
+#ifndef PMK8550_SID
+#define PMK8550_SID 0
+#endif
+
+/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
+#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00)
+#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01)
+#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02)
+#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03)
+
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a)
+
+/* 30k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a)
+
+/* 100k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a)
+
+/* 400k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
new file mode 100644
index 000000000000..ca5a0a947b3b
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
@@ -0,0 +1,379 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_H
+
+/* Voltage ADC channels */
+#define VADC_USBIN 0x00
+#define VADC_DCIN 0x01
+#define VADC_VCHG_SNS 0x02
+#define VADC_SPARE1_03 0x03
+#define VADC_USB_ID_MV 0x04
+#define VADC_VCOIN 0x05
+#define VADC_VBAT_SNS 0x06
+#define VADC_VSYS 0x07
+#define VADC_DIE_TEMP 0x08
+#define VADC_REF_625MV 0x09
+#define VADC_REF_1250MV 0x0a
+#define VADC_CHG_TEMP 0x0b
+#define VADC_SPARE1 0x0c
+#define VADC_SPARE2 0x0d
+#define VADC_GND_REF 0x0e
+#define VADC_VDD_VADC 0x0f
+
+#define VADC_P_MUX1_1_1 0x10
+#define VADC_P_MUX2_1_1 0x11
+#define VADC_P_MUX3_1_1 0x12
+#define VADC_P_MUX4_1_1 0x13
+#define VADC_P_MUX5_1_1 0x14
+#define VADC_P_MUX6_1_1 0x15
+#define VADC_P_MUX7_1_1 0x16
+#define VADC_P_MUX8_1_1 0x17
+#define VADC_P_MUX9_1_1 0x18
+#define VADC_P_MUX10_1_1 0x19
+#define VADC_P_MUX11_1_1 0x1a
+#define VADC_P_MUX12_1_1 0x1b
+#define VADC_P_MUX13_1_1 0x1c
+#define VADC_P_MUX14_1_1 0x1d
+#define VADC_P_MUX15_1_1 0x1e
+#define VADC_P_MUX16_1_1 0x1f
+
+#define VADC_P_MUX1_1_3 0x20
+#define VADC_P_MUX2_1_3 0x21
+#define VADC_P_MUX3_1_3 0x22
+#define VADC_P_MUX4_1_3 0x23
+#define VADC_P_MUX5_1_3 0x24
+#define VADC_P_MUX6_1_3 0x25
+#define VADC_P_MUX7_1_3 0x26
+#define VADC_P_MUX8_1_3 0x27
+#define VADC_P_MUX9_1_3 0x28
+#define VADC_P_MUX10_1_3 0x29
+#define VADC_P_MUX11_1_3 0x2a
+#define VADC_P_MUX12_1_3 0x2b
+#define VADC_P_MUX13_1_3 0x2c
+#define VADC_P_MUX14_1_3 0x2d
+#define VADC_P_MUX15_1_3 0x2e
+#define VADC_P_MUX16_1_3 0x2f
+
+#define VADC_LR_MUX1_BAT_THERM 0x30
+#define VADC_LR_MUX2_BAT_ID 0x31
+#define VADC_LR_MUX3_XO_THERM 0x32
+#define VADC_LR_MUX4_AMUX_THM1 0x33
+#define VADC_LR_MUX5_AMUX_THM2 0x34
+#define VADC_LR_MUX6_AMUX_THM3 0x35
+#define VADC_LR_MUX7_HW_ID 0x36
+#define VADC_LR_MUX8_AMUX_THM4 0x37
+#define VADC_LR_MUX9_AMUX_THM5 0x38
+#define VADC_LR_MUX10_USB_ID 0x39
+#define VADC_AMUX_PU1 0x3a
+#define VADC_AMUX_PU2 0x3b
+#define VADC_LR_MUX3_BUF_XO_THERM 0x3c
+
+#define VADC_LR_MUX1_PU1_BAT_THERM 0x70
+#define VADC_LR_MUX2_PU1_BAT_ID 0x71
+#define VADC_LR_MUX3_PU1_XO_THERM 0x72
+#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73
+#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74
+#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75
+#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76
+#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77
+#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78
+#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79
+#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c
+
+#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0
+#define VADC_LR_MUX2_PU2_BAT_ID 0xb1
+#define VADC_LR_MUX3_PU2_XO_THERM 0xb2
+#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3
+#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4
+#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5
+#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6
+#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7
+#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8
+#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9
+#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc
+
+#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0
+#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1
+#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2
+#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3
+#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4
+#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5
+#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6
+#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7
+#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8
+#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
+#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
+
+/* ADC channels for SPMI PMIC5 */
+
+#define ADC5_REF_GND 0x00
+#define ADC5_1P25VREF 0x01
+#define ADC5_VREF_VADC 0x02
+#define ADC5_VREF_VADC5_DIV_3 0x82
+#define ADC5_VPH_PWR 0x83
+#define ADC5_VBAT_SNS 0x84
+#define ADC5_VCOIN 0x85
+#define ADC5_DIE_TEMP 0x06
+#define ADC5_USB_IN_I 0x07
+#define ADC5_USB_IN_V_16 0x08
+#define ADC5_CHG_TEMP 0x09
+#define ADC5_BAT_THERM 0x0a
+#define ADC5_BAT_ID 0x0b
+#define ADC5_XO_THERM 0x0c
+#define ADC5_AMUX_THM1 0x0d
+#define ADC5_AMUX_THM2 0x0e
+#define ADC5_AMUX_THM3 0x0f
+#define ADC5_AMUX_THM4 0x10
+#define ADC5_AMUX_THM5 0x11
+#define ADC5_GPIO1 0x12
+#define ADC5_GPIO2 0x13
+#define ADC5_GPIO3 0x14
+#define ADC5_GPIO4 0x15
+#define ADC5_GPIO5 0x16
+#define ADC5_GPIO6 0x17
+#define ADC5_GPIO7 0x18
+#define ADC5_SBUx 0x99
+#define ADC5_MID_CHG_DIV6 0x1e
+#define ADC5_OFF 0xff
+
+/* 30k pull-up1 */
+#define ADC5_BAT_THERM_30K_PU 0x2a
+#define ADC5_BAT_ID_30K_PU 0x2b
+#define ADC5_XO_THERM_30K_PU 0x2c
+#define ADC5_AMUX_THM1_30K_PU 0x2d
+#define ADC5_AMUX_THM2_30K_PU 0x2e
+#define ADC5_AMUX_THM3_30K_PU 0x2f
+#define ADC5_AMUX_THM4_30K_PU 0x30
+#define ADC5_AMUX_THM5_30K_PU 0x31
+#define ADC5_GPIO1_30K_PU 0x32
+#define ADC5_GPIO2_30K_PU 0x33
+#define ADC5_GPIO3_30K_PU 0x34
+#define ADC5_GPIO4_30K_PU 0x35
+#define ADC5_GPIO5_30K_PU 0x36
+#define ADC5_GPIO6_30K_PU 0x37
+#define ADC5_GPIO7_30K_PU 0x38
+#define ADC5_SBUx_30K_PU 0x39
+
+/* 100k pull-up2 */
+#define ADC5_BAT_THERM_100K_PU 0x4a
+#define ADC5_BAT_ID_100K_PU 0x4b
+#define ADC5_XO_THERM_100K_PU 0x4c
+#define ADC5_AMUX_THM1_100K_PU 0x4d
+#define ADC5_AMUX_THM2_100K_PU 0x4e
+#define ADC5_AMUX_THM3_100K_PU 0x4f
+#define ADC5_AMUX_THM4_100K_PU 0x50
+#define ADC5_AMUX_THM5_100K_PU 0x51
+#define ADC5_GPIO1_100K_PU 0x52
+#define ADC5_GPIO2_100K_PU 0x53
+#define ADC5_GPIO3_100K_PU 0x54
+#define ADC5_GPIO4_100K_PU 0x55
+#define ADC5_GPIO5_100K_PU 0x56
+#define ADC5_GPIO6_100K_PU 0x57
+#define ADC5_GPIO7_100K_PU 0x58
+#define ADC5_SBUx_100K_PU 0x59
+
+/* 400k pull-up3 */
+#define ADC5_BAT_THERM_400K_PU 0x6a
+#define ADC5_BAT_ID_400K_PU 0x6b
+#define ADC5_XO_THERM_400K_PU 0x6c
+#define ADC5_AMUX_THM1_400K_PU 0x6d
+#define ADC5_AMUX_THM2_400K_PU 0x6e
+#define ADC5_AMUX_THM3_400K_PU 0x6f
+#define ADC5_AMUX_THM4_400K_PU 0x70
+#define ADC5_AMUX_THM5_400K_PU 0x71
+#define ADC5_GPIO1_400K_PU 0x72
+#define ADC5_GPIO2_400K_PU 0x73
+#define ADC5_GPIO3_400K_PU 0x74
+#define ADC5_GPIO4_400K_PU 0x75
+#define ADC5_GPIO5_400K_PU 0x76
+#define ADC5_GPIO6_400K_PU 0x77
+#define ADC5_GPIO7_400K_PU 0x78
+#define ADC5_SBUx_400K_PU 0x79
+
+/* 1/3 Divider */
+#define ADC5_GPIO1_DIV3 0x92
+#define ADC5_GPIO2_DIV3 0x93
+#define ADC5_GPIO3_DIV3 0x94
+#define ADC5_GPIO4_DIV3 0x95
+#define ADC5_GPIO5_DIV3 0x96
+#define ADC5_GPIO6_DIV3 0x97
+#define ADC5_GPIO7_DIV3 0x98
+#define ADC5_SBUx_DIV3 0x99
+
+/* Current and combined current/voltage channels */
+#define ADC5_INT_EXT_ISENSE 0xa1
+#define ADC5_PARALLEL_ISENSE 0xa5
+#define ADC5_CUR_REPLICA_VDS 0xa7
+#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
+#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
+#define ADC5_EXT_SENS_OFFSET 0xad
+
+#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
+#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
+#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
+#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
+#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
+#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
+
+#define ADC5_MAX_CHANNEL 0xc0
+
+/* ADC channels for ADC for PMIC5 Gen2 */
+
+#define ADC5_GEN2_REF_GND 0x00
+#define ADC5_GEN2_1P25VREF 0x01
+#define ADC5_GEN2_VREF_VADC 0x02
+#define ADC5_GEN2_DIE_TEMP 0x03
+
+#define ADC5_GEN2_AMUX_THM1 0x04
+#define ADC5_GEN2_AMUX_THM2 0x05
+#define ADC5_GEN2_AMUX_THM3 0x06
+#define ADC5_GEN2_AMUX_THM4 0x07
+#define ADC5_GEN2_AMUX_THM5 0x08
+#define ADC5_GEN2_AMUX_THM6 0x09
+#define ADC5_GEN2_GPIO1 0x0a
+#define ADC5_GEN2_GPIO2 0x0b
+#define ADC5_GEN2_GPIO3 0x0c
+#define ADC5_GEN2_GPIO4 0x0d
+
+#define ADC5_GEN2_CHG_TEMP 0x10
+#define ADC5_GEN2_USB_IN_V_16 0x11
+#define ADC5_GEN2_VDC_16 0x12
+#define ADC5_GEN2_CC1_ID 0x13
+#define ADC5_GEN2_VREF_BAT_THERM 0x15
+#define ADC5_GEN2_IIN_FB 0x17
+
+/* 30k pull-up1 */
+#define ADC5_GEN2_AMUX_THM1_30K_PU 0x24
+#define ADC5_GEN2_AMUX_THM2_30K_PU 0x25
+#define ADC5_GEN2_AMUX_THM3_30K_PU 0x26
+#define ADC5_GEN2_AMUX_THM4_30K_PU 0x27
+#define ADC5_GEN2_AMUX_THM5_30K_PU 0x28
+#define ADC5_GEN2_AMUX_THM6_30K_PU 0x29
+#define ADC5_GEN2_GPIO1_30K_PU 0x2a
+#define ADC5_GEN2_GPIO2_30K_PU 0x2b
+#define ADC5_GEN2_GPIO3_30K_PU 0x2c
+#define ADC5_GEN2_GPIO4_30K_PU 0x2d
+#define ADC5_GEN2_CC1_ID_30K_PU 0x33
+
+/* 100k pull-up2 */
+#define ADC5_GEN2_AMUX_THM1_100K_PU 0x44
+#define ADC5_GEN2_AMUX_THM2_100K_PU 0x45
+#define ADC5_GEN2_AMUX_THM3_100K_PU 0x46
+#define ADC5_GEN2_AMUX_THM4_100K_PU 0x47
+#define ADC5_GEN2_AMUX_THM5_100K_PU 0x48
+#define ADC5_GEN2_AMUX_THM6_100K_PU 0x49
+#define ADC5_GEN2_GPIO1_100K_PU 0x4a
+#define ADC5_GEN2_GPIO2_100K_PU 0x4b
+#define ADC5_GEN2_GPIO3_100K_PU 0x4c
+#define ADC5_GEN2_GPIO4_100K_PU 0x4d
+#define ADC5_GEN2_CC1_ID_100K_PU 0x53
+
+/* 400k pull-up3 */
+#define ADC5_GEN2_AMUX_THM1_400K_PU 0x64
+#define ADC5_GEN2_AMUX_THM2_400K_PU 0x65
+#define ADC5_GEN2_AMUX_THM3_400K_PU 0x66
+#define ADC5_GEN2_AMUX_THM4_400K_PU 0x67
+#define ADC5_GEN2_AMUX_THM5_400K_PU 0x68
+#define ADC5_GEN2_AMUX_THM6_400K_PU 0x69
+#define ADC5_GEN2_GPIO1_400K_PU 0x6a
+#define ADC5_GEN2_GPIO2_400K_PU 0x6b
+#define ADC5_GEN2_GPIO3_400K_PU 0x6c
+#define ADC5_GEN2_GPIO4_400K_PU 0x6d
+#define ADC5_GEN2_CC1_ID_400K_PU 0x73
+
+/* 1/3 Divider */
+#define ADC5_GEN2_GPIO1_DIV3 0x8a
+#define ADC5_GEN2_GPIO2_DIV3 0x8b
+#define ADC5_GEN2_GPIO3_DIV3 0x8c
+#define ADC5_GEN2_GPIO4_DIV3 0x8d
+
+#define ADC5_GEN2_VPH_PWR 0x8e
+#define ADC5_GEN2_VBAT_SNS 0x8f
+
+#define ADC5_GEN2_SBUx 0x94
+#define ADC5_GEN2_VBAT_2S_MID 0x96
+
+/* ADC channels for PMIC5 Gen3 */
+
+#define ADC5_GEN3_OFFSET_REF 0x00
+#define ADC5_GEN3_1P25VREF 0x01
+#define ADC5_GEN3_VREF_VADC 0x02
+#define ADC5_GEN3_DIE_TEMP 0x03
+
+#define ADC5_GEN3_AMUX1_THM 0x04
+#define ADC5_GEN3_AMUX2_THM 0x05
+#define ADC5_GEN3_AMUX3_THM 0x06
+#define ADC5_GEN3_AMUX4_THM 0x07
+#define ADC5_GEN3_AMUX5_THM 0x08
+#define ADC5_GEN3_AMUX6_THM 0x09
+#define ADC5_GEN3_AMUX1_GPIO 0x0a
+#define ADC5_GEN3_AMUX2_GPIO 0x0b
+#define ADC5_GEN3_AMUX3_GPIO 0x0c
+#define ADC5_GEN3_AMUX4_GPIO 0x0d
+
+#define ADC5_GEN3_CHG_TEMP 0x10
+#define ADC5_GEN3_USB_SNS_V_16 0x11
+#define ADC5_GEN3_VIN_DIV16_MUX 0x12
+#define ADC5_GEN3_VREF_BAT_THERM 0x15
+#define ADC5_GEN3_IIN_FB 0x17
+#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
+#define ADC5_GEN3_IIN_SMB 0x19
+#define ADC5_GEN3_ICHG_SMB 0x1b
+#define ADC5_GEN3_ICHG_FB 0xa1
+
+/* 30k pull-up1 */
+#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
+#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
+#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
+#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
+#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
+#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
+#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
+#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
+#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
+#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
+
+/* 100k pull-up2 */
+#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
+#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
+#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
+#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
+#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
+#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
+#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
+#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
+#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
+#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
+
+/* 400k pull-up3 */
+#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
+#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
+#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
+#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
+#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
+#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
+#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
+#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
+#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
+#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
+
+/* 1/3 Divider */
+#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
+#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
+#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
+
+#define ADC5_GEN3_VPH_PWR 0x8e
+#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
+
+#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
+#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
+#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
+
+#define ADC5_GEN3_OFFSET_EXT2 0xf8
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
--
2.25.1
Now that the ADC dt-binding paths have been updated everywhere
to use the files copied to the 'iio/adc' folder, remove them
from the 'iio' folder.
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 ---
.../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 ----
.../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 ---
.../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 --
.../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 --
.../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 ---
.../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 -----
.../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 -
.../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ---
include/dt-bindings/iio/qcom,spmi-vadc.h | 379 ------------------
10 files changed, 855 deletions(-)
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
delete mode 100644 include/dt-bindings/iio/qcom,spmi-vadc.h
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
deleted file mode 100644
index 77259beaf6e9..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
-
-/* ADC channels for PM8350_ADC for PMIC5 Gen2 */
-#define PM8350_ADC5_GEN2_REF_GND(sid) ((sid) << 8 | 0x0)
-#define PM8350_ADC5_GEN2_1P25VREF(sid) ((sid) << 8 | 0x01)
-#define PM8350_ADC5_GEN2_VREF_VADC(sid) ((sid) << 8 | 0x02)
-#define PM8350_ADC5_GEN2_DIE_TEMP(sid) ((sid) << 8 | 0x03)
-
-#define PM8350_ADC5_GEN2_AMUX_THM1(sid) ((sid) << 8 | 0x04)
-#define PM8350_ADC5_GEN2_AMUX_THM2(sid) ((sid) << 8 | 0x05)
-#define PM8350_ADC5_GEN2_AMUX_THM3(sid) ((sid) << 8 | 0x06)
-#define PM8350_ADC5_GEN2_AMUX_THM4(sid) ((sid) << 8 | 0x07)
-#define PM8350_ADC5_GEN2_AMUX_THM5(sid) ((sid) << 8 | 0x08)
-#define PM8350_ADC5_GEN2_GPIO1(sid) ((sid) << 8 | 0x0a)
-#define PM8350_ADC5_GEN2_GPIO2(sid) ((sid) << 8 | 0x0b)
-#define PM8350_ADC5_GEN2_GPIO3(sid) ((sid) << 8 | 0x0c)
-#define PM8350_ADC5_GEN2_GPIO4(sid) ((sid) << 8 | 0x0d)
-
-/* 30k pull-up1 */
-#define PM8350_ADC5_GEN2_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24)
-#define PM8350_ADC5_GEN2_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25)
-#define PM8350_ADC5_GEN2_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26)
-#define PM8350_ADC5_GEN2_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27)
-#define PM8350_ADC5_GEN2_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28)
-#define PM8350_ADC5_GEN2_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a)
-#define PM8350_ADC5_GEN2_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b)
-#define PM8350_ADC5_GEN2_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c)
-#define PM8350_ADC5_GEN2_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d)
-
-/* 100k pull-up2 */
-#define PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44)
-#define PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45)
-#define PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46)
-#define PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47)
-#define PM8350_ADC5_GEN2_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48)
-#define PM8350_ADC5_GEN2_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a)
-#define PM8350_ADC5_GEN2_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b)
-#define PM8350_ADC5_GEN2_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c)
-#define PM8350_ADC5_GEN2_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d)
-
-/* 400k pull-up3 */
-#define PM8350_ADC5_GEN2_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64)
-#define PM8350_ADC5_GEN2_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65)
-#define PM8350_ADC5_GEN2_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66)
-#define PM8350_ADC5_GEN2_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67)
-#define PM8350_ADC5_GEN2_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68)
-#define PM8350_ADC5_GEN2_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a)
-#define PM8350_ADC5_GEN2_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b)
-#define PM8350_ADC5_GEN2_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c)
-#define PM8350_ADC5_GEN2_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d)
-
-/* 1/3 Divider */
-#define PM8350_ADC5_GEN2_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d)
-
-#define PM8350_ADC5_GEN2_VPH_PWR(sid) ((sid) << 8 | 0x8e)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
deleted file mode 100644
index c7bb54e0b6a6..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H
-
-#ifndef PM8350B_SID
-#define PM8350B_SID 3
-#endif
-
-/* ADC channels for PM8350B_ADC for PMIC5 Gen2 */
-#define PM8350B_ADC5_GEN2_REF_GND (PM8350B_SID << 8 | 0x0)
-#define PM8350B_ADC5_GEN2_1P25VREF (PM8350B_SID << 8 | 0x01)
-#define PM8350B_ADC5_GEN2_VREF_VADC (PM8350B_SID << 8 | 0x02)
-#define PM8350B_ADC5_GEN2_DIE_TEMP (PM8350B_SID << 8 | 0x03)
-
-#define PM8350B_ADC5_GEN2_AMUX_THM1 (PM8350B_SID << 8 | 0x04)
-#define PM8350B_ADC5_GEN2_AMUX_THM2 (PM8350B_SID << 8 | 0x05)
-#define PM8350B_ADC5_GEN2_AMUX_THM3 (PM8350B_SID << 8 | 0x06)
-#define PM8350B_ADC5_GEN2_AMUX_THM4 (PM8350B_SID << 8 | 0x07)
-#define PM8350B_ADC5_GEN2_AMUX_THM5 (PM8350B_SID << 8 | 0x08)
-#define PM8350B_ADC5_GEN2_AMUX_THM6 (PM8350B_SID << 8 | 0x09)
-#define PM8350B_ADC5_GEN2_GPIO1 (PM8350B_SID << 8 | 0x0a)
-#define PM8350B_ADC5_GEN2_GPIO2 (PM8350B_SID << 8 | 0x0b)
-#define PM8350B_ADC5_GEN2_GPIO3 (PM8350B_SID << 8 | 0x0c)
-#define PM8350B_ADC5_GEN2_GPIO4 (PM8350B_SID << 8 | 0x0d)
-
-#define PM8350B_ADC5_GEN2_CHG_TEMP (PM8350B_SID << 8 | 0x10)
-#define PM8350B_ADC5_GEN2_USB_IN_V_16 (PM8350B_SID << 8 | 0x11)
-#define PM8350B_ADC5_GEN2_VDC_16 (PM8350B_SID << 8 | 0x12)
-#define PM8350B_ADC5_GEN2_CC1_ID (PM8350B_SID << 8 | 0x13)
-#define PM8350B_ADC5_GEN2_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15)
-#define PM8350B_ADC5_GEN2_IIN_FB (PM8350B_SID << 8 | 0x17)
-
-/* 30k pull-up1 */
-#define PM8350B_ADC5_GEN2_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24)
-#define PM8350B_ADC5_GEN2_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25)
-#define PM8350B_ADC5_GEN2_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26)
-#define PM8350B_ADC5_GEN2_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27)
-#define PM8350B_ADC5_GEN2_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28)
-#define PM8350B_ADC5_GEN2_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29)
-#define PM8350B_ADC5_GEN2_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a)
-#define PM8350B_ADC5_GEN2_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b)
-#define PM8350B_ADC5_GEN2_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c)
-#define PM8350B_ADC5_GEN2_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d)
-#define PM8350B_ADC5_GEN2_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33)
-
-/* 100k pull-up2 */
-#define PM8350B_ADC5_GEN2_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44)
-#define PM8350B_ADC5_GEN2_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45)
-#define PM8350B_ADC5_GEN2_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46)
-#define PM8350B_ADC5_GEN2_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47)
-#define PM8350B_ADC5_GEN2_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48)
-#define PM8350B_ADC5_GEN2_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49)
-#define PM8350B_ADC5_GEN2_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a)
-#define PM8350B_ADC5_GEN2_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b)
-#define PM8350B_ADC5_GEN2_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c)
-#define PM8350B_ADC5_GEN2_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d)
-#define PM8350B_ADC5_GEN2_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53)
-
-/* 400k pull-up3 */
-#define PM8350B_ADC5_GEN2_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64)
-#define PM8350B_ADC5_GEN2_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65)
-#define PM8350B_ADC5_GEN2_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66)
-#define PM8350B_ADC5_GEN2_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67)
-#define PM8350B_ADC5_GEN2_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68)
-#define PM8350B_ADC5_GEN2_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69)
-#define PM8350B_ADC5_GEN2_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a)
-#define PM8350B_ADC5_GEN2_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b)
-#define PM8350B_ADC5_GEN2_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c)
-#define PM8350B_ADC5_GEN2_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d)
-#define PM8350B_ADC5_GEN2_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73)
-
-/* 1/3 Divider */
-#define PM8350B_ADC5_GEN2_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a)
-#define PM8350B_ADC5_GEN2_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b)
-#define PM8350B_ADC5_GEN2_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c)
-#define PM8350B_ADC5_GEN2_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d)
-
-#define PM8350B_ADC5_GEN2_VPH_PWR (PM8350B_SID << 8 | 0x8e)
-#define PM8350B_ADC5_GEN2_VBAT_SNS (PM8350B_SID << 8 | 0x8f)
-
-#define PM8350B_ADC5_GEN2_SBUx (PM8350B_SID << 8 | 0x94)
-#define PM8350B_ADC5_GEN2_VBAT_2S_MID (PM8350B_SID << 8 | 0x96)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
deleted file mode 100644
index 8de4ee86f875..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H
-
-#ifndef PMK8350_SID
-#define PMK8350_SID 0
-#endif
-
-/* ADC channels for PMK8350_ADC for PMIC5 Gen2 */
-#define PMK8350_ADC5_GEN2_REF_GND (PMK8350_SID << 8 | 0x0)
-#define PMK8350_ADC5_GEN2_1P25VREF (PMK8350_SID << 8 | 0x01)
-#define PMK8350_ADC5_GEN2_VREF_VADC (PMK8350_SID << 8 | 0x02)
-#define PMK8350_ADC5_GEN2_DIE_TEMP (PMK8350_SID << 8 | 0x03)
-
-#define PMK8350_ADC5_GEN2_AMUX_THM1 (PMK8350_SID << 8 | 0x04)
-#define PMK8350_ADC5_GEN2_AMUX_THM2 (PMK8350_SID << 8 | 0x05)
-#define PMK8350_ADC5_GEN2_AMUX_THM3 (PMK8350_SID << 8 | 0x06)
-#define PMK8350_ADC5_GEN2_AMUX_THM4 (PMK8350_SID << 8 | 0x07)
-#define PMK8350_ADC5_GEN2_AMUX_THM5 (PMK8350_SID << 8 | 0x08)
-
-/* 30k pull-up1 */
-#define PMK8350_ADC5_GEN2_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24)
-#define PMK8350_ADC5_GEN2_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25)
-#define PMK8350_ADC5_GEN2_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26)
-#define PMK8350_ADC5_GEN2_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27)
-#define PMK8350_ADC5_GEN2_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28)
-
-/* 100k pull-up2 */
-#define PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44)
-#define PMK8350_ADC5_GEN2_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45)
-#define PMK8350_ADC5_GEN2_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46)
-#define PMK8350_ADC5_GEN2_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47)
-#define PMK8350_ADC5_GEN2_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48)
-
-/* 400k pull-up3 */
-#define PMK8350_ADC5_GEN2_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64)
-#define PMK8350_ADC5_GEN2_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65)
-#define PMK8350_ADC5_GEN2_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66)
-#define PMK8350_ADC5_GEN2_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67)
-#define PMK8350_ADC5_GEN2_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
deleted file mode 100644
index 0f8ad745845b..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H
-
-#ifndef PMR735A_SID
-#define PMR735A_SID 4
-#endif
-
-/* ADC channels for PMR735A_ADC for PMIC5 Gen2 */
-#define PMR735A_ADC5_GEN2_REF_GND (PMR735A_SID << 8 | 0x0)
-#define PMR735A_ADC5_GEN2_1P25VREF (PMR735A_SID << 8 | 0x01)
-#define PMR735A_ADC5_GEN2_VREF_VADC (PMR735A_SID << 8 | 0x02)
-#define PMR735A_ADC5_GEN2_DIE_TEMP (PMR735A_SID << 8 | 0x03)
-
-#define PMR735A_ADC5_GEN2_GPIO1 (PMR735A_SID << 8 | 0x0a)
-#define PMR735A_ADC5_GEN2_GPIO2 (PMR735A_SID << 8 | 0x0b)
-#define PMR735A_ADC5_GEN2_GPIO3 (PMR735A_SID << 8 | 0x0c)
-
-/* 100k pull-up2 */
-#define PMR735A_ADC5_GEN2_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a)
-#define PMR735A_ADC5_GEN2_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b)
-#define PMR735A_ADC5_GEN2_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
deleted file mode 100644
index d05d057276e3..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H
-
-#ifndef PMR735B_SID
-#define PMR735B_SID 5
-#endif
-
-/* ADC channels for PMR735B_ADC for PMIC5 Gen2 */
-#define PMR735B_ADC5_GEN2_REF_GND (PMR735B_SID << 8 | 0x0)
-#define PMR735B_ADC5_GEN2_1P25VREF (PMR735B_SID << 8 | 0x01)
-#define PMR735B_ADC5_GEN2_VREF_VADC (PMR735B_SID << 8 | 0x02)
-#define PMR735B_ADC5_GEN2_DIE_TEMP (PMR735B_SID << 8 | 0x03)
-
-#define PMR735B_ADC5_GEN2_GPIO1 (PMR735B_SID << 8 | 0x0a)
-#define PMR735B_ADC5_GEN2_GPIO2 (PMR735B_SID << 8 | 0x0b)
-#define PMR735B_ADC5_GEN2_GPIO3 (PMR735B_SID << 8 | 0x0c)
-
-/* 100k pull-up2 */
-#define PMR735B_ADC5_GEN2_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a)
-#define PMR735B_ADC5_GEN2_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b)
-#define PMR735B_ADC5_GEN2_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
deleted file mode 100644
index 74e6e2f6f9ed..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
-
-#ifndef PM8550_SID
-#define PM8550_SID 1
-#endif
-
-/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
-#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
-#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
-#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
-#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
-
-#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04)
-#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05)
-#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06)
-#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07)
-#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08)
-#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09)
-#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a)
-#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b)
-#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c)
-#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d)
-
-/* 100k pull-up */
-#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44)
-#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45)
-#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46)
-#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47)
-#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48)
-#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49)
-#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a)
-#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b)
-#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c)
-#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d)
-
-/* 1/3 Divider */
-#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c)
-#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d)
-
-#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
deleted file mode 100644
index 35483dfd970e..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
-
-#ifndef PM8550B_SID
-#define PM8550B_SID 7
-#endif
-
-/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
-#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00)
-#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01)
-#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02)
-#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03)
-
-#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04)
-#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05)
-#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06)
-#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07)
-#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08)
-#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09)
-#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a)
-#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b)
-#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c)
-#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d)
-
-#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10)
-#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11)
-#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12)
-#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13)
-#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15)
-#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17)
-#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18)
-#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19)
-#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a)
-#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b)
-#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e)
-#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f)
-#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1)
-
-/* 30k pull-up */
-#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24)
-#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25)
-#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26)
-#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27)
-#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28)
-#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29)
-#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a)
-#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b)
-#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c)
-#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d)
-
-#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33)
-
-/* 100k pull-up */
-#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44)
-#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45)
-#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46)
-#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47)
-#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48)
-#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49)
-#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a)
-#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b)
-#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c)
-#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d)
-
-#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53)
-
-/* 400k pull-up */
-#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64)
-#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65)
-#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66)
-#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67)
-#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68)
-#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69)
-#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a)
-#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b)
-#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c)
-#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d)
-
-#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73)
-
-/* 1/3 Divider */
-#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a)
-#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b)
-#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c)
-
-#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e)
-#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f)
-#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94)
-#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96)
-#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
deleted file mode 100644
index 337e13f7f56f..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
-
-/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
-#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00)
-#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01)
-#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02)
-#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03)
-
-#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00)
-#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01)
-#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02)
-#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
deleted file mode 100644
index 126fc16d5b20..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
-
-#ifndef PMK8550_SID
-#define PMK8550_SID 0
-#endif
-
-/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
-#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00)
-#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01)
-#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02)
-#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03)
-
-#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04)
-#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05)
-#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06)
-#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07)
-#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08)
-#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09)
-#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a)
-
-/* 30k pull-up */
-#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24)
-#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25)
-#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26)
-#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27)
-#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28)
-#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29)
-#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a)
-
-/* 100k pull-up */
-#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44)
-#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45)
-#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46)
-#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47)
-#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48)
-#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49)
-#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a)
-
-/* 400k pull-up */
-#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64)
-#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65)
-#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66)
-#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67)
-#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68)
-#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69)
-#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a)
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
deleted file mode 100644
index ca5a0a947b3b..000000000000
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_H
-
-/* Voltage ADC channels */
-#define VADC_USBIN 0x00
-#define VADC_DCIN 0x01
-#define VADC_VCHG_SNS 0x02
-#define VADC_SPARE1_03 0x03
-#define VADC_USB_ID_MV 0x04
-#define VADC_VCOIN 0x05
-#define VADC_VBAT_SNS 0x06
-#define VADC_VSYS 0x07
-#define VADC_DIE_TEMP 0x08
-#define VADC_REF_625MV 0x09
-#define VADC_REF_1250MV 0x0a
-#define VADC_CHG_TEMP 0x0b
-#define VADC_SPARE1 0x0c
-#define VADC_SPARE2 0x0d
-#define VADC_GND_REF 0x0e
-#define VADC_VDD_VADC 0x0f
-
-#define VADC_P_MUX1_1_1 0x10
-#define VADC_P_MUX2_1_1 0x11
-#define VADC_P_MUX3_1_1 0x12
-#define VADC_P_MUX4_1_1 0x13
-#define VADC_P_MUX5_1_1 0x14
-#define VADC_P_MUX6_1_1 0x15
-#define VADC_P_MUX7_1_1 0x16
-#define VADC_P_MUX8_1_1 0x17
-#define VADC_P_MUX9_1_1 0x18
-#define VADC_P_MUX10_1_1 0x19
-#define VADC_P_MUX11_1_1 0x1a
-#define VADC_P_MUX12_1_1 0x1b
-#define VADC_P_MUX13_1_1 0x1c
-#define VADC_P_MUX14_1_1 0x1d
-#define VADC_P_MUX15_1_1 0x1e
-#define VADC_P_MUX16_1_1 0x1f
-
-#define VADC_P_MUX1_1_3 0x20
-#define VADC_P_MUX2_1_3 0x21
-#define VADC_P_MUX3_1_3 0x22
-#define VADC_P_MUX4_1_3 0x23
-#define VADC_P_MUX5_1_3 0x24
-#define VADC_P_MUX6_1_3 0x25
-#define VADC_P_MUX7_1_3 0x26
-#define VADC_P_MUX8_1_3 0x27
-#define VADC_P_MUX9_1_3 0x28
-#define VADC_P_MUX10_1_3 0x29
-#define VADC_P_MUX11_1_3 0x2a
-#define VADC_P_MUX12_1_3 0x2b
-#define VADC_P_MUX13_1_3 0x2c
-#define VADC_P_MUX14_1_3 0x2d
-#define VADC_P_MUX15_1_3 0x2e
-#define VADC_P_MUX16_1_3 0x2f
-
-#define VADC_LR_MUX1_BAT_THERM 0x30
-#define VADC_LR_MUX2_BAT_ID 0x31
-#define VADC_LR_MUX3_XO_THERM 0x32
-#define VADC_LR_MUX4_AMUX_THM1 0x33
-#define VADC_LR_MUX5_AMUX_THM2 0x34
-#define VADC_LR_MUX6_AMUX_THM3 0x35
-#define VADC_LR_MUX7_HW_ID 0x36
-#define VADC_LR_MUX8_AMUX_THM4 0x37
-#define VADC_LR_MUX9_AMUX_THM5 0x38
-#define VADC_LR_MUX10_USB_ID 0x39
-#define VADC_AMUX_PU1 0x3a
-#define VADC_AMUX_PU2 0x3b
-#define VADC_LR_MUX3_BUF_XO_THERM 0x3c
-
-#define VADC_LR_MUX1_PU1_BAT_THERM 0x70
-#define VADC_LR_MUX2_PU1_BAT_ID 0x71
-#define VADC_LR_MUX3_PU1_XO_THERM 0x72
-#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73
-#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74
-#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75
-#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76
-#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77
-#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78
-#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79
-#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c
-
-#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0
-#define VADC_LR_MUX2_PU2_BAT_ID 0xb1
-#define VADC_LR_MUX3_PU2_XO_THERM 0xb2
-#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3
-#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4
-#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5
-#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6
-#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7
-#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8
-#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9
-#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc
-
-#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0
-#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1
-#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2
-#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3
-#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4
-#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5
-#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6
-#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7
-#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8
-#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
-#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
-
-/* ADC channels for SPMI PMIC5 */
-
-#define ADC5_REF_GND 0x00
-#define ADC5_1P25VREF 0x01
-#define ADC5_VREF_VADC 0x02
-#define ADC5_VREF_VADC5_DIV_3 0x82
-#define ADC5_VPH_PWR 0x83
-#define ADC5_VBAT_SNS 0x84
-#define ADC5_VCOIN 0x85
-#define ADC5_DIE_TEMP 0x06
-#define ADC5_USB_IN_I 0x07
-#define ADC5_USB_IN_V_16 0x08
-#define ADC5_CHG_TEMP 0x09
-#define ADC5_BAT_THERM 0x0a
-#define ADC5_BAT_ID 0x0b
-#define ADC5_XO_THERM 0x0c
-#define ADC5_AMUX_THM1 0x0d
-#define ADC5_AMUX_THM2 0x0e
-#define ADC5_AMUX_THM3 0x0f
-#define ADC5_AMUX_THM4 0x10
-#define ADC5_AMUX_THM5 0x11
-#define ADC5_GPIO1 0x12
-#define ADC5_GPIO2 0x13
-#define ADC5_GPIO3 0x14
-#define ADC5_GPIO4 0x15
-#define ADC5_GPIO5 0x16
-#define ADC5_GPIO6 0x17
-#define ADC5_GPIO7 0x18
-#define ADC5_SBUx 0x99
-#define ADC5_MID_CHG_DIV6 0x1e
-#define ADC5_OFF 0xff
-
-/* 30k pull-up1 */
-#define ADC5_BAT_THERM_30K_PU 0x2a
-#define ADC5_BAT_ID_30K_PU 0x2b
-#define ADC5_XO_THERM_30K_PU 0x2c
-#define ADC5_AMUX_THM1_30K_PU 0x2d
-#define ADC5_AMUX_THM2_30K_PU 0x2e
-#define ADC5_AMUX_THM3_30K_PU 0x2f
-#define ADC5_AMUX_THM4_30K_PU 0x30
-#define ADC5_AMUX_THM5_30K_PU 0x31
-#define ADC5_GPIO1_30K_PU 0x32
-#define ADC5_GPIO2_30K_PU 0x33
-#define ADC5_GPIO3_30K_PU 0x34
-#define ADC5_GPIO4_30K_PU 0x35
-#define ADC5_GPIO5_30K_PU 0x36
-#define ADC5_GPIO6_30K_PU 0x37
-#define ADC5_GPIO7_30K_PU 0x38
-#define ADC5_SBUx_30K_PU 0x39
-
-/* 100k pull-up2 */
-#define ADC5_BAT_THERM_100K_PU 0x4a
-#define ADC5_BAT_ID_100K_PU 0x4b
-#define ADC5_XO_THERM_100K_PU 0x4c
-#define ADC5_AMUX_THM1_100K_PU 0x4d
-#define ADC5_AMUX_THM2_100K_PU 0x4e
-#define ADC5_AMUX_THM3_100K_PU 0x4f
-#define ADC5_AMUX_THM4_100K_PU 0x50
-#define ADC5_AMUX_THM5_100K_PU 0x51
-#define ADC5_GPIO1_100K_PU 0x52
-#define ADC5_GPIO2_100K_PU 0x53
-#define ADC5_GPIO3_100K_PU 0x54
-#define ADC5_GPIO4_100K_PU 0x55
-#define ADC5_GPIO5_100K_PU 0x56
-#define ADC5_GPIO6_100K_PU 0x57
-#define ADC5_GPIO7_100K_PU 0x58
-#define ADC5_SBUx_100K_PU 0x59
-
-/* 400k pull-up3 */
-#define ADC5_BAT_THERM_400K_PU 0x6a
-#define ADC5_BAT_ID_400K_PU 0x6b
-#define ADC5_XO_THERM_400K_PU 0x6c
-#define ADC5_AMUX_THM1_400K_PU 0x6d
-#define ADC5_AMUX_THM2_400K_PU 0x6e
-#define ADC5_AMUX_THM3_400K_PU 0x6f
-#define ADC5_AMUX_THM4_400K_PU 0x70
-#define ADC5_AMUX_THM5_400K_PU 0x71
-#define ADC5_GPIO1_400K_PU 0x72
-#define ADC5_GPIO2_400K_PU 0x73
-#define ADC5_GPIO3_400K_PU 0x74
-#define ADC5_GPIO4_400K_PU 0x75
-#define ADC5_GPIO5_400K_PU 0x76
-#define ADC5_GPIO6_400K_PU 0x77
-#define ADC5_GPIO7_400K_PU 0x78
-#define ADC5_SBUx_400K_PU 0x79
-
-/* 1/3 Divider */
-#define ADC5_GPIO1_DIV3 0x92
-#define ADC5_GPIO2_DIV3 0x93
-#define ADC5_GPIO3_DIV3 0x94
-#define ADC5_GPIO4_DIV3 0x95
-#define ADC5_GPIO5_DIV3 0x96
-#define ADC5_GPIO6_DIV3 0x97
-#define ADC5_GPIO7_DIV3 0x98
-#define ADC5_SBUx_DIV3 0x99
-
-/* Current and combined current/voltage channels */
-#define ADC5_INT_EXT_ISENSE 0xa1
-#define ADC5_PARALLEL_ISENSE 0xa5
-#define ADC5_CUR_REPLICA_VDS 0xa7
-#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
-#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
-#define ADC5_EXT_SENS_OFFSET 0xad
-
-#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
-#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
-#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
-#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
-#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
-#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
-
-#define ADC5_MAX_CHANNEL 0xc0
-
-/* ADC channels for ADC for PMIC5 Gen2 */
-
-#define ADC5_GEN2_REF_GND 0x00
-#define ADC5_GEN2_1P25VREF 0x01
-#define ADC5_GEN2_VREF_VADC 0x02
-#define ADC5_GEN2_DIE_TEMP 0x03
-
-#define ADC5_GEN2_AMUX_THM1 0x04
-#define ADC5_GEN2_AMUX_THM2 0x05
-#define ADC5_GEN2_AMUX_THM3 0x06
-#define ADC5_GEN2_AMUX_THM4 0x07
-#define ADC5_GEN2_AMUX_THM5 0x08
-#define ADC5_GEN2_AMUX_THM6 0x09
-#define ADC5_GEN2_GPIO1 0x0a
-#define ADC5_GEN2_GPIO2 0x0b
-#define ADC5_GEN2_GPIO3 0x0c
-#define ADC5_GEN2_GPIO4 0x0d
-
-#define ADC5_GEN2_CHG_TEMP 0x10
-#define ADC5_GEN2_USB_IN_V_16 0x11
-#define ADC5_GEN2_VDC_16 0x12
-#define ADC5_GEN2_CC1_ID 0x13
-#define ADC5_GEN2_VREF_BAT_THERM 0x15
-#define ADC5_GEN2_IIN_FB 0x17
-
-/* 30k pull-up1 */
-#define ADC5_GEN2_AMUX_THM1_30K_PU 0x24
-#define ADC5_GEN2_AMUX_THM2_30K_PU 0x25
-#define ADC5_GEN2_AMUX_THM3_30K_PU 0x26
-#define ADC5_GEN2_AMUX_THM4_30K_PU 0x27
-#define ADC5_GEN2_AMUX_THM5_30K_PU 0x28
-#define ADC5_GEN2_AMUX_THM6_30K_PU 0x29
-#define ADC5_GEN2_GPIO1_30K_PU 0x2a
-#define ADC5_GEN2_GPIO2_30K_PU 0x2b
-#define ADC5_GEN2_GPIO3_30K_PU 0x2c
-#define ADC5_GEN2_GPIO4_30K_PU 0x2d
-#define ADC5_GEN2_CC1_ID_30K_PU 0x33
-
-/* 100k pull-up2 */
-#define ADC5_GEN2_AMUX_THM1_100K_PU 0x44
-#define ADC5_GEN2_AMUX_THM2_100K_PU 0x45
-#define ADC5_GEN2_AMUX_THM3_100K_PU 0x46
-#define ADC5_GEN2_AMUX_THM4_100K_PU 0x47
-#define ADC5_GEN2_AMUX_THM5_100K_PU 0x48
-#define ADC5_GEN2_AMUX_THM6_100K_PU 0x49
-#define ADC5_GEN2_GPIO1_100K_PU 0x4a
-#define ADC5_GEN2_GPIO2_100K_PU 0x4b
-#define ADC5_GEN2_GPIO3_100K_PU 0x4c
-#define ADC5_GEN2_GPIO4_100K_PU 0x4d
-#define ADC5_GEN2_CC1_ID_100K_PU 0x53
-
-/* 400k pull-up3 */
-#define ADC5_GEN2_AMUX_THM1_400K_PU 0x64
-#define ADC5_GEN2_AMUX_THM2_400K_PU 0x65
-#define ADC5_GEN2_AMUX_THM3_400K_PU 0x66
-#define ADC5_GEN2_AMUX_THM4_400K_PU 0x67
-#define ADC5_GEN2_AMUX_THM5_400K_PU 0x68
-#define ADC5_GEN2_AMUX_THM6_400K_PU 0x69
-#define ADC5_GEN2_GPIO1_400K_PU 0x6a
-#define ADC5_GEN2_GPIO2_400K_PU 0x6b
-#define ADC5_GEN2_GPIO3_400K_PU 0x6c
-#define ADC5_GEN2_GPIO4_400K_PU 0x6d
-#define ADC5_GEN2_CC1_ID_400K_PU 0x73
-
-/* 1/3 Divider */
-#define ADC5_GEN2_GPIO1_DIV3 0x8a
-#define ADC5_GEN2_GPIO2_DIV3 0x8b
-#define ADC5_GEN2_GPIO3_DIV3 0x8c
-#define ADC5_GEN2_GPIO4_DIV3 0x8d
-
-#define ADC5_GEN2_VPH_PWR 0x8e
-#define ADC5_GEN2_VBAT_SNS 0x8f
-
-#define ADC5_GEN2_SBUx 0x94
-#define ADC5_GEN2_VBAT_2S_MID 0x96
-
-/* ADC channels for PMIC5 Gen3 */
-
-#define ADC5_GEN3_OFFSET_REF 0x00
-#define ADC5_GEN3_1P25VREF 0x01
-#define ADC5_GEN3_VREF_VADC 0x02
-#define ADC5_GEN3_DIE_TEMP 0x03
-
-#define ADC5_GEN3_AMUX1_THM 0x04
-#define ADC5_GEN3_AMUX2_THM 0x05
-#define ADC5_GEN3_AMUX3_THM 0x06
-#define ADC5_GEN3_AMUX4_THM 0x07
-#define ADC5_GEN3_AMUX5_THM 0x08
-#define ADC5_GEN3_AMUX6_THM 0x09
-#define ADC5_GEN3_AMUX1_GPIO 0x0a
-#define ADC5_GEN3_AMUX2_GPIO 0x0b
-#define ADC5_GEN3_AMUX3_GPIO 0x0c
-#define ADC5_GEN3_AMUX4_GPIO 0x0d
-
-#define ADC5_GEN3_CHG_TEMP 0x10
-#define ADC5_GEN3_USB_SNS_V_16 0x11
-#define ADC5_GEN3_VIN_DIV16_MUX 0x12
-#define ADC5_GEN3_VREF_BAT_THERM 0x15
-#define ADC5_GEN3_IIN_FB 0x17
-#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
-#define ADC5_GEN3_IIN_SMB 0x19
-#define ADC5_GEN3_ICHG_SMB 0x1b
-#define ADC5_GEN3_ICHG_FB 0xa1
-
-/* 30k pull-up1 */
-#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
-#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
-#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
-#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
-#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
-#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
-#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
-#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
-#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
-#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
-
-/* 100k pull-up2 */
-#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
-#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
-#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
-#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
-#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
-#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
-#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
-#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
-#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
-#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
-
-/* 400k pull-up3 */
-#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
-#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
-#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
-#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
-#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
-#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
-#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
-#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
-#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
-#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
-
-/* 1/3 Divider */
-#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
-#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
-#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
-
-#define ADC5_GEN3_VPH_PWR 0x8e
-#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
-
-#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
-#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
-#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
-
-#define ADC5_GEN3_OFFSET_EXT2 0xf8
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
--
2.25.1
On Sat, 8 Jul 2023 12:58:25 +0530
Jishnu Prakash <[email protected]> wrote:
> The name used initially for this version of Qualcomm Technologies, Inc.
> PMIC ADC was ADC7, following the convention of calling the PMIC generation
> PMIC7. However, the names were later amended internally to ADC5 Gen2 and
> PMIC5 Gen2. In addition, the latest PMIC generation now is known as
> PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more
> sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7.
> Since this affects ADC devices across some PMICs, update the names accordingly.
>
> In order to avoid breaking the existing implementations of ADC7, add
> support for ADC5 Gen2 first now and remove the ADC7 support in a later
> patch.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
Hi Jishnu.
Whilst I can appreciate why you've picked this particular approach to
deal with the renames I'm not sure it's the smoothest path - or the
easiest to review.
If doing a single patch for the complete rename was too much, perhaps
doing one header (or if it makes sense set of headers)
at a time would be easier to read? With a final patch doing the compatible
addition. Maybe let's see what other reviewers think though.
A few other comments inline,
Jonathan
> ---
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 21 +++--
> .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 16 ++--
> .../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 +++++++++++++
> .../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 +++++++++++++++++++
> .../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 ++++++++++
> .../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++++++
> .../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++++++
> include/dt-bindings/iio/qcom,spmi-vadc.h | 77 ++++++++++++++++
> 8 files changed, 354 insertions(+), 17 deletions(-)
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> index ad7d6fc49de5..f886977de165 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> @@ -13,7 +13,7 @@ maintainers:
> description: |
> SPMI PMIC voltage ADC (VADC) provides interface to clients to read
> voltage. The VADC is a 15-bit sigma-delta ADC.
> - SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read
> + SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read
> voltage. The VADC is a 16-bit sigma-delta ADC.
>
> properties:
> @@ -27,6 +27,7 @@ properties:
> - qcom,spmi-adc5
> - qcom,spmi-adc-rev2
> - qcom,spmi-adc7
> + - qcom,spmi-adc5-gen2
Alphabetical order (roughly given currently list). So I'd stick
this after qcom,spmi-adc5
>
> reg:
> description: VADC base address in the SPMI PMIC register map
> @@ -71,7 +72,7 @@ patternProperties:
> description: |
> ADC channel number.
> See include/dt-bindings/iio/qcom,spmi-vadc.h
> - For PMIC7 ADC, the channel numbers are specified separately per PMIC
> + For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
> in the PMIC-specific files in include/dt-bindings/iio/.
>
> label:
> @@ -114,7 +115,7 @@ patternProperties:
> channel calibration. If property is not found, channel will be
> calibrated with 0.625V and 1.25V reference channels, also
> known as absolute calibration.
> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
> "qcom,spmi-adc-rev2", if this property is specified VADC will use
> the VDD reference (1.875V) and GND for channel calibration. If
> property is not found, channel will be calibrated with 0V and 1.25V
> @@ -213,7 +214,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: qcom,spmi-adc7
> + enum :
> + - qcom,spmi-adc7
There is a deprecated marking for dt-bindings. Might be good to use it here.
> + - qcom,spmi-adc5-gen2
>
> then:
> patternProperties:
> @@ -277,8 +280,8 @@ examples:
> };
>U>;
> + io-channels = <&pmk8350_vadc PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>;
> qcom,decimation = <340>;
> qcom,ratiometric;
> qcom,hw-settle-time-us = <200>;
> @@ -251,7 +251,7 @@ examples:
>
> conn-therm@1 {
> reg = <1>;
> - io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
> + io-channels = <&pmk8350_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
> qcom,avg-samples = <2>;
> qcom,ratiometric;
> qcom,hw-settle-time-us = <200>;
On Sat, 8 Jul 2023 12:58:28 +0530
Jishnu Prakash <[email protected]> wrote:
> Now that usage of "ADC7" name has been replaced with usage of "ADC5
> Gen2" name everywhere, remove all support for "ADC7" name.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 5 +-
> .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 1 -
> .../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 63 -------------
> .../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 -------------------
> .../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 ----------
> .../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 ------
> .../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 ------
> include/dt-bindings/iio/qcom,spmi-vadc.h | 76 ----------------
> 8 files changed, 1 insertion(+), 334 deletions(-)
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> index f886977de165..eb7d16e385ad 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> @@ -26,7 +26,6 @@ properties:
> - qcom,spmi-vadc
> - qcom,spmi-adc5
> - qcom,spmi-adc-rev2
> - - qcom,spmi-adc7
> - qcom,spmi-adc5-gen2
>
> reg:
> @@ -214,9 +213,7 @@ allOf:
> properties:
> compatible:
> contains:
> - enum :
> - - qcom,spmi-adc7
> - - qcom,spmi-adc5-gen2
> + const: qcom,spmi-adc5-gen2
>
> then:
> patternProperties:
Hmm. Definitely can't drop support (as per comment on next patch).
I think you should just mark it deprecated rather than remove it here but maybe
you can drop it. Let's see what DT binding maintainers say.
Jonathan
On Sat, 8 Jul 2023 12:58:29 +0530
Jishnu Prakash <[email protected]> wrote:
> Now that usage of "ADC7" name has been replaced with usage of "ADC5
> Gen2" name everywhere, remove the "qcom,spmi-adc7" compatible string.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
Nope. Unless all your dts files are distributed with the kernel, dropping
this breaks anyone who upgrades the kernel against an older firmware...
So even after the rename, you need to keep the deprecated naming around for
the binding side of things.
Jonathan
> ---
> drivers/iio/adc/qcom-spmi-adc5.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c
> index 3ac1ee500a67..6cebeaa69a75 100644
> --- a/drivers/iio/adc/qcom-spmi-adc5.c
> +++ b/drivers/iio/adc/qcom-spmi-adc5.c
> @@ -807,10 +807,6 @@ static const struct of_device_id adc5_match_table[] = {
> .compatible = "qcom,spmi-adc5",
> .data = &adc5_data_pmic,
> },
> - {
> - .compatible = "qcom,spmi-adc7",
> - .data = &adc5_gen2_data_pmic,
> - },
> {
> .compatible = "qcom,spmi-adc5-gen2",
> .data = &adc5_gen2_data_pmic,
On Sat, 8 Jul 2023 12:58:30 +0530
Jishnu Prakash <[email protected]> wrote:
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS firmware through a single register interface. This
> interface is implemented on an SDAM peripheral on the master PMIC PMK8550
> rather than a dedicated ADC peripheral.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++--
> .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++
> .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++
> .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++
> .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++
> include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++
> 6 files changed, 402 insertions(+), 12 deletions(-)
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> index eb7d16e385ad..090113e62d52 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> @@ -13,8 +13,8 @@ maintainers:
> description: |
> SPMI PMIC voltage ADC (VADC) provides interface to clients to read
> voltage. The VADC is a 15-bit sigma-delta ADC.
> - SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read
> - voltage. The VADC is a 16-bit sigma-delta ADC.
> + SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to
> + clients to read voltage. The VADC is a 16-bit sigma-delta ADC.
>
> properties:
> compatible:
> @@ -27,10 +27,11 @@ properties:
> - qcom,spmi-adc5
> - qcom,spmi-adc-rev2
> - qcom,spmi-adc5-gen2
> + - qcom,spmi-adc5-gen3
>
> reg:
> description: VADC base address in the SPMI PMIC register map
> - maxItems: 1
> + minItems: 1
?
>
> '#address-cells':
> const: 1
> @@ -38,6 +39,12 @@ properties:
> '#size-cells':
> const: 0
>
> + "#thermal-sensor-cells":
> + const: 1
> + description:
> + Number of cells required to uniquely identify the thermal sensors. Since
> + we have multiple sensors this is set to 1.
> +
Defined only for the new gen3? If so make make it false for the other devices.
> '#io-channel-cells':
> const: 1
>
> @@ -71,8 +78,8 @@ patternProperties:
> description: |
> ADC channel number.
> See include/dt-bindings/iio/qcom,spmi-vadc.h
> - For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
> - in the PMIC-specific files in include/dt-bindings/iio/.
> + For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per
> + PMIC in the PMIC-specific files in include/dt-bindings/iio/.
>
> label:
> $ref: /schemas/types.yaml#/definitions/string
> @@ -114,11 +121,12 @@ patternProperties:
> channel calibration. If property is not found, channel will be
> calibrated with 0.625V and 1.25V reference channels, also
> known as absolute calibration.
> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
> - "qcom,spmi-adc-rev2", if this property is specified VADC will use
> - the VDD reference (1.875V) and GND for channel calibration. If
> - property is not found, channel will be calibrated with 0V and 1.25V
> - reference channels, also known as absolute calibration.
> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2",
> + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property
> + is specified VADC will use the VDD reference (1.875V) and GND for
> + channel calibration. If property is not found, channel will be
> + calibrated with 0V and 1.25V reference channels, also known as
> + absolute calibration.
> type: boolean
>
> qcom,hw-settle-time:
> @@ -136,6 +144,12 @@ patternProperties:
> from the ADC that is an average of multiple samples. The value
> selected is 2^(value).
>
> + qcom,adc-tm-type:
> + description: |
> + Indicates if ADC_TM monitoring is done on this channel.
> + Defined for compatible property "qcom,spmi-adc5-gen3".
> + type: boolean
Enforce that in the binding, not via a comment. Once the binding
performs that check (set it to false for non matching compatibles) then
there is no need to also mention it in text.
> +
> required:
> - reg
>
> @@ -213,7 +227,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: qcom,spmi-adc5-gen2
> + enum:
> + - qcom,spmi-adc5-gen2
> + - qcom,spmi-adc5-gen3
Side note - it's fine to have a single element enum, so you could
use that option to reduce churn in this set...
>
> then:
> patternProperties:
> @@ -299,7 +315,7 @@ examples:
> label = "xo_therm";
> };
>
> - channel@47 {
> + channel@147 {
? If that's a valid change, then it looks like a separate fix.
> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
> qcom,ratiometric;
> qcom,hw-settle-time = <200>;
> @@ -307,3 +323,80 @@ examples:
> };
> };
> };
> +
> + - |
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
> +
> + pmic {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VADC node */
> + pmk8550_vadc: vadc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>;
> + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + #thermal-sensor-cells = <1>;
> +
> + /* PMK8550 Channel nodes */
> + channel@3 {
> + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pmk8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@44 {
> + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
> + label = "pmk8550_xo_therm";
> + qcom,pre-scaling = <1 1>;
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,adc-tm-type;
> + };
> +
> + /* PM8550 Channel nodes */
> + channel@103 {
> + reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pm8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@18e {
> + reg = <PM8550_ADC5_GEN3_VPH_PWR>;
> + label = "pm8550_vph_pwr";
> + qcom,pre-scaling = <1 3>;
> + };
> +
> + /* PM8550B Channel nodes */
> + channel@703 {
> + reg = <PM8550B_ADC5_GEN3_DIE_TEMP>;
> + label = "pm8550b_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@78e {
> + reg = <PM8550B_ADC5_GEN3_VPH_PWR>;
> + label = "pm8550b_vph_pwr";
> + qcom,pre-scaling = <1 3>;
> + };
> +
> + channel@78f {
> + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
> + label = "pm8550b_vbat_sns_qbg";
> + qcom,pre-scaling = <1 3>;
> + };
> +
> + /* PM8550VS_C Channel nodes */
> + channel@203 {
> + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
> + label = "pm8550vs_c_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> + };
> + };
> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
> new file mode 100644
> index 000000000000..74e6e2f6f9ed
> --- /dev/null
> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +
> +#ifndef PM8550_SID
> +#define PM8550_SID 1
> +#endif
> +
> +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
> +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
can we do the naming for the 0x00 as per Dmitry's set? That is get them from
qcom,spmi-vadc.h
https://patchwork.kernel.org/project/linux-iio/patch/[email protected]/
> +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
> +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
> +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
> +
> diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
> index b1413c62ad27..ca5a0a947b3b 100644
> --- a/include/dt-bindings/iio/qcom,spmi-vadc.h
> +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
> @@ -298,4 +298,82 @@
> #define ADC5_GEN2_SBUx 0x94
> #define ADC5_GEN2_VBAT_2S_MID 0x96
>
> +/* ADC channels for PMIC5 Gen3 */
> +
> +#define ADC5_GEN3_OFFSET_REF 0x00
> +#define ADC5_GEN3_1P25VREF 0x01
> +#define ADC5_GEN3_VREF_VADC 0x02
> +#define ADC5_GEN3_DIE_TEMP 0x03
On Sat, 8 Jul 2023 12:58:24 +0530
Jishnu Prakash <[email protected]> wrote:
> PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2,
> with all SW communication to ADC going through PMK8550 which
> communicates with other PMICs through PBS. The major difference is
> that the register interface used here is that of an SDAM present on
> PMK8550, rather than a dedicated ADC peripheral. There may be more than one
> SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may
> be used for either immediate reads (same functionality as previous PMIC5 and
> PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5
> Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality
> combined into the same driver.
>
> Patches 1-5 update the name of the previous generation of PMIC5 ADC peripherals
> from ADC7 to ADC5 Gen2, as this is the correct name and it makes more sense now
> to update it, with the addition of the latest ADC5 Gen3 peripheral support.
>
> Patches 6 and 7 add bindings and driver support respectively for ADC5 Gen3.
>
> Patches 8-11 are for an additional change, where the QCOM ADC dt-bindings files
> are moved from dt-bindings/iio to dt-bindings/iio/adc folder, as they are
> specifically for ADC devices.
>
This crossed with Dmitry's set...
https://patchwork.kernel.org/project/linux-iio/patch/[email protected]/
which changes a bunch of the includes you are going to rename.
I don't mind which order these land (if both go forward) so will leave
it up to the two of you to figure that out and tell me ;)
Jonathan
> > properties:
> > compatible:
> > @@ -27,10 +27,11 @@ properties:
> > - qcom,spmi-adc5
> > - qcom,spmi-adc-rev2
> > - qcom,spmi-adc5-gen2
> > + - qcom,spmi-adc5-gen3
> >
> > reg:
> > description: VADC base address in the SPMI PMIC register map
> > - maxItems: 1
> > + minItems: 1
>
> ?
Found it now. This needs documentation that it's providing multiple
base addresses for gen3. Also needs to only apply that to gen3...
On 08/07/2023 09:28, Jishnu Prakash wrote:
> Now that usage of "ADC7" name has been replaced with usage of "ADC5
> Gen2" name everywhere, remove all support for "ADC7" name.
Why?
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 5 +-
> .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 1 -
> .../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 63 -------------
> .../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 -------------------
> .../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 ----------
> .../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 ------
> .../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 ------
> include/dt-bindings/iio/qcom,spmi-vadc.h | 76 ----------------
> 8 files changed, 1 insertion(+), 334 deletions(-)
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
> delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> index f886977de165..eb7d16e385ad 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> @@ -26,7 +26,6 @@ properties:
> - qcom,spmi-vadc
> - qcom,spmi-adc5
> - qcom,spmi-adc-rev2
> - - qcom,spmi-adc7
NAK. You did not explained why dropping existing compatible is correct,
expected and okay.
Also:
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> The name used initially for this version of Qualcomm Technologies, Inc.
> PMIC ADC was ADC7, following the convention of calling the PMIC generation
> PMIC7. However, the names were later amended internally to ADC5 Gen2 and
> PMIC5 Gen2. In addition, the latest PMIC generation now is known as
> PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more
> sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7.
> Since this affects ADC devices across some PMICs, update the names accordingly.
>
> In order to avoid breaking the existing implementations of ADC7, add
> support for ADC5 Gen2 first now and remove the ADC7 support in a later
> patch.
I don't understand and I do not see it explained, why do you remove
ADC7. The patch is also doing way too many things at the same time...
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 21 +++--
> .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 16 ++--
> .../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 +++++++++++++
> .../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 +++++++++++++++++++
> .../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 ++++++++++
> .../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++++++
> .../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++++++
> include/dt-bindings/iio/qcom,spmi-vadc.h | 77 ++++++++++++++++
Bindings are always separate patches. If this is commit for bindings, then:
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS firmware through a single register interface. This
> interface is implemented on an SDAM peripheral on the master PMIC PMK8550
> rather than a dedicated ADC peripheral.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++--
> .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++
> .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++
> .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++
> .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++
> include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++
> 6 files changed, 402 insertions(+), 12 deletions(-)
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
> create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> index eb7d16e385ad..090113e62d52 100644
> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
> @@ -13,8 +13,8 @@ maintainers:
> description: |
> SPMI PMIC voltage ADC (VADC) provides interface to clients to read
> voltage. The VADC is a 15-bit sigma-delta ADC.
> - SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read
> - voltage. The VADC is a 16-bit sigma-delta ADC.
> + SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to
> + clients to read voltage. The VADC is a 16-bit sigma-delta ADC.
>
> properties:
> compatible:
> @@ -27,10 +27,11 @@ properties:
> - qcom,spmi-adc5
> - qcom,spmi-adc-rev2
> - qcom,spmi-adc5-gen2
> + - qcom,spmi-adc5-gen3
This could be ordered...
>
> reg:
> description: VADC base address in the SPMI PMIC register map
> - maxItems: 1
> + minItems: 1
Why? This does not make any sense. With previous patches it looks like
random set of changes.
>
> '#address-cells':
> const: 1
> @@ -38,6 +39,12 @@ properties:
> '#size-cells':
> const: 0
>
> + "#thermal-sensor-cells":
> + const: 1
> + description:
> + Number of cells required to uniquely identify the thermal sensors. Since
> + we have multiple sensors this is set to 1.
> +
> '#io-channel-cells':
> const: 1
>
> @@ -71,8 +78,8 @@ patternProperties:
> description: |
> ADC channel number.
> See include/dt-bindings/iio/qcom,spmi-vadc.h
> - For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
> - in the PMIC-specific files in include/dt-bindings/iio/.
> + For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per
> + PMIC in the PMIC-specific files in include/dt-bindings/iio/.
>
> label:
> $ref: /schemas/types.yaml#/definitions/string
> @@ -114,11 +121,12 @@ patternProperties:
> channel calibration. If property is not found, channel will be
> calibrated with 0.625V and 1.25V reference channels, also
> known as absolute calibration.
> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
> - "qcom,spmi-adc-rev2", if this property is specified VADC will use
> - the VDD reference (1.875V) and GND for channel calibration. If
> - property is not found, channel will be calibrated with 0V and 1.25V
> - reference channels, also known as absolute calibration.
> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2",
> + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property
> + is specified VADC will use the VDD reference (1.875V) and GND for
> + channel calibration. If property is not found, channel will be
> + calibrated with 0V and 1.25V reference channels, also known as
> + absolute calibration.
> type: boolean
>
> qcom,hw-settle-time:
> @@ -136,6 +144,12 @@ patternProperties:
> from the ADC that is an average of multiple samples. The value
> selected is 2^(value).
>
> + qcom,adc-tm-type:
> + description: |
> + Indicates if ADC_TM monitoring is done on this channel.
Description does not match property name.
> + Defined for compatible property "qcom,spmi-adc5-gen3".
Then you need if:then:.
> + type: boolean
> +
> required:
> - reg
>
> @@ -213,7 +227,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: qcom,spmi-adc5-gen2
> + enum:
> + - qcom,spmi-adc5-gen2
> + - qcom,spmi-adc5-gen3
>
> then:
> patternProperties:
> @@ -299,7 +315,7 @@ examples:
> label = "xo_therm";
> };
>
> - channel@47 {
> + channel@147 {
Why?
> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
> qcom,ratiometric;
> qcom,hw-settle-time = <200>;
> @@ -307,3 +323,80 @@ examples:
> };
> };
> };
> +
> + - |
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
> +
> + pmic {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VADC node */
> + pmk8550_vadc: vadc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
Don't add new examples which differ only in compatible.
> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
> new file mode 100644
> index 000000000000..74e6e2f6f9ed
> --- /dev/null
> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
Dual license.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> The name "ADC7" needs to be replaced with the name "ADC5_GEN2"
> everywhere to match the convention used for these ADC peripherals
> on Qualcomm Technologies, Inc. PMICs. Update devicetree files for
We do not rename compatibles to match convention. Please provide proper
rationale.
> the corresponding name change done in bindings and driver.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/pmk8350.dtsi | 4 +-
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +-
> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +-
> arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 8 ++--
> .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 48 +++++++++----------
> arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +-
> .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 +-
> 7 files changed, 37 insertions(+), 37 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
> index bc6297e7253e..149d2bb43d2d 100644
> --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
> @@ -50,7 +50,7 @@ pon_resin: resin {
> };
>
> pmk8350_vadc: adc@3100 {
> - compatible = "qcom,spmi-adc7";
> + compatible = "qcom,spmi-adc5-gen2";
You break all users without explaining it.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> At present, the QCOM ADC bindings files are located in the
> dt-bindings/iio folder. As they are all specifically for
> ADC, copy them into the dt-bindings/iio/adc folder.
Copy? I expect moving. Either description does not make any sense or
your created a lot of duplicated code.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> Now that usage of "ADC7" name has been replaced with usage of "ADC5
> Gen2" name everywhere, remove the "qcom,spmi-adc7" compatible string.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> drivers/iio/adc/qcom-spmi-adc5.c | 4 ----
Your patchset is not bisectable. Neither this patch nor cover letter
marked this. This is not correct and will lead to broken kernels.
Even if not considering bisectability, this basically breaks the ABI
without any explanation and rationale.
Breaking ABI just because you want to rename something, is not the way
to go, so NAK. Sorry.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> Update ADC dt-bindings file paths in QCOM devicetree files to
> match the dt-bindings change moving the files from 'iio' to
> 'iio/adc' folder.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
Your order of patches is incorrect. DTS cannot be before bindings,
because this indicates you broke ABI. Please keep entire patchset
bisectable and split DTS to separate patchset (linking the driver and
bindings).
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> Update ADC dt-bindings file paths in QCOM devicetree files to
> match the dt-bindings change moving the files from 'iio' to
> 'iio/adc' folder.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
Also (I am repeating myself):
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
Best regards,
Krzysztof
On 08/07/2023 09:28, Jishnu Prakash wrote:
> Now that the ADC dt-binding paths have been updated everywhere
> to use the files copied to the 'iio/adc' folder, remove them
> from the 'iio' folder.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
Nothing this was explained in previous patches... We should not have to
read patchset from the end to understand what is happening here. Anyway,
your commits lack rationale why this is done. Without it, this is pure
churn which breaks users. ABI breaks need to be explained in the commit
msg and come with some reason.
...
> -/* 400k pull-up3 */
> -#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
> -#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
> -#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
> -#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
> -#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
> -#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
> -#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
> -#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
> -#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
> -#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
> -
> -/* 1/3 Divider */
> -#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
> -#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
> -#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
You just added these defines in previous patches. Don't add them to
incorrect places just to fix it second later.
Best regards,
Krzysztof
Hi Jonathan,
Sorry for the late reply, I could not get back earlier as I got occupied
with other work till now. I have addressed your comments inline.
On 7/8/2023 8:28 PM, Jonathan Cameron wrote:
> On Sat, 8 Jul 2023 12:58:25 +0530
> Jishnu Prakash <[email protected]> wrote:
>
>> The name used initially for this version of Qualcomm Technologies, Inc.
>> PMIC ADC was ADC7, following the convention of calling the PMIC generation
>> PMIC7. However, the names were later amended internally to ADC5 Gen2 and
>> PMIC5 Gen2. In addition, the latest PMIC generation now is known as
>> PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more
>> sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7.
>> Since this affects ADC devices across some PMICs, update the names accordingly.
>>
>> In order to avoid breaking the existing implementations of ADC7, add
>> support for ADC5 Gen2 first now and remove the ADC7 support in a later
>> patch.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
> Hi Jishnu.
>
> Whilst I can appreciate why you've picked this particular approach to
> deal with the renames I'm not sure it's the smoothest path - or the
> easiest to review.
>
> If doing a single patch for the complete rename was too much, perhaps
> doing one header (or if it makes sense set of headers)
> at a time would be easier to read? With a final patch doing the compatible
> addition. Maybe let's see what other reviewers think though.
I don't completely understand what you mean here - but first let me
briefly recap what I was trying to do here.
In patches 1-5 of this series, I intended to update all existing support
for ADC7 by renaming it to ADC5 Gen2 to match the correct name used
internally. In addition, since I am adding support for ADC5 Gen3 in
patches 6 and 7, I thought it would make sense to rename this older
peripheral, to make it more obvious to everyone that this version lies
between ADC5 and ADC5 Gen3.
The patches were organized like this:
Patch 1 - Update documentation to add gen2 compatible and update
examples(without removing older compatible). Add new binding files
equivalent to existing ADC7 files, just with macros and file names
updated to use "adc5_gen2" instead of "adc7"
Patch 2 - Update driver files to replace usage of "adc7" with "adc5
gen2", adding new compatible for adc5 gen2 without removing exsiting one
for adc7.
Patch 3 - Update compatible, macros and binding files included in all
devicetree files, based on the earlier two changes.
Patch 4 - Delete all instances of adc7 compatible from documentation
files. Delete all older binding files
Patch 5 - Delete the adc7 compatible from the driver
Based on the comments I got, I understand I cannot proceed as such with
patches 4 and 5, I can amend/drop them. But to get back to your above
point about my overall approach, how exactly would you like me to
structure my patch series?
Should I make one big patch for documentation, bindings, driver and
devicetree changes where I update the naming and deprecate adc7 usage?
This may be straightforward but also hard to review.
Or a patch series like this:
One patch to update documentation
One patch to update the bindings (headers) (Or one patch per header file?)
One patch to update driver file (adding new compatible and comment to
deprecate old one)
One patch to update all devicetree files (or separate patches?)
Please let me know what you think.
> A few other comments inline,
>
> Jonathan
>
>
>>
>> properties:
>> @@ -27,6 +27,7 @@ properties:
>> - qcom,spmi-adc5
>> - qcom,spmi-adc-rev2
>> - qcom,spmi-adc7
>> + - qcom,spmi-adc5-gen2
> Alphabetical order (roughly given currently list). So I'd stick
> this after qcom,spmi-adc5
Will reorder them in the next patchset.
>>
>> reg:
>> description: VADC base address in the SPMI PMIC register map
>> @@ -71,7 +72,7 @@ patternProperties:
>> description: |
>> ADC channel number.
>> See include/dt-bindings/iio/qcom,spmi-vadc.h
>> - For PMIC7 ADC, the channel numbers are specified separately per PMIC
>> + For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
>> in the PMIC-specific files in include/dt-bindings/iio/.
>>
>> label:
>> @@ -114,7 +115,7 @@ patternProperties:
>> channel calibration. If property is not found, channel will be
>> calibrated with 0.625V and 1.25V reference channels, also
>> known as absolute calibration.
>> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
>> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
>> "qcom,spmi-adc-rev2", if this property is specified VADC will use
>> the VDD reference (1.875V) and GND for channel calibration. If
>> property is not found, channel will be calibrated with 0V and 1.25V
>> @@ -213,7 +214,9 @@ allOf:
>> properties:
>> compatible:
>> contains:
>> - const: qcom,spmi-adc7
>> + enum :
>> + - qcom,spmi-adc7
> There is a deprecated marking for dt-bindings. Might be good to use it here.
Thanks for your suggestion, I'll do this in the next patchset.
>
>> + - qcom,spmi-adc5-gen2
>>
>> then:
Thanks,
Jishnu
>>
Hi Krzysztof,
Sorry for the late reply, I could not get back earlier as I got occupied
with other work till now. I have addressed your comments inline.
On 7/9/2023 10:47 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> The name used initially for this version of Qualcomm Technologies, Inc.
>> PMIC ADC was ADC7, following the convention of calling the PMIC generation
>> PMIC7. However, the names were later amended internally to ADC5 Gen2 and
>> PMIC5 Gen2. In addition, the latest PMIC generation now is known as
>> PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more
>> sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7.
>> Since this affects ADC devices across some PMICs, update the names accordingly.
>>
>> In order to avoid breaking the existing implementations of ADC7, add
>> support for ADC5 Gen2 first now and remove the ADC7 support in a later
>> patch.
> I don't understand and I do not see it explained, why do you remove
> ADC7. The patch is also doing way too many things at the same time...
In patches 1-5 of this series, I intended to update all existing support
for ADC7 by renaming it to ADC5 Gen2 to match the correct name used
internally. In addition, since I am adding support for ADC5 Gen3 in
patches 6 and 7, I thought it would make sense to rename this older
peripheral, to make it more obvious to others that this version lies
between ADC5 and ADC5 Gen3.
I have also left a comment in one earlier upstream change for PMIC5 Gen2
ADC_TM (closely related to ADC5 Gen2) where I mentioned the same
briefly, when I was asked why we were not naming it ADC_TM7:
https://lore.kernel.org/linux-arm-msm/[email protected]/.
Is it fine if we keep the old compatible for adc7, marking it
deprecated, while adding the new compatible for adc5-gen2 and updating
the bindings, driver and devicetree completely to use gen2 (while not
replacing instances of the old compatible)?
Or should we also keep the old bindings with macros using the adc7 name
instead of directly replacing them with new macros using the adc5 gen2
name, to avoid the possibility breaking the devicetree for some users?
>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> ---
>> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 21 +++--
>> .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 16 ++--
>> .../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 +++++++++++++
>> .../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 +++++++++++++++++++
>> .../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 ++++++++++
>> .../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++++++
>> .../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++++++
>> include/dt-bindings/iio/qcom,spmi-vadc.h | 77 ++++++++++++++++
> Bindings are always separate patches. If this is commit for bindings, then:
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching.
Sure, I'll check this for the next patch series.
Thanks,
Jishnu
>
>
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
On 7/9/2023 10:48 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> The name "ADC7" needs to be replaced with the name "ADC5_GEN2"
>> everywhere to match the convention used for these ADC peripherals
>> on Qualcomm Technologies, Inc. PMICs. Update devicetree files for
> We do not rename compatibles to match convention. Please provide proper
> rationale.
I'll avoid renaming the compatible directly, will just mark it
deprecated - but is it fine to do the other changes, for updating the
macro names used in devicetree (replacing the ADC7 macros with the ADC5
Gen2 macros)?
I do see an example of a macro change in devicetree done in this patch:
https://lore.kernel.org/all/[email protected]/.
Patch 2 here replaced some macro definitions:
https://lore.kernel.org/all/f9284873c2993a9952d9fe4f8dd5e89f20daab75.1646388139.git.zong.li@sifive.com/.
Patch 3 made the corresponding update in devicetree files:
https://lore.kernel.org/all/db92d209fa700f7da8bc8028083476fcc138d80e.1646388139.git.zong.li@sifive.com/.
From this mail, it looks like the maintainer was willing to pick them
at that time:
https://lore.kernel.org/all/[email protected]/,
would something similar be possible here?
Thanks,
Jishnu
Hi Jonathan,
On 7/8/2023 8:32 PM, Jonathan Cameron wrote:
> On Sat, 8 Jul 2023 12:58:28 +0530
> Jishnu Prakash <[email protected]> wrote:
>
>> Now that usage of "ADC7" name has been replaced with usage of "ADC5
>> Gen2" name everywhere, remove all support for "ADC7" name.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> @@ -26,7 +26,6 @@ properties:
>> - qcom,spmi-vadc
>> - qcom,spmi-adc5
>> - qcom,spmi-adc-rev2
>> - - qcom,spmi-adc7
>> - qcom,spmi-adc5-gen2
>>
>> reg:
>> @@ -214,9 +213,7 @@ allOf:
>> properties:
>> compatible:
>> contains:
>> - enum :
>> - - qcom,spmi-adc7
>> - - qcom,spmi-adc5-gen2
>> + const: qcom,spmi-adc5-gen2
>>
>> then:
>> patternProperties:
> Hmm. Definitely can't drop support (as per comment on next patch).
> I think you should just mark it deprecated rather than remove it here but maybe
> you can drop it. Let's see what DT binding maintainers say.
>
> Jonathan
Yes, I'll mark it deprecated without removing it.
Thanks,
Jishnu
Hi Krzysztof,
On 7/9/2023 10:49 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> Now that usage of "ADC7" name has been replaced with usage of "ADC5
>> Gen2" name everywhere, remove all support for "ADC7" name.
> Why?
The idea is to replace usage of the name "ADC7" with "ADC5 Gen2"
everywhere possible, to match our internal convention and align better
with the "ADC5 Gen3" support I'm adding in this patch series - is it
better if I just update documentation and dtbindings directly in one
patch for ADC5 Gen2 and update devicetree in one patch after that for
the corresponding macro changes?
>
>
>> @@ -26,7 +26,6 @@ properties:
>> - qcom,spmi-vadc
>> - qcom,spmi-adc5
>> - qcom,spmi-adc-rev2
>> - - qcom,spmi-adc7
> NAK. You did not explained why dropping existing compatible is correct,
> expected and okay.
>
> Also:
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching.
>
>
>
> Best regards,
> Krzysztof
Yes, I'll avoid dropping the compatible, I'll just mark it deprecated as
Jonathan suggested, in a single bindings patch without having separate
patches for adding and removing support.
Will make sure to check subject prefixes too.
Thanks,
Jishnu
Hi Jonathan,
On 7/8/2023 8:30 PM, Jonathan Cameron wrote:
> On Sat, 8 Jul 2023 12:58:29 +0530
> Jishnu Prakash <[email protected]> wrote:
>
>> Now that usage of "ADC7" name has been replaced with usage of "ADC5
>> Gen2" name everywhere, remove the "qcom,spmi-adc7" compatible string.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
> Nope. Unless all your dts files are distributed with the kernel, dropping
> this breaks anyone who upgrades the kernel against an older firmware...
>
> So even after the rename, you need to keep the deprecated naming around for
> the binding side of things.
>
> Jonathan
>
>> ---
Yes, I'll drop this patch, will just mark the older name as deprecated.
Thanks,
Jishnu
Hi Krzysztof,
On 7/9/2023 11:08 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> Now that usage of "ADC7" name has been replaced with usage of "ADC5
>> Gen2" name everywhere, remove the "qcom,spmi-adc7" compatible string.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> ---
>> drivers/iio/adc/qcom-spmi-adc5.c | 4 ----
> Your patchset is not bisectable. Neither this patch nor cover letter
> marked this. This is not correct and will lead to broken kernels.
>
> Even if not considering bisectability, this basically breaks the ABI
> without any explanation and rationale.
>
> Breaking ABI just because you want to rename something, is not the way
> to go, so NAK. Sorry.
>
> Best regards,
> Krzysztof
I'll drop this patch and just mark the older name as deprecated. For
concerns on bisectability, I have asked some questions in my other
replies for this patch series, I'll structure my next patchsets
according to the replies I get.
Thanks,
Jishnu
>
Hi Jonathan,
On 7/8/2023 8:42 PM, Jonathan Cameron wrote:
> On Sat, 8 Jul 2023 12:58:30 +0530
> Jishnu Prakash <[email protected]> wrote:
>
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>
>> reg:
>> description: VADC base address in the SPMI PMIC register map
>> - maxItems: 1
>> + minItems: 1
> ?
The idea here is to convey that reg can have multiple values for ADC5
Gen3 as there can be more than one peripheral used for ADC, so there can
be multiple base addresses. I'll try to make this more clear in the next
patchset.
>
>>
>> '#address-cells':
>> const: 1
>> @@ -38,6 +39,12 @@ properties:
>> '#size-cells':
>> const: 0
>>
>> + "#thermal-sensor-cells":
>> + const: 1
>> + description:
>> + Number of cells required to uniquely identify the thermal sensors. Since
>> + we have multiple sensors this is set to 1.
>> +
> Defined only for the new gen3? If so make make it false for the other devices.
Yes, will do that in the next patchset.
>
>> '#io-channel-cells':
>> const: 1
>>
>> @@ -71,8 +78,8 @@ patternProperties:
>> description: |
>> ADC channel number.
>>
>> + qcom,adc-tm-type:
>> + description: |
>> + Indicates if ADC_TM monitoring is done on this channel.
>> + Defined for compatible property "qcom,spmi-adc5-gen3".
>> + type: boolean
> Enforce that in the binding, not via a comment. Once the binding
> performs that check (set it to false for non matching compatibles) then
> there is no need to also mention it in text.
Will do that in the next patchset.
>
>> +
>> required:
>> - reg
>>
>> @@ -213,7 +227,9 @@ allOf:
>> properties:
>> compatible:
>> contains:
>> - const: qcom,spmi-adc5-gen2
>> + enum:
>> + - qcom,spmi-adc5-gen2
>> + - qcom,spmi-adc5-gen3
> Side note - it's fine to have a single element enum, so you could
> use that option to reduce churn in this set...
I think we can remove this and instead specify properties explicitly for
qcom,spmi-adc5-gen3 too separately in the next patchset.
>
>>
>> then:
>> patternProperties:
>> @@ -299,7 +315,7 @@ examples:
>> label = "xo_therm";
>> };
>>
>> - channel@47 {
>> + channel@147 {
> ? If that's a valid change, then it looks like a separate fix.
I think I can avoid this for now, although it would be needed if this
channel number was the virtual channel number made by combining PMIC SID
and actual channel number....maybe we can do it in a separate fix.
>
>> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
>> qcom,ratiometric;
>> qcom,hw-settle-time = <200>;
>> @@ -307,3 +323,80 @@ examples:
>> };
>> };
>> };
>> +
>> +#ifndef PM8550_SID
>> +#define PM8550_SID 1
>> +#endif
>> +
>> +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
>> +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
> can we do the naming for the 0x00 as per Dmitry's set? That is get them from
> qcom,spmi-vadc.h
>
> https://patchwork.kernel.org/project/linux-iio/patch/[email protected]/
Yes, will do that in the next patchset.
Thanks,
Jishnu
Hi Jonathan,
On 7/8/2023 8:55 PM, Jonathan Cameron wrote:
>>> properties:
>>> compatible:
>>> @@ -27,10 +27,11 @@ properties:
>>> - qcom,spmi-adc5
>>> - qcom,spmi-adc-rev2
>>> - qcom,spmi-adc5-gen2
>>> + - qcom,spmi-adc5-gen3
>>>
>>> reg:
>>> description: VADC base address in the SPMI PMIC register map
>>> - maxItems: 1
>>> + minItems: 1
>> ?
> Found it now. This needs documentation that it's providing multiple
> base addresses for gen3. Also needs to only apply that to gen3...
>
Yes, I'll do that in the next patchset.
Thanks,
Jishnu
Hi Krzysztof,
On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>> going through PBS firmware through a single register interface. This
>> interface is implemented on an SDAM peripheral on the master PMIC PMK8550
>> rather than a dedicated ADC peripheral.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> ---
>> properties:
>> compatible:
>> @@ -27,10 +27,11 @@ properties:
>> - qcom,spmi-adc5
>> - qcom,spmi-adc-rev2
>> - qcom,spmi-adc5-gen2
>> + - qcom,spmi-adc5-gen3
>
> This could be ordered...
Yes, will do that in the next patchset.
>>
>> reg:
>> description: VADC base address in the SPMI PMIC register map
>> - maxItems: 1
>> + minItems: 1
> Why? This does not make any sense. With previous patches it looks like
> random set of changes.
The idea here is to convey that reg can have multiple values for ADC5
Gen3 as there can be more than one peripheral used for ADC, so there can
be multiple base addresses. I'll try to make this more clear in the next
patchset.
>
>
>>
>> '#address-cells':
>> const: 1
>> @@ -38,6 +39,12 @@ properties:
>> '#size-cells':
>> const: 0
>>
>>
>> + qcom,adc-tm-type:
>> + description: |
>> + Indicates if ADC_TM monitoring is done on this channel.
> Description does not match property name.
You mean it sounds more like an enum which can take several values
rather than just a boolean? I can update it to "qcom,adc-tm" if that
looks better.
>
>> + Defined for compatible property "qcom,spmi-adc5-gen3".
> Then you need if:then:.
Yes, will update this explicitly for ADC5 Gen3 in the next patchset.
>
>> + type: boolean
>> +
>> required:
>> - reg
>>
>> @@ -213,7 +227,9 @@ allOf:
>> properties:
>> compatible:
>> contains:
>> - const: qcom,spmi-adc5-gen2
>> + enum:
>> + - qcom,spmi-adc5-gen2
>> + - qcom,spmi-adc5-gen3
>>
>> then:
>> patternProperties:
>> @@ -299,7 +315,7 @@ examples:
>> label = "xo_therm";
>> };
>>
>> - channel@47 {
>> + channel@147 {
> Why?
It would be needed if this channel number was supposed to be the virtual
channel number made by combining PMIC SID and actual channel
number....but I could drop it for now and do it in a separate fix as
Jonathan suggested.
>
>> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
>> qcom,ratiometric;
>> qcom,hw-settle-time = <200>;
>> @@ -307,3 +323,80 @@ examples:
>> };
>> };
>> };
>> +
>> + - |
>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
>> +
>> + pmic {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* VADC node */
>> + pmk8550_vadc: vadc@9000 {
>> + compatible = "qcom,spmi-adc5-gen3";
> Don't add new examples which differ only in compatible.
This example does have differences unique to ADC5 Gen3 such as use of
"#thermal-sensor-cells" and "qcom,adc-tm-type" properties....to make it
clearer, I'll delete some of the excess nodes which don't highlight
these differences.
>
>
>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>> new file mode 100644
>> index 000000000000..74e6e2f6f9ed
>> --- /dev/null
>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>> @@ -0,0 +1,48 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
> Dual license.
I think we do have an internal rule by which we do have to add these two
licenses....I'll check again and update them if required.
Thanks,
Jishnu
>
>
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
On 7/9/2023 10:55 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> At present, the QCOM ADC bindings files are located in the
>> dt-bindings/iio folder. As they are all specifically for
>> ADC, copy them into the dt-bindings/iio/adc folder.
> Copy? I expect moving. Either description does not make any sense or
> your created a lot of duplicated code.
In patches 8-11, the intention is to move the dt-binding files used for
QCOM ADCs from /dt-bindings/iio folder to the /dt-bindings/iio/adc
folder. I was not certain how much we could do in a single patch here,
which is why I did this to avoid breaking compilation. I think I can do
it in fewer patches.
Thanks,
Jishnu
>
>
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
On 7/9/2023 10:56 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> Update ADC dt-bindings file paths in QCOM devicetree files to
>> match the dt-bindings change moving the files from 'iio' to
>> 'iio/adc' folder.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> ---
> Your order of patches is incorrect. DTS cannot be before bindings,
> because this indicates you broke ABI. Please keep entire patchset
> bisectable and split DTS to separate patchset (linking the driver and
> bindings).
>
> Best regards,
> Krzysztof
OK....so you mean I can move the dtbinding files and update
documentation and driver files for this, all in one patch and then make
a second patch for updating devicetree files for the file paths?
I'll make this change in the next patchset if it looks fine, although
the two patches would need to be picked together to avoid kernel
breakage. I have asked Jonathan about this too in my reply for the
previous patchset 9.
Thanks,
Jishnu
On 23/10/2023 08:16, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 7/9/2023 10:55 PM, Krzysztof Kozlowski wrote:
>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>> At present, the QCOM ADC bindings files are located in the
>>> dt-bindings/iio folder. As they are all specifically for
>>> ADC, copy them into the dt-bindings/iio/adc folder.
>> Copy? I expect moving. Either description does not make any sense or
>> your created a lot of duplicated code.
>
>
> In patches 8-11, the intention is to move the dt-binding files used for
> QCOM ADCs from /dt-bindings/iio folder to the /dt-bindings/iio/adc
> folder. I was not certain how much we could do in a single patch here,
> which is why I did this to avoid breaking compilation. I think I can do
> it in fewer patches.
I still do not understand. Why would you copy binding headers?
Best regards,
Krzysztof
Hi Krzysztof,
On 7/9/2023 10:56 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> Update ADC dt-bindings file paths in QCOM devicetree files to
>> match the dt-bindings change moving the files from 'iio' to
>> 'iio/adc' folder.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
> Also (I am repeating myself):
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching.
>
> Best regards,
> Krzysztof
Yes, I'll check this for the next patchsets.
Thanks,
Jishnu
Hi Krzysztof,
On 7/9/2023 10:58 PM, Krzysztof Kozlowski wrote:
> On 08/07/2023 09:28, Jishnu Prakash wrote:
>> Now that the ADC dt-binding paths have been updated everywhere
>> to use the files copied to the 'iio/adc' folder, remove them
>> from the 'iio' folder.
>>
>> Signed-off-by: Jishnu Prakash <[email protected]>
>> ---
> Nothing this was explained in previous patches... We should not have to
> read patchset from the end to understand what is happening here. Anyway,
> your commits lack rationale why this is done. Without it, this is pure
> churn which breaks users. ABI breaks need to be explained in the commit
> msg and come with some reason.
I'll try to do the changes in one or two patchsets, based on my replies
for the previous few patchsets (8, 9, 10), hope this can work.
>
> ...
>
>> -/* 400k pull-up3 */
>> -#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
>> -#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
>> -#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
>> -#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
>> -#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
>> -#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
>> -#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
>> -#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
>> -#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
>> -#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
>> -
>> -/* 1/3 Divider */
>> -#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
>> -#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
>> -#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
> You just added these defines in previous patches. Don't add them to
> incorrect places just to fix it second later.
Right, I'll avoid this and add the ADC5 Gen3 macros in the
dt-bindings/iio/adc/ folder in the next patchset, irrespective of what
happens with updating the file paths, hope there won't be any issues.
Thanks,
Jishnu
>
> Best regards,
> Krzysztof
>
On 23/10/2023 08:09, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 7/9/2023 10:48 PM, Krzysztof Kozlowski wrote:
>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>> The name "ADC7" needs to be replaced with the name "ADC5_GEN2"
>>> everywhere to match the convention used for these ADC peripherals
>>> on Qualcomm Technologies, Inc. PMICs. Update devicetree files for
>> We do not rename compatibles to match convention. Please provide proper
>> rationale.
>
> I'll avoid renaming the compatible directly, will just mark it
> deprecated - but is it fine to do the other changes, for updating the
> macro names used in devicetree (replacing the ADC7 macros with the ADC5
> Gen2 macros)?
Please provide proper rationale why "ADC7 needs to be replaced". Your
marketing is not a proper rationale.
>
> I do see an example of a macro change in devicetree done in this patch:
> https://lore.kernel.org/all/[email protected]/.
>
> Patch 2 here replaced some macro definitions:
> https://lore.kernel.org/all/f9284873c2993a9952d9fe4f8dd5e89f20daab75.1646388139.git.zong.li@sifive.com/.
>
> Patch 3 made the corresponding update in devicetree files:
> https://lore.kernel.org/all/db92d209fa700f7da8bc8028083476fcc138d80e.1646388139.git.zong.li@sifive.com/.
And what is rationale in that patchset?
>
>
> From this mail, it looks like the maintainer was willing to pick them
> at that time:
> https://lore.kernel.org/all/[email protected]/,
> would something similar be possible here?
For stated before marketing reasons - no, would not be possible.
Best regards,
Krzysztof
On 23/10/2023 08:11, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 7/9/2023 10:49 PM, Krzysztof Kozlowski wrote:
>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>> Now that usage of "ADC7" name has been replaced with usage of "ADC5
>>> Gen2" name everywhere, remove all support for "ADC7" name.
>> Why?
>
> The idea is to replace usage of the name "ADC7" with "ADC5 Gen2"
> everywhere possible, to match our internal convention and align better
That's not a valid reason to touch bindings. Compatible is just some
unique name, so there is nothing bad in existing name.
> with the "ADC5 Gen3" support I'm adding in this patch series - is it
> better if I just update documentation and dtbindings directly in one
> patch for ADC5 Gen2 and update devicetree in one patch after that for
> the corresponding macro changes?
Don't touch the compatible.
Best regards,
Krzysztof
On 23/10/2023 08:14, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote:
>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>> going through PBS firmware through a single register interface. This
>>> interface is implemented on an SDAM peripheral on the master PMIC PMK8550
>>> rather than a dedicated ADC peripheral.
>>>
>>> Signed-off-by: Jishnu Prakash <[email protected]>
>>> ---
>>> properties:
>>> compatible:
>>> @@ -27,10 +27,11 @@ properties:
>>> - qcom,spmi-adc5
>>> - qcom,spmi-adc-rev2
>>> - qcom,spmi-adc5-gen2
>>> + - qcom,spmi-adc5-gen3
>>
>> This could be ordered...
>
>
> Yes, will do that in the next patchset.
>
>
>>>
>>> reg:
>>> description: VADC base address in the SPMI PMIC register map
>>> - maxItems: 1
>>> + minItems: 1
>> Why? This does not make any sense. With previous patches it looks like
>> random set of changes.
>
>
> The idea here is to convey that reg can have multiple values for ADC5
> Gen3 as there can be more than one peripheral used for ADC, so there can
> be multiple base addresses. I'll try to make this more clear in the next
> patchset.
You cannot remove constraints from an entry.
>
>
>>
>>
>>>
>>> '#address-cells':
>>> const: 1
>>> @@ -38,6 +39,12 @@ properties:
>>> '#size-cells':
>>> const: 0
>>>
>>>
>>> + qcom,adc-tm-type:
>>> + description: |
>>> + Indicates if ADC_TM monitoring is done on this channel.
>> Description does not match property name.
>
>
> You mean it sounds more like an enum which can take several values
> rather than just a boolean? I can update it to "qcom,adc-tm" if that
> looks better.
The property name suggests this is type of monitoring. Property
description says this will enable ADC_TM monitoring. These two do not match.
Except that I wonder now whether this is a property of hardware at
all... What is this monitoring? By the driver?
...
>>> then:
>>> patternProperties:
>>> @@ -299,7 +315,7 @@ examples:
>>> label = "xo_therm";
>>> };
>>>
>>> - channel@47 {
>>> + channel@147 {
>> Why?
>
>
> It would be needed if this channel number was supposed to be the virtual
> channel number made by combining PMIC SID and actual channel
> number....but I could drop it for now and do it in a separate fix as
> Jonathan suggested.
>
>
>>
>>> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>;
>>> qcom,ratiometric;
>>> qcom,hw-settle-time = <200>;
>>> @@ -307,3 +323,80 @@ examples:
>>> };
>>> };
>>> };
>>> +
>>> + - |
>>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
>>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
>>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
>>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
>>> +
>>> + pmic {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + /* VADC node */
>>> + pmk8550_vadc: vadc@9000 {
>>> + compatible = "qcom,spmi-adc5-gen3";
>> Don't add new examples which differ only in compatible.
>
>
> This example does have differences unique to ADC5 Gen3 such as use of
> "#thermal-sensor-cells" and "qcom,adc-tm-type" properties....to make it
> clearer, I'll delete some of the excess nodes which don't highlight
> these differences.
>
>
>>
>>
>>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>>> new file mode 100644
>>> index 000000000000..74e6e2f6f9ed
>>> --- /dev/null
>>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>>> @@ -0,0 +1,48 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> Dual license.
>
>
> I think we do have an internal rule by which we do have to add these two
> licenses....I'll check again and update them if required.
Just to be clear: your internal rules are your internal affair. We
expect here dual license.
Best regards,
Krzysztof
On 23/10/2023 08:18, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 7/9/2023 10:56 PM, Krzysztof Kozlowski wrote:
>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>> Update ADC dt-bindings file paths in QCOM devicetree files to
>>> match the dt-bindings change moving the files from 'iio' to
>>> 'iio/adc' folder.
>>>
>>> Signed-off-by: Jishnu Prakash <[email protected]>
>>> ---
>> Your order of patches is incorrect. DTS cannot be before bindings,
>> because this indicates you broke ABI. Please keep entire patchset
>> bisectable and split DTS to separate patchset (linking the driver and
>> bindings).
>>
>> Best regards,
>> Krzysztof
>
> OK....so you mean I can move the dtbinding files and update
> documentation and driver files for this, all in one patch and then make
No
> a second patch for updating devicetree files for the file paths?
No. And this proves the patchset is broken.
Best regards,
Krzysztof
On 23/10/2023 08:19, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 7/9/2023 10:58 PM, Krzysztof Kozlowski wrote:
>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>> Now that the ADC dt-binding paths have been updated everywhere
>>> to use the files copied to the 'iio/adc' folder, remove them
>>> from the 'iio' folder.
>>>
>>> Signed-off-by: Jishnu Prakash <[email protected]>
>>> ---
>> Nothing this was explained in previous patches... We should not have to
>> read patchset from the end to understand what is happening here. Anyway,
>> your commits lack rationale why this is done. Without it, this is pure
>> churn which breaks users. ABI breaks need to be explained in the commit
>> msg and come with some reason.
>
>
> I'll try to do the changes in one or two patchsets, based on my replies
> for the previous few patchsets (8, 9, 10), hope this can work.
You are not responding to actual comment. Splitting this to one (??? it
is already one patchset) or two patchsets will not fix anything. You
still break users and break ABI without justification. Your marketing is
not a justification for that.
Best regards,
Krzysztof
On Mon, 23 Oct 2023 11:35:43 +0530
Jishnu Prakash <[email protected]> wrote:
> Hi Jonathan,
>
> Sorry for the late reply, I could not get back earlier as I got occupied
> with other work till now. I have addressed your comments inline.
>
> On 7/8/2023 8:28 PM, Jonathan Cameron wrote:
> > On Sat, 8 Jul 2023 12:58:25 +0530
> > Jishnu Prakash <[email protected]> wrote:
> >
> >> The name used initially for this version of Qualcomm Technologies, Inc.
> >> PMIC ADC was ADC7, following the convention of calling the PMIC generation
> >> PMIC7. However, the names were later amended internally to ADC5 Gen2 and
> >> PMIC5 Gen2. In addition, the latest PMIC generation now is known as
> >> PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more
> >> sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7.
> >> Since this affects ADC devices across some PMICs, update the names accordingly.
> >>
> >> In order to avoid breaking the existing implementations of ADC7, add
> >> support for ADC5 Gen2 first now and remove the ADC7 support in a later
> >> patch.
> >>
> >> Signed-off-by: Jishnu Prakash <[email protected]>
> > Hi Jishnu.
> >
> > Whilst I can appreciate why you've picked this particular approach to
> > deal with the renames I'm not sure it's the smoothest path - or the
> > easiest to review.
> >
> > If doing a single patch for the complete rename was too much, perhaps
> > doing one header (or if it makes sense set of headers)
> > at a time would be easier to read? With a final patch doing the compatible
> > addition. Maybe let's see what other reviewers think though.
>
>
> I don't completely understand what you mean here - but first let me
> briefly recap what I was trying to do here.
>
> In patches 1-5 of this series, I intended to update all existing support
> for ADC7 by renaming it to ADC5 Gen2 to match the correct name used
> internally. In addition, since I am adding support for ADC5 Gen3 in
> patches 6 and 7, I thought it would make sense to rename this older
> peripheral, to make it more obvious to everyone that this version lies
> between ADC5 and ADC5 Gen3.
>
> The patches were organized like? this:
>
> Patch 1 - Update documentation to add gen2 compatible and update
> examples(without removing older compatible). Add new binding files
> equivalent to existing ADC7 files, just with macros and file names
> updated to use "adc5_gen2" instead of "adc7"
>
> Patch 2 - Update driver files to replace usage of "adc7" with "adc5
> gen2", adding new compatible for adc5 gen2 without removing exsiting one
> for adc7.
>
> Patch 3 - Update compatible, macros and binding files included in all
> devicetree files, based on the earlier two changes.
>
> Patch 4 - Delete all instances of adc7 compatible from documentation
> files. Delete all older binding files
>
> Patch 5 - Delete the adc7 compatible from the driver
>
>
> Based on the comments I got, I understand I cannot proceed as such with
> patches 4 and 5, I can amend/drop them. But to get back to your above
> point about my overall approach, how exactly would you like me to
> structure my patch series?
>
> Should I make one big patch for documentation, bindings, driver and
> devicetree changes where I update the naming and deprecate adc7 usage?
> This may be straightforward but also hard to review.
>
>
> Or a patch series like this:
>
> One patch to update documentation
>
> One patch to update the bindings (headers) (Or one patch per header file?)
>
> One patch to update driver file (adding new compatible and comment to
> deprecate old one)
>
> One patch to update all devicetree files (or separate patches?)
It must remain buildable at all times. That can either be done by
duplicating everything, or by pushing through a patch that performs
all renames (maybe excluding bindings as we care less about that).
The all renames in single patch is a lot easier to review as can
see both sides of the change in a single patch.
Breaking that up into sets of renames will keep it manageable.
Jonathan
>
> Please let me know what you think.
>
> > A few other comments inline,
> >
> > Jonathan
> >
> >
> >>
> >> properties:
> >> @@ -27,6 +27,7 @@ properties:
> >> - qcom,spmi-adc5
> >> - qcom,spmi-adc-rev2
> >> - qcom,spmi-adc7
> >> + - qcom,spmi-adc5-gen2
> > Alphabetical order (roughly given currently list). So I'd stick
> > this after qcom,spmi-adc5
>
>
> Will reorder them in the next patchset.
>
>
> >>
> >> reg:
> >> description: VADC base address in the SPMI PMIC register map
> >> @@ -71,7 +72,7 @@ patternProperties:
> >> description: |
> >> ADC channel number.
> >> See include/dt-bindings/iio/qcom,spmi-vadc.h
> >> - For PMIC7 ADC, the channel numbers are specified separately per PMIC
> >> + For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC
> >> in the PMIC-specific files in include/dt-bindings/iio/.
> >>
> >> label:
> >> @@ -114,7 +115,7 @@ patternProperties:
> >> channel calibration. If property is not found, channel will be
> >> calibrated with 0.625V and 1.25V reference channels, also
> >> known as absolute calibration.
> >> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
> >> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and
> >> "qcom,spmi-adc-rev2", if this property is specified VADC will use
> >> the VDD reference (1.875V) and GND for channel calibration. If
> >> property is not found, channel will be calibrated with 0V and 1.25V
> >> @@ -213,7 +214,9 @@ allOf:
> >> properties:
> >> compatible:
> >> contains:
> >> - const: qcom,spmi-adc7
> >> + enum :
> >> + - qcom,spmi-adc7
> > There is a deprecated marking for dt-bindings. Might be good to use it here.
>
>
> Thanks for your suggestion, I'll do this in the next patchset.
>
>
> >
> >> + - qcom,spmi-adc5-gen2
> >>
> >> then:
>
> Thanks,
>
> Jishnu
>
> >>
Hi Krzysztof,
On 11/10/2023 4:29 PM, Krzysztof Kozlowski wrote:
> On 09/11/2023 09:22, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 10/23/2023 12:02 PM, Krzysztof Kozlowski wrote:
>>
>> Since you do not want us to modify the existing bindings, is it fine if
>> I just add a new compatible for ADC5 Gen2 and comments to indicate the
>> ADC7 compatible should be considered deprecated?
> No, because adc7 compatible is valid and there is no reason to replace
> it. Just because you changed naming does not matter for compatibles.
> It's just unique string, that's it. Don't touch it.
>
>
>> If you are not convinced, we can drop the Gen2 name related changes from
>> the patch series.
> Feel free to add comments or descriptions, if you want to map some
> marketing name to real hardware or to compatibles.
Yes, I'll just add a line in the documentation to mention ADC7 goes
between ADC5 and ADC5 Gen3.
Thanks,
Jishnu
> Best regards,
> Krzysztof
>
Hi Krzysztof,
On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote:
> On 23/10/2023 08:14, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote:
>>
>>>> reg:
>>>> description: VADC base address in the SPMI PMIC register map
>>>> - maxItems: 1
>>>> + minItems: 1
>>> Why? This does not make any sense. With previous patches it looks like
>>> random set of changes.
>> The idea here is to convey that reg can have multiple values for ADC5
>> Gen3 as there can be more than one peripheral used for ADC, so there can
>> be multiple base addresses. I'll try to make this more clear in the next
>> patchset.
> You cannot remove constraints from an entry.
In this case, minItems: 1 will remain true for all other ADC devices
documented here, but it will not be true for ADC5 Gen3, as this one can
have multiple base addresses if more than one SDAM is used for ADC. I'll
update this separately for each compatible, keeping it the same for the
older ones, hope that should work.
>>>>
>>>> '#address-cells':
>>>> const: 1
>>>> @@ -38,6 +39,12 @@ properties:
>>>> '#size-cells':
>>>> const: 0
>>>>
>>>>
>>>> + qcom,adc-tm-type:
>>>> + description: |
>>>> + Indicates if ADC_TM monitoring is done on this channel.
>>> Description does not match property name.
>> You mean it sounds more like an enum which can take several values
>> rather than just a boolean? I can update it to "qcom,adc-tm" if that
>> looks better.
> The property name suggests this is type of monitoring. Property
> description says this will enable ADC_TM monitoring. These two do not match.
>
> Except that I wonder now whether this is a property of hardware at
> all... What is this monitoring? By the driver?
The property description is right, this property is used to indicate
that one of the configurable channels on the ADC SDAMs will be used for
ADC_TM functionality, for periodically monitoring this particular ADC
channel . This is the exact same functionality as in the existing QCOM
ADC_TM device, documented at
devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. I'll mention this
too in the description.
It can be considered a property of the hardware as the monitoring is
done by a sequence under PBS (Programmable Boot Sequence, can be
considered firmware), which periodically gets the channel reading and
checks it against upper/lower thresholds set by clients of this driver,
for threshold violations.
> ...
>
>>>> then:
>>>> patternProperties:
>>>> @@ -299,7 +315,7 @@ examples:
>>>> label = "xo_therm";
>>>> };
>>>>
>>>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>>>> new file mode 100644
>>>> index 000000000000..74e6e2f6f9ed
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>>>> @@ -0,0 +1,48 @@
>>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>> Dual license.
>> I think we do have an internal rule by which we do have to add these two
>> licenses....I'll check again and update them if required.
> Just to be clear: your internal rules are your internal affair. We
> expect here dual license.
I misunderstood what you meant earlier, I understand now that
"GPL-2.0-only" is wrong, I'll update it.
Thanks,
Jishnu
> Best regards,
> Krzysztof
>
Hi Bjorn,
On 11/11/2023 5:17 AM, Bjorn Andersson wrote:
> On Mon, Oct 23, 2023 at 11:48:13AM +0530, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 7/9/2023 10:56 PM, Krzysztof Kozlowski wrote:
>>> On 08/07/2023 09:28, Jishnu Prakash wrote:
>>>> Update ADC dt-bindings file paths in QCOM devicetree files to
>>>> match the dt-bindings change moving the files from 'iio' to
>>>> 'iio/adc' folder.
>>>>
>>>> Signed-off-by: Jishnu Prakash<[email protected]>
>>>> ---
>>> Your order of patches is incorrect. DTS cannot be before bindings,
>>> because this indicates you broke ABI. Please keep entire patchset
>>> bisectable and split DTS to separate patchset (linking the driver and
>>> bindings).
>>>
>>> Best regards,
>>> Krzysztof
>> OK....so you mean I can move the dtbinding files and update documentation
>> and driver files for this, all in one patch and then make a second patch for
>> updating devicetree files for the file paths?
>>
>> I'll make this change in the next patchset if it looks fine, although the
>> two patches would need to be picked together to avoid kernel breakage. I
>> have asked Jonathan about this too in my reply for the previous patchset 9.
>>
> 1) We need to be able to use git bisect to identify regressions, and as
> such the kernel need to be buildable and functional after each applied
> patch.
>
> 2) DeviceTree source (dts) changes enters the kernel through different
> maintainer paths than the DeviceTree binding and driver changes, and
> therefore at different times. In some cases the .dtb file is also
> delivered separately from the kernel, which means people might be
> running an old .dtb for a considerable amount of time after your change.
> As such your driver changes needs to be compatible with both the new and
> the old DeviceTree binding.
Thanks for your comments. For now, Jonathan and Dmitry have asked me to
move the binding files and fix all errors in one commit for their
review, so I'll be doing as they requested. Based on their review, I'm
assuming they will also suggest what other changes are needed for
compatibility with older devicetrees as you mentioned.
> Regards,
> Bjorn
On 16/11/2023 04:23, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote:
>> On 23/10/2023 08:14, Jishnu Prakash wrote:
>>> Hi Krzysztof,
>>>
>>> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote:
>>>
>>>>> reg:
>>>>> description: VADC base address in the SPMI PMIC register map
>>>>> - maxItems: 1
>>>>> + minItems: 1
>>>> Why? This does not make any sense. With previous patches it looks like
>>>> random set of changes.
>>> The idea here is to convey that reg can have multiple values for ADC5
>>> Gen3 as there can be more than one peripheral used for ADC, so there can
>>> be multiple base addresses. I'll try to make this more clear in the next
>>> patchset.
>> You cannot remove constraints from an entry.
>
>
> In this case, minItems: 1 will remain true for all other ADC devices
> documented here, but it will not be true for ADC5 Gen3, as this one can
> have multiple base addresses if more than one SDAM is used for ADC. I'll
> update this separately for each compatible, keeping it the same for the
> older ones, hope that should work.
You responded like you disagree with me, so just in case: my comment
stays. If you resend the same, I will NAK it.
>
>
>>>>>
>>>>> '#address-cells':
>>>>> const: 1
>>>>> @@ -38,6 +39,12 @@ properties:
>>>>> '#size-cells':
>>>>> const: 0
>>>>>
>>>>>
>>>>> + qcom,adc-tm-type:
>>>>> + description: |
>>>>> + Indicates if ADC_TM monitoring is done on this channel.
>>>> Description does not match property name.
>>> You mean it sounds more like an enum which can take several values
>>> rather than just a boolean? I can update it to "qcom,adc-tm" if that
>>> looks better.
>> The property name suggests this is type of monitoring. Property
>> description says this will enable ADC_TM monitoring. These two do not match.
>>
>> Except that I wonder now whether this is a property of hardware at
>> all... What is this monitoring? By the driver?
>
>
> The property description is right, this property is used to indicate
> that one of the configurable channels on the ADC SDAMs will be used for
> ADC_TM functionality, for periodically monitoring this particular ADC
> channel . This is the exact same functionality as in the existing QCOM
> ADC_TM device, documented at
> devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. I'll mention this
> too in the description.
>
> It can be considered a property of the hardware as the monitoring is
> done by a sequence under PBS (Programmable Boot Sequence, can be
> considered firmware), which periodically gets the channel reading and
> checks it against upper/lower thresholds set by clients of this driver,
> for threshold violations.
>
>
>> ...
>>
>>>>> then:
>>>>> patternProperties:
>>>>> @@ -299,7 +315,7 @@ examples:
>>>>> label = "xo_therm";
>>>>> };
>>>>>
>
>>>>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>>>>> new file mode 100644
>>>>> index 000000000000..74e6e2f6f9ed
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h
>>>>> @@ -0,0 +1,48 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>>> Dual license.
>>> I think we do have an internal rule by which we do have to add these two
>>> licenses....I'll check again and update them if required.
>> Just to be clear: your internal rules are your internal affair. We
>> expect here dual license.
>
>
> I misunderstood what you meant earlier, I understand now that
> "GPL-2.0-only" is wrong, I'll update it.
If only you run checkpatch before sending patches...
Best regards,
Krzysztof
On 16/11/2023 04:23, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote:
>> On 23/10/2023 08:14, Jishnu Prakash wrote:
>>> Hi Krzysztof,
>>>
>>> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote:
>>>
>>>>> reg:
>>>>> description: VADC base address in the SPMI PMIC register map
>>>>> - maxItems: 1
>>>>> + minItems: 1
>>>> Why? This does not make any sense. With previous patches it looks like
>>>> random set of changes.
>>> The idea here is to convey that reg can have multiple values for ADC5
>>> Gen3 as there can be more than one peripheral used for ADC, so there can
>>> be multiple base addresses. I'll try to make this more clear in the next
>>> patchset.
>> You cannot remove constraints from an entry.
>
>
> In this case, minItems: 1 will remain true for all other ADC devices
> documented here, but it will not be true for ADC5 Gen3, as this one can
> have multiple base addresses if more than one SDAM is used for ADC. I'll
> update this separately for each compatible, keeping it the same for the
> older ones, hope that should work.
BTW, you disagree with me and send new version 2 minutes later.
Basically you did not leave me any time to respond to you.
That's not how the process works.
Best regards,
Krzysztof
Hi Krzysztof
On 11/16/2023 5:16 PM, Krzysztof Kozlowski wrote:
> On 16/11/2023 04:23, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote:
>>> You cannot remove constraints from an entry.
>>
>> In this case, minItems: 1 will remain true for all other ADC devices
>> documented here, but it will not be true for ADC5 Gen3, as this one can
>> have multiple base addresses if more than one SDAM is used for ADC. I'll
>> update this separately for each compatible, keeping it the same for the
>> older ones, hope that should work.
> BTW, you disagree with me and send new version 2 minutes later.
> Basically you did not leave me any time to respond to you.
>
> That's not how the process works.
Sorry about this, I'll make sure not to repeat this.
Thanks,
Jishnu
>
> Best regards,
> Krzysztof
>