Hi
This series adds corresponding AM642x CPSW3g nodes required to enable networking
on TI am642-evm/sk platforms and adds required pinmux/PHY nodes in corresponding
board files.
Kernel Boot Log:
EVM: https://pastebin.ubuntu.com/p/6Qkbw35Jg3/
SK: https://pastebin.ubuntu.com/p/Pd3xxP9J9K/
Grygorii Strashko (1):
arm64: dts: ti: k3-am64-main: add main CPTS entry
Vignesh Raghavendra (3):
arm64: dts: ti: am64-main: Add CPSW DT node
arm64: dts: ti: k3-am642-evm: add CPSW3g DT nodes
arm64: dts: ti: k3-am642-sk: Add CPSW DT nodes
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 89 +++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 +
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 93 ++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 73 +++++++++++++++++++
4 files changed, 257 insertions(+)
--
2.17.1
Add DT node for the Main domain CPTS.
Signed-off-by: Grygorii Strashko <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 80443dbf272c..0cf727e3d1e2 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -476,4 +476,19 @@
ti,cpts-periodic-outputs = <2>;
};
};
+
+ cpts@39000000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x39000000 0x0 0x400>;
+ reg-names = "cpts";
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 84 0>;
+ clock-names = "cpts";
+ assigned-clocks = <&k3_clks 84 0>;
+ assigned-clock-parents = <&k3_clks 84 8>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+ };
};
--
2.17.1
From: Vignesh Raghavendra <[email protected]>
Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
feature), so that CPSW DMA channel participates in Coherency and thus avoid
need to cache maintenance for SKBs. This improves bidirectional TCP
performance by up to 100Mbps (on 1G link).
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Grygorii Strashko <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 +
2 files changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 5f85950daef7..80443dbf272c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -178,6 +178,12 @@
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
};
main_uart0: serial@2800000 {
@@ -402,4 +408,72 @@
ti,otap-del-sel-ddr50 = <0x9>;
ti,clkbuf-sel = <0x7>;
};
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 1>;
+ assigned-clock-parents = <&k3_clks 13 9>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_pktdma 0xC500 15>,
+ <&main_pktdma 0xC501 15>,
+ <&main_pktdma 0xC502 15>,
+ <&main_pktdma 0xC503 15>,
+ <&main_pktdma 0xC504 15>,
+ <&main_pktdma 0xC505 15>,
+ <&main_pktdma 0xC506 15>,
+ <&main_pktdma 0xC507 15>,
+ <&main_pktdma 0x4500 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 de ad be ef];
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 01 de ad be ef];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 0ae8c844c482..de6805b0c72c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -28,6 +28,8 @@
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
};
chosen { };
--
2.17.1
From: Vignesh Raghavendra <[email protected]>
AM642 SK board has 2 CPSW3g ports connected through TI DP83867 PHYs. Add DT
entries for the same.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Grygorii Strashko <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 73 ++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index aa6ca4c49153..397ed3b2e121 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
@@ -90,6 +91,47 @@
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
+ AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
+ AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
};
&mcu_uart0 {
@@ -171,3 +213,34 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
--
2.17.1
On 04/03/21 12:51 am, Grygorii Strashko wrote:
> From: Vignesh Raghavendra <[email protected]>
>
> Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
> CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
> feature), so that CPSW DMA channel participates in Coherency and thus avoid
> need to cache maintenance for SKBs. This improves bidirectional TCP
> performance by up to 100Mbps (on 1G link).
>
> Signed-off-by: Vignesh Raghavendra <[email protected]>
> Signed-off-by: Grygorii Strashko <[email protected]>
nit pick. In $subject : k3-am64-main.
Thanks and regards,
Lokesh
> ---
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 +
> 2 files changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index 5f85950daef7..80443dbf272c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -178,6 +178,12 @@
> compatible = "ti,am654-chipid";
> reg = <0x00000014 0x4>;
> };
> +
> + phy_gmii_sel: phy@4044 {
> + compatible = "ti,am654-phy-gmii-sel";
> + reg = <0x4044 0x8>;
> + #phy-cells = <1>;
> + };
> };
>
> main_uart0: serial@2800000 {
> @@ -402,4 +408,72 @@
> ti,otap-del-sel-ddr50 = <0x9>;
> ti,clkbuf-sel = <0x7>;
> };
> +
> + cpsw3g: ethernet@8000000 {
> + compatible = "ti,am642-cpsw-nuss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x8000000 0x0 0x200000>;
> + reg-names = "cpsw_nuss";
> + ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
> + clocks = <&k3_clks 13 0>;
> + assigned-clocks = <&k3_clks 13 1>;
> + assigned-clock-parents = <&k3_clks 13 9>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <&main_pktdma 0xC500 15>,
> + <&main_pktdma 0xC501 15>,
> + <&main_pktdma 0xC502 15>,
> + <&main_pktdma 0xC503 15>,
> + <&main_pktdma 0xC504 15>,
> + <&main_pktdma 0xC505 15>,
> + <&main_pktdma 0xC506 15>,
> + <&main_pktdma 0xC507 15>,
> + <&main_pktdma 0x4500 15>;
> + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
> + "tx7", "rx";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpsw_port1: port@1 {
> + reg = <1>;
> + ti,mac-only;
> + label = "port1";
> + phys = <&phy_gmii_sel 1>;
> + mac-address = [00 00 de ad be ef];
> + };
> +
> + cpsw_port2: port@2 {
> + reg = <2>;
> + ti,mac-only;
> + label = "port2";
> + phys = <&phy_gmii_sel 2>;
> + mac-address = [00 01 de ad be ef];
> + };
> + };
> +
> + cpsw3g_mdio: mdio@f00 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + reg = <0x0 0xf00 0x0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&k3_clks 13 0>;
> + clock-names = "fck";
> + bus_freq = <1000000>;
> + };
> +
> + cpts@3d000 {
> + compatible = "ti,j721e-cpts";
> + reg = <0x0 0x3d000 0x0 0x400>;
> + clocks = <&k3_clks 13 1>;
> + clock-names = "cpts";
> + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "cpts";
> + ti,cpts-ext-ts-inputs = <4>;
> + ti,cpts-periodic-outputs = <2>;
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> index 0ae8c844c482..de6805b0c72c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> @@ -28,6 +28,8 @@
> serial6 = &main_uart4;
> serial7 = &main_uart5;
> serial8 = &main_uart6;
> + ethernet0 = &cpsw_port1;
> + ethernet1 = &cpsw_port2;
> };
>
> chosen { };
>
On 04/03/21 12:51 am, Grygorii Strashko wrote:
> Hi
>
> This series adds corresponding AM642x CPSW3g nodes required to enable networking
> on TI am642-evm/sk platforms and adds required pinmux/PHY nodes in corresponding
> board files.
>
> Kernel Boot Log:
> EVM: https://pastebin.ubuntu.com/p/6Qkbw35Jg3/
> SK: https://pastebin.ubuntu.com/p/Pd3xxP9J9K/
Except for the minor comment. Series
Reviewed-by: Lokesh Vutla <[email protected]>
Thanks and regards,
Lokesh
>
>
> Grygorii Strashko (1):
> arm64: dts: ti: k3-am64-main: add main CPTS entry
>
> Vignesh Raghavendra (3):
> arm64: dts: ti: am64-main: Add CPSW DT node
> arm64: dts: ti: k3-am642-evm: add CPSW3g DT nodes
> arm64: dts: ti: k3-am642-sk: Add CPSW DT nodes
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 89 +++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 +
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 93 ++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 73 +++++++++++++++++++
> 4 files changed, 257 insertions(+)
>