One of the clock entry "dcl" clk's rate can only be changed by
changing its parent's clock rate. But it was missing to have
CLK_SET_RATE_PARENT flag as enabled.
Add/enable CLK_SET_RATE_PARENT flag for dcl clk in order to
allow its clk rate to be changed via its parent's clk.
Signed-off-by: Rahul Tanwar <[email protected]>
---
drivers/clk/x86/clk-lgm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c
index e312af42e97a..34e16ea90596 100644
--- a/drivers/clk/x86/clk-lgm.c
+++ b/drivers/clk/x86/clk-lgm.c
@@ -255,7 +255,7 @@ static const struct lgm_clk_branch lgm_branch_clks[] = {
LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
- LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
+ LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR,
25, 3, 0, 0, 0, 0, dcl_div),
LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
0, 1, CLK_MUX_ROUND_CLOSEST, 0),
--
2.17.1
Quoting Rahul Tanwar (2022-09-21 23:24:28)
> One of the clock entry "dcl" clk's rate can only be changed by
> changing its parent's clock rate. But it was missing to have
> CLK_SET_RATE_PARENT flag as enabled.
>
> Add/enable CLK_SET_RATE_PARENT flag for dcl clk in order to
> allow its clk rate to be changed via its parent's clk.
>
> Signed-off-by: Rahul Tanwar <[email protected]>
> ---
Any Fixes tag?
On 29/9/2022 8:18 am, Stephen Boyd wrote:
> This email was sent from outside of MaxLinear.
>
>
> Quoting Rahul Tanwar (2022-09-21 23:24:28)
>> One of the clock entry "dcl" clk's rate can only be changed by
>> changing its parent's clock rate. But it was missing to have
>> CLK_SET_RATE_PARENT flag as enabled.
>>
>> Add/enable CLK_SET_RATE_PARENT flag for dcl clk in order to
>> allow its clk rate to be changed via its parent's clk.
>>
>> Signed-off-by: Rahul Tanwar <[email protected]>
>> ---
>
> Any Fixes tag?
>
Missed it, will add in v3.
Thanks,
Rahul
>