As noted by some people, some parts of the recently added extensions
(svpbmt, zicbom) + t-head errata could use some styling upgrades.
So this series provides these.
changes in v2:
- add patch also converting cpufeature probe to BIT()
- update commit message in patch1 (Conor)
Heiko Stuebner (5):
riscv: cleanup svpbmt cpufeature probing
riscv: drop some idefs from CMO initialization
riscv: use BIT() macros in t-head errata init
riscv: use BIT() marco for cpufeature probing
riscv: check for kernel config option in t-head memory types errata
arch/riscv/errata/thead/errata.c | 14 ++++++-----
arch/riscv/include/asm/cacheflush.h | 2 ++
arch/riscv/kernel/cpufeature.c | 39 ++++++++++++-----------------
3 files changed, 26 insertions(+), 29 deletions(-)
--
2.35.1
Using the appropriate BIT macro makes the code better readable.
Suggested-by: Conor Dooley <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
arch/riscv/errata/thead/errata.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index bffa711aaf64..a6f4bd8ccf3f 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage,
u32 cpu_req_errata = 0;
if (errata_probe_pbmt(stage, archid, impid))
- cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
+ cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
if (errata_probe_cmo(stage, archid, impid))
- cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
+ cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
return cpu_req_errata;
}
--
2.35.1
Using the appropriate BIT macro makes the code better readable.
Suggested-by: Conor Dooley <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/kernel/cpufeature.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 729f7a218093..08f7445985dc 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -289,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
u32 cpu_req_feature = 0;
if (cpufeature_probe_svpbmt(stage))
- cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
+ cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
if (cpufeature_probe_zicbom(stage))
- cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
+ cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);
return cpu_req_feature;
}
--
2.35.1
For better readability (and compile time coverage) use IS_ENABLED
instead of ifdef and drop the new unneeded switch statement.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
arch/riscv/kernel/cpufeature.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 553d755483ed..764ea220161f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
#ifdef CONFIG_RISCV_ALTERNATIVE
static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
{
-#ifdef CONFIG_RISCV_ISA_SVPBMT
- switch (stage) {
- case RISCV_ALTERNATIVES_EARLY_BOOT:
+ if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
return false;
- default:
- return riscv_isa_extension_available(NULL, SVPBMT);
- }
-#endif
- return false;
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ return false;
+
+ return riscv_isa_extension_available(NULL, SVPBMT);
}
static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
--
2.35.1
The t-head variant of page-based memory types should also check first
for the enabled kernel config option.
Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
arch/riscv/errata/thead/errata.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index a6f4bd8ccf3f..902e12452821 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -17,6 +17,9 @@
static bool errata_probe_pbmt(unsigned int stage,
unsigned long arch_id, unsigned long impid)
{
+ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
+ return false;
+
if (arch_id != 0 || impid != 0)
return false;
--
2.35.1
Wrapping things in #ifdefs makes the code harder to read
while we also have IS_ENABLED() macros to do this in regular code
and the extension detection is not _that_ runtime critical.
So define a stub for riscv_noncoherent_supported() in the
non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
us IS_ENABLED.
Suggested-by: Conor Dooley <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
arch/riscv/errata/thead/errata.c | 7 +++----
arch/riscv/include/asm/cacheflush.h | 2 ++
arch/riscv/kernel/cpufeature.c | 22 +++++++++-------------
3 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 202c83f677b2..bffa711aaf64 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
static bool errata_probe_cmo(unsigned int stage,
unsigned long arch_id, unsigned long impid)
{
-#ifdef CONFIG_ERRATA_THEAD_CMO
+ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
+ return false;
+
if (arch_id != 0 || impid != 0)
return false;
@@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
riscv_noncoherent_supported();
return true;
-#else
- return false;
-#endif
}
static u32 thead_errata_probe(unsigned int stage,
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index a60acaecfeda..4363d0beb38a 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
#ifdef CONFIG_RISCV_DMA_NONCOHERENT
void riscv_noncoherent_supported(void);
+#else
+static inline void riscv_noncoherent_supported(void) {}
#endif
/*
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 764ea220161f..729f7a218093 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
{
-#ifdef CONFIG_RISCV_ISA_ZICBOM
- switch (stage) {
- case RISCV_ALTERNATIVES_EARLY_BOOT:
+ if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
+ return false;
+
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ return false;
+
+ if (!riscv_isa_extension_available(NULL, ZICBOM))
return false;
- default:
- if (riscv_isa_extension_available(NULL, ZICBOM)) {
- riscv_noncoherent_supported();
- return true;
- } else {
- return false;
- }
- }
-#endif
- return false;
+ riscv_noncoherent_supported();
+ return true;
}
/*
--
2.35.1
Am Montag, 5. September 2022, 13:19:41 CEST schrieb [email protected]:
> On 05/09/2022 12:10, Heiko Stuebner wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Using the appropriate BIT macro makes the code better readable.
> >
> > Suggested-by: Conor Dooley <[email protected]>
> > Signed-off-by: Heiko Stuebner <[email protected]>
>
> Missing the cover-letter with the changelog?
> At least, I didn't get it in my inbox.
darn git send-email and its automatic selection ;-)
I.e. I _should_ have added you to the hard recipient list for my series
in the first place, but instead git send-email selected you based on
the Suggested-by ... but it looks like these selectoions don't get
applied to the cover-letter ... sorry about that
Heiko
> Either way,
>
> Reviewed-by: Conor Dooley <[email protected]>
>
> > ---
> > arch/riscv/kernel/cpufeature.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 729f7a218093..08f7445985dc 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -289,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
> > u32 cpu_req_feature = 0;
> >
> > if (cpufeature_probe_svpbmt(stage))
> > - cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
> > + cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
> >
> > if (cpufeature_probe_zicbom(stage))
> > - cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
> > + cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);
> >
> > return cpu_req_feature;
> > }
> > --
> > 2.35.1
> >
>
>
On 05/09/2022 12:10, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Using the appropriate BIT macro makes the code better readable.
>
> Suggested-by: Conor Dooley <[email protected]>
> Signed-off-by: Heiko Stuebner <[email protected]>
Missing the cover-letter with the changelog?
At least, I didn't get it in my inbox. Either way,
Reviewed-by: Conor Dooley <[email protected]>
> ---
> arch/riscv/kernel/cpufeature.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 729f7a218093..08f7445985dc 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -289,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
> u32 cpu_req_feature = 0;
>
> if (cpufeature_probe_svpbmt(stage))
> - cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
> + cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
>
> if (cpufeature_probe_zicbom(stage))
> - cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
> + cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);
>
> return cpu_req_feature;
> }
> --
> 2.35.1
>
On 05/09/2022 15:12, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Montag, 5. September 2022, 13:23:01 CEST schrieb Heiko Stübner:
>> Am Montag, 5. September 2022, 13:19:41 CEST schrieb [email protected]:
>>> On 05/09/2022 12:10, Heiko Stuebner wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> Using the appropriate BIT macro makes the code better readable.
>>>>
>>>> Suggested-by: Conor Dooley <[email protected]>
>>>> Signed-off-by: Heiko Stuebner <[email protected]>
>>>
>>> Missing the cover-letter with the changelog?
>>> At least, I didn't get it in my inbox.
>>
>> darn git send-email and its automatic selection ;-)
>>
>> I.e. I _should_ have added you to the hard recipient list for my series
>> in the first place, but instead git send-email selected you based on
>> the Suggested-by ... but it looks like these selectoions don't get
>> applied to the cover-letter ... sorry about that
>
> For the record, the series is here:
> https://lore.kernel.org/all/[email protected]/
>
> Though right now, I don't see it in the linux-riscv list-archive or my
> own inbox of that list. Maybe infradead has some issue today.
I ended up seeing it in one of my random folders but not my linux-riscv
which is where I checked after it didnt come directly.
>>> Either way,
>>>
>>> Reviewed-by: Conor Dooley <[email protected]>
btw, just noticed - s/marco/macro in the subject...
Conor.
Am Montag, 5. September 2022, 13:23:01 CEST schrieb Heiko St?bner:
> Am Montag, 5. September 2022, 13:19:41 CEST schrieb [email protected]:
> > On 05/09/2022 12:10, Heiko Stuebner wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > Using the appropriate BIT macro makes the code better readable.
> > >
> > > Suggested-by: Conor Dooley <[email protected]>
> > > Signed-off-by: Heiko Stuebner <[email protected]>
> >
> > Missing the cover-letter with the changelog?
> > At least, I didn't get it in my inbox.
>
> darn git send-email and its automatic selection ;-)
>
> I.e. I _should_ have added you to the hard recipient list for my series
> in the first place, but instead git send-email selected you based on
> the Suggested-by ... but it looks like these selectoions don't get
> applied to the cover-letter ... sorry about that
For the record, the series is here:
https://lore.kernel.org/all/[email protected]/
Though right now, I don't see it in the linux-riscv list-archive or my
own inbox of that list. Maybe infradead has some issue today.
>
>
> Heiko
>
>
> > Either way,
> >
> > Reviewed-by: Conor Dooley <[email protected]>
> >
> > > ---
> > > arch/riscv/kernel/cpufeature.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > index 729f7a218093..08f7445985dc 100644
> > > --- a/arch/riscv/kernel/cpufeature.c
> > > +++ b/arch/riscv/kernel/cpufeature.c
> > > @@ -289,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
> > > u32 cpu_req_feature = 0;
> > >
> > > if (cpufeature_probe_svpbmt(stage))
> > > - cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
> > > + cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
> > >
> > > if (cpufeature_probe_zicbom(stage))
> > > - cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
> > > + cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);
> > >
> > > return cpu_req_feature;
> > > }
> > > --
> > > 2.35.1
> > >
> >
> >
>
>
Reviewed-by: Guo Ren <[email protected]>
On Mon, Sep 5, 2022 at 7:10 PM Heiko Stuebner <[email protected]> wrote:
>
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
>
> Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
> Signed-off-by: Heiko Stuebner <[email protected]>
> Reviewed-by: Conor Dooley <[email protected]>
> Reviewed-by: Andrew Jones <[email protected]>
> ---
> arch/riscv/errata/thead/errata.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
> static bool errata_probe_pbmt(unsigned int stage,
> unsigned long arch_id, unsigned long impid)
> {
> + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> + return false;
> +
> if (arch_id != 0 || impid != 0)
> return false;
>
> --
> 2.35.1
>
--
Best Regards
Guo Ren
Reviewed-by: Guo Ren <[email protected]>
On Thu, Sep 8, 2022 at 6:50 AM Atish Patra <[email protected]> wrote:
>
>
>
> On Mon, Sep 5, 2022 at 7:15 AM Heiko Stuebner <[email protected]> wrote:
>>
>> Using the appropriate BIT macro makes the code better readable.
>>
>> Suggested-by: Conor Dooley <[email protected]>
>> Signed-off-by: Heiko Stuebner <[email protected]>
>> ---
>> arch/riscv/kernel/cpufeature.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index 729f7a218093..08f7445985dc 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -289,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
>> u32 cpu_req_feature = 0;
>>
>> if (cpufeature_probe_svpbmt(stage))
>> - cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
>> + cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);
>>
>> if (cpufeature_probe_zicbom(stage))
>> - cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
>> + cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);
>>
>> return cpu_req_feature;
>> }
>> --
>> 2.35.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
>
> Reviewed-by: Atish Patra <[email protected]>
>
> --
> Regards,
> Atish
--
Best Regards
Guo Ren
On Mon, 5 Sep 2022 13:10:22 +0200, Heiko Stuebner wrote:
> As noted by some people, some parts of the recently added extensions
> (svpbmt, zicbom) + t-head errata could use some styling upgrades.
>
> So this series provides these.
>
> changes in v2:
> - add patch also converting cpufeature probe to BIT()
> - update commit message in patch1 (Conor)
>
> [...]
Applied, thanks!
[1/5] riscv: cleanup svpbmt cpufeature probing
https://git.kernel.org/palmer/c/e47bddcb2ec5
[2/5] riscv: drop some idefs from CMO initialization
https://git.kernel.org/palmer/c/f055268e3946
[3/5] riscv: use BIT() macros in t-head errata init
https://git.kernel.org/palmer/c/499590c084f1
[4/5] riscv: use BIT() marco for cpufeature probing
https://git.kernel.org/palmer/c/e283187c034c
[5/5] riscv: check for kernel config option in t-head memory types errata
https://git.kernel.org/palmer/c/14057733109d
Best regards,
--
Palmer Dabbelt <[email protected]>