On 15.11.2023 04:25, Luo Jie wrote:
> For the platform ipq5332, the related GCC clocks need to be enabled
> to make the GPIO reset of the MDIO slave devices taking effect.
>
> Signed-off-by: Luo Jie <[email protected]>
[...]
> static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
> @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus)
> u32 val;
> int ret;
>
> + /* For the platform ipq5332, there are two uniphy available to connect the
> + * ethernet devices, the uniphy gcc clock should be enabled for resetting
> + * the connected device such as qca8386 switch or qca8081 PHY effectively.
> + */
> + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) {
Would that not also be taken care of in the phy driver?
Konrad
On 11/20/2023 10:22 PM, Konrad Dybcio wrote:
> On 15.11.2023 04:25, Luo Jie wrote:
>> For the platform ipq5332, the related GCC clocks need to be enabled
>> to make the GPIO reset of the MDIO slave devices taking effect.
>>
>> Signed-off-by: Luo Jie <[email protected]>
> [...]
>
>> static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
>> @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus)
>> u32 val;
>> int ret;
>>
>> + /* For the platform ipq5332, there are two uniphy available to connect the
>> + * ethernet devices, the uniphy gcc clock should be enabled for resetting
>> + * the connected device such as qca8386 switch or qca8081 PHY effectively.
>> + */
>> + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) {
> Would that not also be taken care of in the phy driver?
>
> Konrad
Hi Konrad,
These clocks are the SOC clocks that is not related to the PHY type.
no matter what kind of PHY is connected, we also need to configure
these clocks.
On Tue, Nov 21, 2023 at 06:28:54PM +0800, Jie Luo wrote:
>
>
> On 11/20/2023 10:22 PM, Konrad Dybcio wrote:
> > On 15.11.2023 04:25, Luo Jie wrote:
> > > For the platform ipq5332, the related GCC clocks need to be enabled
> > > to make the GPIO reset of the MDIO slave devices taking effect.
> > >
> > > Signed-off-by: Luo Jie <[email protected]>
> > [...]
> >
> > > static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
> > > @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus)
> > > u32 val;
> > > int ret;
> > > + /* For the platform ipq5332, there are two uniphy available to connect the
> > > + * ethernet devices, the uniphy gcc clock should be enabled for resetting
> > > + * the connected device such as qca8386 switch or qca8081 PHY effectively.
> > > + */
> > > + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) {
> > Would that not also be taken care of in the phy driver?
> >
> > Konrad
>
> Hi Konrad,
> These clocks are the SOC clocks that is not related to the PHY type.
> no matter what kind of PHY is connected, we also need to configure
> these clocks.
Hi Jie
You can avoid lots of these questions by making your commit message
better. Assume the reader does not know the clock tree for this
device. With a bit of experience, you can guess what reviewers are
going to ask, and answer those questions in the commit message.
Andrew
On 11/21/2023 10:04 PM, Andrew Lunn wrote:
> On Tue, Nov 21, 2023 at 06:28:54PM +0800, Jie Luo wrote:
>>
>>
>> On 11/20/2023 10:22 PM, Konrad Dybcio wrote:
>>> On 15.11.2023 04:25, Luo Jie wrote:
>>>> For the platform ipq5332, the related GCC clocks need to be enabled
>>>> to make the GPIO reset of the MDIO slave devices taking effect.
>>>>
>>>> Signed-off-by: Luo Jie <[email protected]>
>>> [...]
>>>
>>>> static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
>>>> @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus)
>>>> u32 val;
>>>> int ret;
>>>> + /* For the platform ipq5332, there are two uniphy available to connect the
>>>> + * ethernet devices, the uniphy gcc clock should be enabled for resetting
>>>> + * the connected device such as qca8386 switch or qca8081 PHY effectively.
>>>> + */
>>>> + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) {
>>> Would that not also be taken care of in the phy driver?
>>>
>>> Konrad
>>
>> Hi Konrad,
>> These clocks are the SOC clocks that is not related to the PHY type.
>> no matter what kind of PHY is connected, we also need to configure
>> these clocks.
>
> Hi Jie
>
> You can avoid lots of these questions by making your commit message
> better. Assume the reader does not know the clock tree for this
> device. With a bit of experience, you can guess what reviewers are
> going to ask, and answer those questions in the commit message.
>
> Andrew
Hi Andrew,
Got it, will take more attention on the commit message to make the
code clearly in future patches, thanks for the suggestion.