This patchset fixes the following set of coding style
issues found using checkpatch.
ERROR: space prohibited after that open parenthesis '('
ERROR: trailing whitespace
ERROR: space required before the open parenthesis '('
ERROR: space required after that ',' (ctx:VxV)
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '==' (ctx:WxV)
ERROR: that open brace { should be on the previous line
Abdun Nihaal (7):
staging: mt7621-pci: Remove space after open parenthesis
staging: mt7621-pci: remove trailing whitespace
staging: mt7621-pci: add space before open parenthesis
staging: mt7621-pci: add space after comma symbol
staging: mt7621-pci: add spaces around equal symbol
staging: mt7621-pci: add space after '==' symbol
staging: mt7621-pci: fix coding style error
drivers/staging/mt7621-pci/pci-mt7621.c | 114 ++++++++++++------------
1 file changed, 56 insertions(+), 58 deletions(-)
--
2.17.0
This fixes the following checkpatch error:
ERROR: space prohibited after that open parenthesis '('
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1fa41eb8a87f..44f1a592a7a5 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -221,7 +221,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
MV_WRITE(data_reg, *data);
break;
case PCI_ACCESS_READ_1:
- MV_READ_8( data_reg+(where&0x3), data);
+ MV_READ_8(data_reg+(where&0x3), data);
break;
case PCI_ACCESS_READ_2:
MV_READ_16(data_reg+(where&0x3), data);
@@ -663,7 +663,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(500);
#if defined (CONFIG_PCIE_PORT0)
- if(( RALINK_PCI0_STATUS & 0x1) == 0)
+ if((RALINK_PCI0_STATUS & 0x1) == 0)
{
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
@@ -675,7 +675,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT1)
- if(( RALINK_PCI1_STATUS & 0x1) == 0)
+ if((RALINK_PCI1_STATUS & 0x1) == 0)
{
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
@@ -687,7 +687,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT2)
- if (( RALINK_PCI2_STATUS & 0x1) == 0) {
+ if ((RALINK_PCI2_STATUS & 0x1) == 0) {
printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
--
2.17.0
This fixes the following checkpatch error:
ERROR: trailing whitespace
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 32 ++++++++++++-------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 44f1a592a7a5..fbcee58445b3 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -498,7 +498,7 @@ set_phy_for_ssc(void)
printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
- if (reg >= 6) {
+ if (reg >= 6) {
printk("***** Xtal 25MHz *****\n");
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
@@ -510,15 +510,15 @@ set_phy_for_ssc(void)
}
}
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
/* Enable PHY and disable force mode */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
@@ -546,15 +546,15 @@ set_phy_for_ssc(void)
}
}
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
/* Enable PHY and disable force mode */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
@@ -650,7 +650,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCIE_CLK_GEN |= 0x80000000;
mdelay(50);
RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
-
+
#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
--
2.17.0
This fixes the following checkpatch error:
ERROR: spaces required around that '==' (ctx:WxV)
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 3bd715a4b139..510aa633589a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -417,13 +417,13 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
irq = RALINK_INT_PCIE1;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
- } else if ((dev->bus->number ==3) && (slot == 0x0)) {
+ } else if ((dev->bus->number == 3) && (slot == 0x0)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
- } else if ((dev->bus->number ==3) && (slot == 0x1)) {
+ } else if ((dev->bus->number == 3) && (slot == 0x1)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
- } else if ((dev->bus->number ==3) && (slot == 0x2)) {
+ } else if ((dev->bus->number == 3) && (slot == 0x2)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else {
--
2.17.0
This fixes the following checkpatch error:
ERROR: spaces required around that '=' (ctx:VxW)
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index f347eaf9063c..3bd715a4b139 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -308,7 +308,7 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
}
}
-struct pci_ops mt7621_pci_ops= {
+struct pci_ops mt7621_pci_ops = {
.read = pci_config_read,
.write = pci_config_write,
};
@@ -584,8 +584,8 @@ static int mt7621_pci_probe(struct platform_device *pdev)
unsigned long val = 0;
iomem_resource.start = 0;
- iomem_resource.end= ~0;
- ioport_resource.start= 0;
+ iomem_resource.end = ~0;
+ ioport_resource.start = 0;
ioport_resource.end = ~0;
#if defined (CONFIG_PCIE_PORT0)
--
2.17.0
This patch fixes the following checkpatch error:
ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 36 ++++++++++++-------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 28b9a11e9ecb..f347eaf9063c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -373,17 +373,17 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 0 = %x\n", val);
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
} else if ((dev->bus->number == 0) && (slot == 0x1)) {
write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 1 = %x\n", val);
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
} else if ((dev->bus->number == 0) && (slot == 0x2)) {
write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 2 = %x\n", val);
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
} else if ((dev->bus->number == 1) && (slot == 0x0)) {
switch (pcie_link_status) {
case 2:
@@ -396,7 +396,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
default:
irq = RALINK_INT_PCIE0;
}
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x0)) {
switch (pcie_link_status) {
case 5:
@@ -406,7 +406,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
default:
irq = RALINK_INT_PCIE1;
}
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x1)) {
switch (pcie_link_status) {
case 5:
@@ -416,18 +416,18 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
default:
irq = RALINK_INT_PCIE1;
}
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x0)) {
irq = RALINK_INT_PCIE2;
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x1)) {
irq = RALINK_INT_PCIE2;
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x2)) {
irq = RALINK_INT_PCIE2;
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else {
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
return 0;
}
@@ -501,10 +501,10 @@ set_phy_for_ssc(void)
if (reg >= 6) {
printk("***** Xtal 25MHz *****\n");
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
} else {
printk("***** Xtal 20MHz *****\n");
}
@@ -539,10 +539,10 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) { // 25MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
}
}
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
--
2.17.0
This fixes the following checkpatch error:
ERROR: space required before the open parenthesis '('
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++++++++++++-------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index fbcee58445b3..28b9a11e9ecb 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -155,13 +155,13 @@ extern void chk_phy_pll(void);
RALINK_RSTCTRL |= val; \
else \
RALINK_RSTCTRL &= ~val; \
- } while(0)
+ } while (0)
#define DEASSERT_SYSRST_PCIE(val) do { \
if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
RALINK_RSTCTRL &= ~val; \
else \
RALINK_RSTCTRL |= val; \
- } while(0)
+ } while (0)
#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
@@ -210,7 +210,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
MV_WRITE(address_reg, address);
- switch(access_type) {
+ switch (access_type) {
case PCI_ACCESS_WRITE_1:
MV_WRITE_8(data_reg+(where&0x3), *data);
break;
@@ -374,12 +374,12 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 0 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
- } else if((dev->bus->number == 0) && (slot == 0x1)) {
+ } else if ((dev->bus->number == 0) && (slot == 0x1)) {
write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 1 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
- } else if((dev->bus->number == 0) && (slot == 0x2)) {
+ } else if ((dev->bus->number == 0) && (slot == 0x2)) {
write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 2 = %x\n", val);
@@ -493,7 +493,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal
@@ -516,7 +516,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
@@ -533,7 +533,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
} else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
@@ -552,7 +552,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
@@ -663,7 +663,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(500);
#if defined (CONFIG_PCIE_PORT0)
- if((RALINK_PCI0_STATUS & 0x1) == 0)
+ if ((RALINK_PCI0_STATUS & 0x1) == 0)
{
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
@@ -675,7 +675,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT1)
- if((RALINK_PCI1_STATUS & 0x1) == 0)
+ if ((RALINK_PCI1_STATUS & 0x1) == 0)
{
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
@@ -711,7 +711,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
3'b110 1 0 x
3'b111 2 1 0
*/
- switch(pcie_link_status) {
+ switch (pcie_link_status) {
case 2:
RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
@@ -749,7 +749,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
#if defined (CONFIG_PCIE_PORT0)
//PCIe0
- if((pcie_link_status & 0x1) != 0) {
+ if ((pcie_link_status & 0x1) != 0) {
RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
RALINK_PCI0_CLASS = 0x06040001;
@@ -776,7 +776,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
#endif
- switch(pcie_link_status) {
+ switch (pcie_link_status) {
case 7:
read_config(0, 2, 0, 0x4, &val);
write_config(0, 2, 0, 0x4, val|0x4);
--
2.17.0
This fixes the following checkpatch error:
ERROR: that open brace { should be on the previous line
Signed-off-by: Abdun Nihaal <[email protected]>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 510aa633589a..96cae1e1838b 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -663,8 +663,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(500);
#if defined (CONFIG_PCIE_PORT0)
- if ((RALINK_PCI0_STATUS & 0x1) == 0)
- {
+ if ((RALINK_PCI0_STATUS & 0x1) == 0) {
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
@@ -675,8 +674,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT1)
- if ((RALINK_PCI1_STATUS & 0x1) == 0)
- {
+ if ((RALINK_PCI1_STATUS & 0x1) == 0) {
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
--
2.17.0
On Sun, Jun 03 2018, Abdun Nihaal wrote:
> This patchset fixes the following set of coding style
> issues found using checkpatch.
>
> ERROR: space prohibited after that open parenthesis '('
> ERROR: trailing whitespace
> ERROR: space required before the open parenthesis '('
> ERROR: space required after that ',' (ctx:VxV)
> ERROR: spaces required around that '=' (ctx:VxW)
> ERROR: spaces required around that '==' (ctx:WxV)
> ERROR: that open brace { should be on the previous line
Hi,
thanks for contributing these, how ever some of these issues have
already been address (not all). I think you must be working from an
old try.
When submitting patches to drives/staging, they should be based on
the staging-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
Also, I'd suggest leaving linux-arm-kernel and linux-mediatek off the
cc list. They are unlikely to be interested until the driver is ready
to be moved out of drivers/staging.
Thanks,
NeilBrown
>
> Abdun Nihaal (7):
> staging: mt7621-pci: Remove space after open parenthesis
> staging: mt7621-pci: remove trailing whitespace
> staging: mt7621-pci: add space before open parenthesis
> staging: mt7621-pci: add space after comma symbol
> staging: mt7621-pci: add spaces around equal symbol
> staging: mt7621-pci: add space after '==' symbol
> staging: mt7621-pci: fix coding style error
>
> drivers/staging/mt7621-pci/pci-mt7621.c | 114 ++++++++++++------------
> 1 file changed, 56 insertions(+), 58 deletions(-)
>
> --
> 2.17.0