Hi,
This patchset adds support for pwm clock. At boot, this clock does not have a
default parent nor a default rate set. Thus we should be able to change its
parent to get this clock working. The current clock implementation is using a
mux to select the parent, but these clocks need to add a password (0x5a) in
higher register bits when changing parent. So a generic mux cannot be used
here.
The two first patches fix the clock parent selection, while the last ones are
actually adding the pwm clock registration.
Changes since v1:
- determine_rate now based its parent selection upon divided rate
instead of the parent one
- bcm2835_clock_choose_div has been modified to produce an avarage rate
lower or equal to the requested one
- devicetree modifications have removed to be send in another patch
Changes since v2:
- Remove useless variable and include
- Make bcm2835_clock_choose_div() divisor round up ability optional
- Set rate in bcm2835_determine_rate()
- Add device tree modification in a separate patch
Remi Pommarel (4):
clk: bcm2835: add a round up ability to the clock divisor
clk: bcm2835: Support for clock parent selection
clk: bcm2835: Add PWM clock support
clk: bcm2835: Add PWM clock support to the device tree
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +
arch/arm/boot/dts/bcm2835.dtsi | 9 +++
drivers/clk/bcm/clk-bcm2835.c | 155 +++++++++++++++++++++++-------------
include/dt-bindings/clock/bcm2835.h | 3 +-
4 files changed, 116 insertions(+), 55 deletions(-)
--
2.0.1
Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor
so that the resulting average rate will not be higher than the requested one.
Signed-off-by: Remi Pommarel <[email protected]>
---
drivers/clk/bcm/clk-bcm2835.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 39bf582..9e881ee 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1148,22 +1148,24 @@ static int bcm2835_clock_is_on(struct clk_hw *hw)
static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
unsigned long rate,
- unsigned long parent_rate)
+ unsigned long parent_rate,
+ bool round_up)
{
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
const struct bcm2835_clock_data *data = clock->data;
- u32 unused_frac_mask = GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0);
+ u32 unused_frac_mask =
+ GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
+ u64 rem;
u32 div;
- do_div(temp, rate);
+ rem = do_div(temp, rate);
div = temp;
- /* Round and mask off the unused bits */
- if (unused_frac_mask != 0) {
- div += unused_frac_mask >> 1;
- div &= ~unused_frac_mask;
- }
+ /* Round up and mask off the unused bits */
+ if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
+ div += unused_frac_mask + 1;
+ div &= ~unused_frac_mask;
/* Clamp to the limits. */
div = max(div, unused_frac_mask + 1);
@@ -1202,7 +1204,7 @@ static long bcm2835_clock_round_rate(struct clk_hw *hw,
unsigned long *parent_rate)
{
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
- u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);
+ u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate, false);
return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
}
@@ -1271,7 +1273,7 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
struct bcm2835_cprman *cprman = clock->cprman;
const struct bcm2835_clock_data *data = clock->data;
- u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
+ u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
cprman_write(cprman, data->div_reg, div);
--
2.0.1
Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
parent clocks. These clocks divide the rate of a parent which can be selected by
setting the proper bits in the clock control register.
Previously all these parents where handled by a mux clock. But a mux clock
cannot be used because updating clock control register to select parent needs a
password to be xor'd with the parent index.
This patch get rid of mux clock and make these clocks handle their own parent,
allowing them to select the one to use.
Signed-off-by: Remi Pommarel <[email protected]>
---
drivers/clk/bcm/clk-bcm2835.c | 122 ++++++++++++++++++++++++++----------------
1 file changed, 77 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 9e881ee..6e4dd6f 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1199,16 +1199,6 @@ static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
return temp;
}
-static long bcm2835_clock_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
-{
- struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
- u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate, false);
-
- return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
-}
-
static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -1280,13 +1270,75 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
return 0;
}
+static int bcm2835_clock_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ struct clk_hw *parent, *best_parent = NULL;
+ unsigned long rate, best_rate = 0;
+ unsigned long prate, best_prate = 0;
+ size_t i;
+ u32 div;
+
+ /*
+ * Select parent clock that results in the closest but lower rate
+ */
+ for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
+ parent = clk_hw_get_parent_by_index(hw, i);
+ if (!parent)
+ continue;
+ prate = clk_hw_get_rate(parent);
+ div = bcm2835_clock_choose_div(hw, req->rate, prate, true);
+ rate = bcm2835_clock_rate_from_divisor(clock, prate, div);
+ if (rate > best_rate && rate <= req->rate) {
+ best_parent = parent;
+ best_prate = prate;
+ best_rate = rate;
+ }
+ }
+
+ if (!best_parent)
+ return -EINVAL;
+
+ req->best_parent_hw = best_parent;
+ req->best_parent_rate = best_prate;
+
+ req->rate = best_rate;
+
+ return 0;
+}
+
+static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ struct bcm2835_cprman *cprman = clock->cprman;
+ const struct bcm2835_clock_data *data = clock->data;
+ u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
+
+ cprman_write(cprman, data->ctl_reg, src);
+ return 0;
+}
+
+static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
+{
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ struct bcm2835_cprman *cprman = clock->cprman;
+ const struct bcm2835_clock_data *data = clock->data;
+ u32 src = cprman_read(cprman, data->ctl_reg);
+
+ return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
+}
+
+
static const struct clk_ops bcm2835_clock_clk_ops = {
.is_prepared = bcm2835_clock_is_on,
.prepare = bcm2835_clock_on,
.unprepare = bcm2835_clock_off,
.recalc_rate = bcm2835_clock_get_rate,
.set_rate = bcm2835_clock_set_rate,
- .round_rate = bcm2835_clock_round_rate,
+ .determine_rate = bcm2835_clock_determine_rate,
+ .set_parent = bcm2835_clock_set_parent,
+ .get_parent = bcm2835_clock_get_parent,
};
static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
@@ -1302,7 +1354,9 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
.is_prepared = bcm2835_vpu_clock_is_on,
.recalc_rate = bcm2835_clock_get_rate,
.set_rate = bcm2835_clock_set_rate,
- .round_rate = bcm2835_clock_round_rate,
+ .determine_rate = bcm2835_clock_determine_rate,
+ .set_parent = bcm2835_clock_set_parent,
+ .get_parent = bcm2835_clock_get_parent,
};
static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
@@ -1396,45 +1450,23 @@ static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman,
{
struct bcm2835_clock *clock;
struct clk_init_data init;
- const char *parent;
+ const char *parents[1 << CM_SRC_BITS];
+ size_t i;
/*
- * Most of the clock generators have a mux field, so we
- * instantiate a generic mux as our parent to handle it.
+ * Replace our "xosc" references with the oscillator's
+ * actual name.
*/
- if (data->num_mux_parents) {
- const char *parents[1 << CM_SRC_BITS];
- int i;
-
- parent = devm_kasprintf(cprman->dev, GFP_KERNEL,
- "mux_%s", data->name);
- if (!parent)
- return NULL;
-
- /*
- * Replace our "xosc" references with the oscillator's
- * actual name.
- */
- for (i = 0; i < data->num_mux_parents; i++) {
- if (strcmp(data->parents[i], "xosc") == 0)
- parents[i] = cprman->osc_name;
- else
- parents[i] = data->parents[i];
- }
-
- clk_register_mux(cprman->dev, parent,
- parents, data->num_mux_parents,
- CLK_SET_RATE_PARENT,
- cprman->regs + data->ctl_reg,
- CM_SRC_SHIFT, CM_SRC_BITS,
- 0, &cprman->regs_lock);
- } else {
- parent = data->parents[0];
+ for (i = 0; i < data->num_mux_parents; i++) {
+ if (strcmp(data->parents[i], "xosc") == 0)
+ parents[i] = cprman->osc_name;
+ else
+ parents[i] = data->parents[i];
}
memset(&init, 0, sizeof(init));
- init.parent_names = &parent;
- init.num_parents = 1;
+ init.parent_names = parents;
+ init.num_parents = data->num_mux_parents;
init.name = data->name;
init.flags = CLK_IGNORE_UNUSED;
--
2.0.1
Register the pwm clock for bcm2835.
Signed-off-by: Remi Pommarel <[email protected]>
---
drivers/clk/bcm/clk-bcm2835.c | 13 +++++++++++++
include/dt-bindings/clock/bcm2835.h | 3 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 6e4dd6f..015e687 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -807,6 +807,16 @@ static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
.frac_bits = 8,
};
+static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
+ .name = "pwm",
+ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
+ .parents = bcm2835_clock_per_parents,
+ .ctl_reg = CM_PWMCTL,
+ .div_reg = CM_PWMDIV,
+ .int_bits = 12,
+ .frac_bits = 12,
+};
+
struct bcm2835_pll {
struct clk_hw hw;
struct bcm2835_cprman *cprman;
@@ -1584,6 +1594,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
cprman->regs + CM_PERIICTL, CM_GATE_BIT,
0, &cprman->regs_lock);
+ clks[BCM2835_CLOCK_PWM] =
+ bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
+
return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
&cprman->onecell);
}
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index d323efa..61f1d20 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -43,5 +43,6 @@
#define BCM2835_CLOCK_TSENS 27
#define BCM2835_CLOCK_EMMC 28
#define BCM2835_CLOCK_PERI_IMAGE 29
+#define BCM2835_CLOCK_PWM 30
-#define BCM2835_CLOCK_COUNT 30
+#define BCM2835_CLOCK_COUNT 31
--
2.0.1
Signed-off-by: Remi Pommarel <[email protected]>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 ++++
arch/arm/boot/dts/bcm2835.dtsi | 9 +++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 3572f03..55801e0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -60,3 +60,7 @@
status = "okay";
bus-width = <4>;
};
+
+&pwm {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index aef64de..641f7f4 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -149,6 +149,15 @@
status = "disabled";
};
+ pwm: pwm@7e20c000 {
+ compatible = "brcm,bcm2835-pwm";
+ reg = <0x7e20c000 0x28>;
+ clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clock-rates = <10000000>;
+ status = "disabled";
+ };
+
sdhci: sdhci@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
--
2.0.1
Hi Remi,
please send this patch to [email protected].
Am 06.12.2015 um 17:22 schrieb Remi Pommarel:
> Signed-off-by: Remi Pommarel <[email protected]>
> ---
> arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 ++++
> arch/arm/boot/dts/bcm2835.dtsi | 9 +++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
> index 3572f03..55801e0 100644
> --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
> +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
> @@ -60,3 +60,7 @@
> status = "okay";
> bus-width = <4>;
> };
> +
> +&pwm {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
> index aef64de..641f7f4 100644
> --- a/arch/arm/boot/dts/bcm2835.dtsi
> +++ b/arch/arm/boot/dts/bcm2835.dtsi
> @@ -149,6 +149,15 @@
> status = "disabled";
> };
>
> + pwm: pwm@7e20c000 {
> + compatible = "brcm,bcm2835-pwm";
> + reg = <0x7e20c000 0x28>;
> + clocks = <&clocks BCM2835_CLOCK_PWM>;
Looks like #pwm-cells is missing.
Regards
Stefan
> + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
> + assigned-clock-rates = <10000000>;
> + status = "disabled";
> + };
> +
> sdhci: sdhci@7e300000 {
> compatible = "brcm,bcm2835-sdhci";
> reg = <0x7e300000 0x100>;
>
Hi Stefan,
On Sun, Dec 06, 2015 at 10:16:25PM +0100, Stefan Wahren wrote:
> Hi Remi,
>
> please send this patch to [email protected].
Ok, just to be sure I understand the process here. I should resend a new
version of the whole patchset including the devicetree mailing list as
recipent. Then the first 3 patches will eventually get pushed by a clock
subsystem maintainer. And finally this last patch will be pushed by a
devicetree maintainer.
Am I right here ?
>
> Am 06.12.2015 um 17:22 schrieb Remi Pommarel:
> >Signed-off-by: Remi Pommarel <[email protected]>
> >---
> > arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 ++++
> > arch/arm/boot/dts/bcm2835.dtsi | 9 +++++++++
> > 2 files changed, 13 insertions(+)
> >
> >diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
> >index 3572f03..55801e0 100644
> >--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
> >+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
> >@@ -60,3 +60,7 @@
> > status = "okay";
> > bus-width = <4>;
> > };
> >+
> >+&pwm {
> >+ status = "okay";
> >+};
> >diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
> >index aef64de..641f7f4 100644
> >--- a/arch/arm/boot/dts/bcm2835.dtsi
> >+++ b/arch/arm/boot/dts/bcm2835.dtsi
> >@@ -149,6 +149,15 @@
> > status = "disabled";
> > };
> >
> >+ pwm: pwm@7e20c000 {
> >+ compatible = "brcm,bcm2835-pwm";
> >+ reg = <0x7e20c000 0x28>;
> >+ clocks = <&clocks BCM2835_CLOCK_PWM>;
>
> Looks like #pwm-cells is missing.
>
Yes will do. Thank you.
Regards
--
Remi
Hi Remi,
Am 07.12.2015 um 19:17 schrieb Remi Pommarel:
> Hi Stefan,
>
> On Sun, Dec 06, 2015 at 10:16:25PM +0100, Stefan Wahren wrote:
>> Hi Remi,
>>
>> please send this patch to [email protected].
>
> Ok, just to be sure I understand the process here. I should resend a new
> version of the whole patchset including the devicetree mailing list as
> recipent. Then the first 3 patches will eventually get pushed by a clock
> subsystem maintainer. And finally this last patch will be pushed by a
> devicetree maintainer.
>
> Am I right here ?
sorry for the confusion. I mean that you send a copy to
[email protected] so subscribers have a chance to review.
I'm not sure but according to your subject you suggest that this dts
patch should go through clock subsystem which isn't optimal. This should
be better applied by Stephen or Eric.
Best regards
Stefan
Remi Pommarel <[email protected]> writes:
> Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor
> so that the resulting average rate will not be higher than the requested one.
>
> Signed-off-by: Remi Pommarel <[email protected]>
> ---
> drivers/clk/bcm/clk-bcm2835.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 39bf582..9e881ee 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1148,22 +1148,24 @@ static int bcm2835_clock_is_on(struct clk_hw *hw)
>
> static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
> unsigned long rate,
> - unsigned long parent_rate)
> + unsigned long parent_rate,
> + bool round_up)
> {
> struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
> const struct bcm2835_clock_data *data = clock->data;
> - u32 unused_frac_mask = GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0);
> + u32 unused_frac_mask =
> + GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
> u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
> + u64 rem;
> u32 div;
>
> - do_div(temp, rate);
> + rem = do_div(temp, rate);
> div = temp;
>
> - /* Round and mask off the unused bits */
> - if (unused_frac_mask != 0) {
> - div += unused_frac_mask >> 1;
> - div &= ~unused_frac_mask;
> - }
> + /* Round up and mask off the unused bits */
> + if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
> + div += unused_frac_mask + 1;
> + div &= ~unused_frac_mask;
>
> /* Clamp to the limits. */
> div = max(div, unused_frac_mask + 1);
> @@ -1202,7 +1204,7 @@ static long bcm2835_clock_round_rate(struct clk_hw *hw,
> unsigned long *parent_rate)
> {
> struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
> - u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);
> + u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate, false);
>
> return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
> }
> @@ -1271,7 +1273,7 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
> struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
> struct bcm2835_cprman *cprman = clock->cprman;
> const struct bcm2835_clock_data *data = clock->data;
> - u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
> + u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
I think you meant ", true" on one of these. With that fixed,
Reviewed-by: Eric Anholt <[email protected]>
Remi Pommarel <[email protected]> writes:
> Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
> parent clocks. These clocks divide the rate of a parent which can be selected by
> setting the proper bits in the clock control register.
>
> Previously all these parents where handled by a mux clock. But a mux clock
> cannot be used because updating clock control register to select parent needs a
> password to be xor'd with the parent index.
>
> This patch get rid of mux clock and make these clocks handle their own parent,
> allowing them to select the one to use.
I see, you use the new flag now in this patch. I take back the comment
on the previous patch.
Patches 1-3 are:
Reviewed-by: Eric Anholt <[email protected]>
and I think they're ready to go in the clock tree, even while the DT for
setting up the bcm2835-pwm driver is being reviewed on the DT list.
Stefan Wahren <[email protected]> writes:
> Hi Remi,
>
> Am 07.12.2015 um 19:17 schrieb Remi Pommarel:
>> Hi Stefan,
>>
>> On Sun, Dec 06, 2015 at 10:16:25PM +0100, Stefan Wahren wrote:
>>> Hi Remi,
>>>
>>> please send this patch to [email protected].
>>
>> Ok, just to be sure I understand the process here. I should resend a new
>> version of the whole patchset including the devicetree mailing list as
>> recipent. Then the first 3 patches will eventually get pushed by a clock
>> subsystem maintainer. And finally this last patch will be pushed by a
>> devicetree maintainer.
>>
>> Am I right here ?
>
> sorry for the confusion. I mean that you send a copy to
> [email protected] so subscribers have a chance to review.
>
> I'm not sure but according to your subject you suggest that this dts
> patch should go through clock subsystem which isn't optimal. This should
> be better applied by Stephen or Eric.
It would be applied by me, but that's for me to worry about, not the
patch submitter. The subject prefix would be "ARM: bcm2835: ", but
that's trivial for me to fix when applying, not the kind of thing worth
asking for a respin for.
On Mon, Dec 07, 2015 at 08:09:47PM -0800, Eric Anholt wrote:
> Stefan Wahren <[email protected]> writes:
>
> > Hi Remi,
> >
> > Am 07.12.2015 um 19:17 schrieb Remi Pommarel:
> >> Hi Stefan,
> >>
> >> On Sun, Dec 06, 2015 at 10:16:25PM +0100, Stefan Wahren wrote:
> >>> Hi Remi,
> >>>
> >>> please send this patch to [email protected].
> >>
> >> Ok, just to be sure I understand the process here. I should resend a new
> >> version of the whole patchset including the devicetree mailing list as
> >> recipent. Then the first 3 patches will eventually get pushed by a clock
> >> subsystem maintainer. And finally this last patch will be pushed by a
> >> devicetree maintainer.
> >>
> >> Am I right here ?
> >
> > sorry for the confusion. I mean that you send a copy to
> > [email protected] so subscribers have a chance to review.
> >
> > I'm not sure but according to your subject you suggest that this dts
> > patch should go through clock subsystem which isn't optimal. This should
> > be better applied by Stephen or Eric.
>
> It would be applied by me, but that's for me to worry about, not the
> patch submitter. The subject prefix would be "ARM: bcm2835: ", but
> that's trivial for me to fix when applying, not the kind of thing worth
> asking for a respin for.
Thanks for review.
I'll submit dt patch to [email protected] for review. Is it better
to submit the whole patchset (patch 1 to 4) to provide some context for the
device tree patch or just this patch alone ?
Best Regards,
--
Remi
Remi Pommarel <[email protected]> writes:
> On Mon, Dec 07, 2015 at 08:09:47PM -0800, Eric Anholt wrote:
>> Stefan Wahren <[email protected]> writes:
>>
>> > Hi Remi,
>> >
>> > Am 07.12.2015 um 19:17 schrieb Remi Pommarel:
>> >> Hi Stefan,
>> >>
>> >> On Sun, Dec 06, 2015 at 10:16:25PM +0100, Stefan Wahren wrote:
>> >>> Hi Remi,
>> >>>
>> >>> please send this patch to [email protected].
>> >>
>> >> Ok, just to be sure I understand the process here. I should resend a new
>> >> version of the whole patchset including the devicetree mailing list as
>> >> recipent. Then the first 3 patches will eventually get pushed by a clock
>> >> subsystem maintainer. And finally this last patch will be pushed by a
>> >> devicetree maintainer.
>> >>
>> >> Am I right here ?
>> >
>> > sorry for the confusion. I mean that you send a copy to
>> > [email protected] so subscribers have a chance to review.
>> >
>> > I'm not sure but according to your subject you suggest that this dts
>> > patch should go through clock subsystem which isn't optimal. This should
>> > be better applied by Stephen or Eric.
>>
>> It would be applied by me, but that's for me to worry about, not the
>> patch submitter. The subject prefix would be "ARM: bcm2835: ", but
>> that's trivial for me to fix when applying, not the kind of thing worth
>> asking for a respin for.
>
> Thanks for review.
>
> I'll submit dt patch to [email protected] for review. Is it better
> to submit the whole patchset (patch 1 to 4) to provide some context for the
> device tree patch or just this patch alone ?
I think you're fine sending just patch 4 -- the clk-bcm2835.c bugfixes
are between us and the clk maintainers, as far as I know. Check
scripts/get_maintainer.pl output to see who all should get the CC on it.
On Sun, Dec 06, 2015 at 05:22:45PM +0100, Remi Pommarel wrote:
> Hi,
>
> This patchset adds support for pwm clock. At boot, this clock does not have a
> default parent nor a default rate set. Thus we should be able to change its
> parent to get this clock working. The current clock implementation is using a
> mux to select the parent, but these clocks need to add a password (0x5a) in
> higher register bits when changing parent. So a generic mux cannot be used
> here.
>
> The two first patches fix the clock parent selection, while the last ones are
> actually adding the pwm clock registration.
>
> Changes since v1:
> - determine_rate now based its parent selection upon divided rate
> instead of the parent one
> - bcm2835_clock_choose_div has been modified to produce an avarage rate
> lower or equal to the requested one
> - devicetree modifications have removed to be send in another patch
>
> Changes since v2:
> - Remove useless variable and include
> - Make bcm2835_clock_choose_div() divisor round up ability optional
> - Set rate in bcm2835_determine_rate()
> - Add device tree modification in a separate patch
>
>
> Remi Pommarel (4):
> clk: bcm2835: add a round up ability to the clock divisor
> clk: bcm2835: Support for clock parent selection
> clk: bcm2835: Add PWM clock support
> clk: bcm2835: Add PWM clock support to the device tree
>
> arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +
> arch/arm/boot/dts/bcm2835.dtsi | 9 +++
> drivers/clk/bcm/clk-bcm2835.c | 155 +++++++++++++++++++++++-------------
> include/dt-bindings/clock/bcm2835.h | 3 +-
> 4 files changed, 116 insertions(+), 55 deletions(-)
>
Gently ping.
Patches 0 to 3 are reviewed by Eric, and can eventually be pushed on clk
tree.
Patch 4 has been sent on devicetree mailinglist for review
(http://www.spinics.net/lists/devicetree/msg108070.html), waiting for
previous patches to be pushed.
Thanks
--
Remi
On 12/23, Remi Pommarel wrote:
> On Sun, Dec 06, 2015 at 05:22:45PM +0100, Remi Pommarel wrote:
> > Hi,
> >
> > This patchset adds support for pwm clock. At boot, this clock does not have a
> > default parent nor a default rate set. Thus we should be able to change its
> > parent to get this clock working. The current clock implementation is using a
> > mux to select the parent, but these clocks need to add a password (0x5a) in
> > higher register bits when changing parent. So a generic mux cannot be used
> > here.
> >
> > The two first patches fix the clock parent selection, while the last ones are
> > actually adding the pwm clock registration.
> >
> > Changes since v1:
> > - determine_rate now based its parent selection upon divided rate
> > instead of the parent one
> > - bcm2835_clock_choose_div has been modified to produce an avarage rate
> > lower or equal to the requested one
> > - devicetree modifications have removed to be send in another patch
> >
> > Changes since v2:
> > - Remove useless variable and include
> > - Make bcm2835_clock_choose_div() divisor round up ability optional
> > - Set rate in bcm2835_determine_rate()
> > - Add device tree modification in a separate patch
> >
> >
> > Remi Pommarel (4):
> > clk: bcm2835: add a round up ability to the clock divisor
> > clk: bcm2835: Support for clock parent selection
> > clk: bcm2835: Add PWM clock support
> > clk: bcm2835: Add PWM clock support to the device tree
> >
> > arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +
> > arch/arm/boot/dts/bcm2835.dtsi | 9 +++
> > drivers/clk/bcm/clk-bcm2835.c | 155 +++++++++++++++++++++++-------------
> > include/dt-bindings/clock/bcm2835.h | 3 +-
> > 4 files changed, 116 insertions(+), 55 deletions(-)
> >
>
> Gently ping.
>
> Patches 0 to 3 are reviewed by Eric, and can eventually be pushed on clk
> tree.
Patches 1-3 applied to clk-next towards 4.5.
>
> Patch 4 has been sent on devicetree mailinglist for review
> (http://www.spinics.net/lists/devicetree/msg108070.html), waiting for
> previous patches to be pushed.
Sounds good.
Regards,
Mike
>
> Thanks
>
> --
> Remi