This patch adds ACP5x PCM driver DMA operations.
Signed-off-by: Vijendar Mukunda <[email protected]>
---
sound/soc/amd/vangogh/acp5x-pcm-dma.c | 306 +++++++++++++++++++++++++-
sound/soc/amd/vangogh/acp5x.h | 106 +++++++++
2 files changed, 410 insertions(+), 2 deletions(-)
diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
index d79712587d30..a4235cf33548 100644
--- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
+++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
@@ -17,8 +17,42 @@
#define DRV_NAME "acp5x_i2s_dma"
-static const struct snd_soc_component_driver acp5x_i2s_component = {
- .name = DRV_NAME,
+static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
+ .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
+ .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
+ .periods_min = PLAYBACK_MIN_NUM_PERIODS,
+ .periods_max = PLAYBACK_MAX_NUM_PERIODS,
+};
+
+static const struct snd_pcm_hardware acp5x_pcm_hardware_capture = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
+ .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
+ .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
+ .periods_min = CAPTURE_MIN_NUM_PERIODS,
+ .periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
@@ -68,6 +102,274 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
return IRQ_NONE;
}
+static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
+{
+ u16 page_idx;
+ u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
+ u32 reg_dma_size, reg_fifo_size;
+ dma_addr_t addr;
+
+ addr = rtd->dma_addr;
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ val = ACP_SRAM_HS_PB_PTE_OFFSET;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ val = ACP_SRAM_SP_PB_PTE_OFFSET;
+ }
+ } else {
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ val = ACP_SRAM_HS_CP_PTE_OFFSET;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ val = ACP_SRAM_SP_CP_PTE_OFFSET;
+ }
+ }
+ /* Group Enable */
+ acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
+ ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
+ acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
+ ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
+
+ for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
+ /* Load the low address of page int ACP SRAM through SRBM */
+ low = lower_32_bits(addr);
+ high = upper_32_bits(addr);
+
+ acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
+ high |= BIT(31);
+ acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val
+ + 4);
+ /* Move to next physically contiguous page */
+ val += 8;
+ addr += PAGE_SIZE;
+ }
+
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ reg_dma_size = ACP_HS_TX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ HS_PB_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = ACP_HS_TX_FIFOADDR;
+ reg_fifo_size = ACP_HS_TX_FIFOSIZE;
+ acp_writel(I2S_HS_TX_MEM_WINDOW_START,
+ rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
+ break;
+
+ case I2S_SP_INSTANCE:
+ default:
+ reg_dma_size = ACP_I2S_TX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ SP_PB_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
+ reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
+ acp_writel(I2S_SP_TX_MEM_WINDOW_START,
+ rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
+ }
+ } else {
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ reg_dma_size = ACP_HS_RX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ HS_CAPT_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = ACP_HS_RX_FIFOADDR;
+ reg_fifo_size = ACP_HS_RX_FIFOSIZE;
+ acp_writel(I2S_HS_RX_MEM_WINDOW_START,
+ rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
+ break;
+
+ case I2S_SP_INSTANCE:
+ default:
+ reg_dma_size = ACP_I2S_RX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ SP_CAPT_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
+ reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
+ acp_writel(I2S_SP_RX_MEM_WINDOW_START,
+ rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
+ }
+ }
+ acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
+ acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
+ acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
+ acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
+ | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
+ rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
+}
+
+static int acp5x_dma_open(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime;
+ struct snd_soc_pcm_runtime *prtd;
+ struct i2s_dev_data *adata;
+ struct i2s_stream_instance *i2s_data;
+ int ret;
+
+ runtime = substream->runtime;
+ prtd = asoc_substream_to_rtd(substream);
+ component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+ adata = dev_get_drvdata(component->dev);
+
+ i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
+ if (!i2s_data)
+ return -EINVAL;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ runtime->hw = acp5x_pcm_hardware_playback;
+ else
+ runtime->hw = acp5x_pcm_hardware_capture;
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0) {
+ dev_err(component->dev, "set integer constraint failed\n");
+ kfree(i2s_data);
+ return ret;
+ }
+ i2s_data->acp5x_base = adata->acp5x_base;
+ runtime->private_data = i2s_data;
+ return ret;
+}
+
+static int acp5x_dma_hw_params(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct i2s_stream_instance *rtd;
+ struct snd_soc_pcm_runtime *prtd;
+ struct snd_soc_card *card;
+ struct acp5x_platform_info *pinfo;
+ struct i2s_dev_data *adata;
+ u64 size;
+
+ prtd = asoc_substream_to_rtd(substream);
+ card = prtd->card;
+ pinfo = snd_soc_card_get_drvdata(card);
+ adata = dev_get_drvdata(component->dev);
+ rtd = substream->runtime->private_data;
+
+ if (!rtd)
+ return -EINVAL;
+
+ if (pinfo) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ rtd->i2s_instance = pinfo->play_i2s_instance;
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ adata->play_stream = substream;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ adata->i2ssp_play_stream = substream;
+ }
+ } else {
+ rtd->i2s_instance = pinfo->cap_i2s_instance;
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ adata->capture_stream = substream;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ adata->i2ssp_capture_stream = substream;
+ }
+ }
+ } else {
+ pr_err("pinfo failed\n");
+ }
+ size = params_buffer_bytes(params);
+ rtd->dma_addr = substream->dma_buffer.addr;
+ rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
+ config_acp5x_dma(rtd, substream->stream);
+ return 0;
+}
+
+static snd_pcm_uframes_t acp5x_dma_pointer(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct i2s_stream_instance *rtd;
+ u32 pos;
+ u32 buffersize;
+ u64 bytescount;
+
+ rtd = substream->runtime->private_data;
+ buffersize = frames_to_bytes(substream->runtime,
+ substream->runtime->buffer_size);
+ bytescount = acp_get_byte_count(rtd, substream->stream);
+ if (bytescount > rtd->bytescount)
+ bytescount -= rtd->bytescount;
+ pos = do_div(bytescount, buffersize);
+ return bytes_to_frames(substream->runtime, pos);
+}
+
+static int acp5x_dma_new(struct snd_soc_component *component,
+ struct snd_soc_pcm_runtime *rtd)
+{
+ struct device *parent = component->dev->parent;
+
+ snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
+ parent, MIN_BUFFER, MAX_BUFFER);
+ return 0;
+}
+
+static int acp5x_dma_mmap(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ return snd_pcm_lib_default_mmap(substream, vma);
+}
+
+static int acp5x_dma_close(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *prtd;
+ struct i2s_dev_data *adata;
+ struct i2s_stream_instance *ins;
+
+ prtd = asoc_substream_to_rtd(substream);
+ component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+ adata = dev_get_drvdata(component->dev);
+ ins = substream->runtime->private_data;
+ if (!ins)
+ return -EINVAL;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ switch (ins->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ adata->play_stream = NULL;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ adata->i2ssp_play_stream = NULL;
+ }
+ } else {
+ switch (ins->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ adata->capture_stream = NULL;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ adata->i2ssp_capture_stream = NULL;
+ }
+ }
+ kfree(ins);
+ return 0;
+}
+
+static const struct snd_soc_component_driver acp5x_i2s_component = {
+ .name = DRV_NAME,
+ .open = acp5x_dma_open,
+ .close = acp5x_dma_close,
+ .hw_params = acp5x_dma_hw_params,
+ .pointer = acp5x_dma_pointer,
+ .mmap = acp5x_dma_mmap,
+ .pcm_construct = acp5x_dma_new,
+};
+
static int acp5x_audio_probe(struct platform_device *pdev)
{
struct resource *res;
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index 44662e54bd34..99298a2f38ce 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -6,6 +6,7 @@
*/
#include "vg_chip_offset_byte.h"
+#include <sound/pcm.h>
#define ACP5x_PHY_BASE_ADDRESS 0x1240000
#define ACP_DEVICE_ID 0x15E2
@@ -36,6 +37,39 @@
#define HS_TX_THRESHOLD 24
#define HS_RX_THRESHOLD 23
+#define I2S_SP_INSTANCE 0x01
+#define I2S_HS_INSTANCE 0x02
+
+#define ACP_SRAM_PTE_OFFSET 0x02050000
+#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
+#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
+#define ACP_SRAM_HS_PB_PTE_OFFSET 0x200
+#define ACP_SRAM_HS_CP_PTE_OFFSET 0x300
+#define PAGE_SIZE_4K_ENABLE 0x2
+#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
+#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
+#define I2S_HS_TX_MEM_WINDOW_START 0x4040000
+#define I2S_HS_RX_MEM_WINDOW_START 0x4060000
+
+#define SP_PB_FIFO_ADDR_OFFSET 0x500
+#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
+#define HS_PB_FIFO_ADDR_OFFSET 0x900
+#define HS_CAPT_FIFO_ADDR_OFFSET 0xB00
+#define PLAYBACK_MIN_NUM_PERIODS 2
+#define PLAYBACK_MAX_NUM_PERIODS 8
+#define PLAYBACK_MAX_PERIOD_SIZE 8192
+#define PLAYBACK_MIN_PERIOD_SIZE 1024
+#define CAPTURE_MIN_NUM_PERIODS 2
+#define CAPTURE_MAX_NUM_PERIODS 8
+#define CAPTURE_MAX_PERIOD_SIZE 8192
+#define CAPTURE_MIN_PERIOD_SIZE 1024
+
+#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
+#define MIN_BUFFER MAX_BUFFER
+#define FIFO_SIZE 0x100
+#define DMA_SIZE 0x40
+#define FRM_LEN 0x100
+
struct i2s_dev_data {
unsigned int i2s_irq;
void __iomem *acp5x_base;
@@ -45,6 +79,31 @@ struct i2s_dev_data {
struct snd_pcm_substream *i2ssp_capture_stream;
};
+struct i2s_stream_instance {
+ u16 num_pages;
+ u16 i2s_instance;
+ u16 direction;
+ u16 channels;
+ u32 xfer_resolution;
+ u32 val;
+ dma_addr_t dma_addr;
+ u64 bytescount;
+ void __iomem *acp5x_base;
+};
+
+union acp_dma_count {
+ struct {
+ u32 low;
+ u32 high;
+ } bcount;
+ u64 bytescount;
+};
+
+struct acp5x_platform_info {
+ u16 play_i2s_instance;
+ u16 cap_i2s_instance;
+};
+
static inline u32 acp_readl(void __iomem *base_addr)
{
return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
@@ -54,3 +113,50 @@ static inline void acp_writel(u32 val, void __iomem *base_addr)
{
writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
}
+
+static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
+ int direction)
+{
+ union acp_dma_count byte_count;
+
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ byte_count.bcount.high =
+ acp_readl(rtd->acp5x_base +
+ ACP_HS_TX_LINEARPOSCNTR_HIGH);
+ byte_count.bcount.low =
+ acp_readl(rtd->acp5x_base +
+ ACP_HS_TX_LINEARPOSCNTR_LOW);
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ byte_count.bcount.high =
+ acp_readl(rtd->acp5x_base +
+ ACP_I2S_TX_LINEARPOSCNTR_HIGH);
+ byte_count.bcount.low =
+ acp_readl(rtd->acp5x_base +
+ ACP_I2S_TX_LINEARPOSCNTR_LOW);
+ }
+ } else {
+ switch (rtd->i2s_instance) {
+ case I2S_HS_INSTANCE:
+ byte_count.bcount.high =
+ acp_readl(rtd->acp5x_base +
+ ACP_HS_RX_LINEARPOSCNTR_HIGH);
+ byte_count.bcount.low =
+ acp_readl(rtd->acp5x_base +
+ ACP_HS_RX_LINEARPOSCNTR_LOW);
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ byte_count.bcount.high =
+ acp_readl(rtd->acp5x_base +
+ ACP_I2S_RX_LINEARPOSCNTR_HIGH);
+ byte_count.bcount.low =
+ acp_readl(rtd->acp5x_base +
+ ACP_I2S_RX_LINEARPOSCNTR_LOW);
+ }
+ }
+ return byte_count.bytescount;
+}
--
2.17.1
On Wed, Jul 07, 2021 at 11:26:18AM +0530, Vijendar Mukunda wrote:
> + /* Group Enable */
> + acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
> + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
> + acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
> + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
This isn't connected to the kernel page size is it? If so we might've
configured to 16K or 64K, or possibly even some other options - I know
those two are out there in the wild.
On 7/7/21 12:56 AM, Vijendar Mukunda wrote:
> This patch adds ACP5x PCM driver DMA operations.
>
> Signed-off-by: Vijendar Mukunda <[email protected]>
> ---
> sound/soc/amd/vangogh/acp5x-pcm-dma.c | 306 +++++++++++++++++++++++++-
> sound/soc/amd/vangogh/acp5x.h | 106 +++++++++
> 2 files changed, 410 insertions(+), 2 deletions(-)
>
> diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
> index d79712587d30..a4235cf33548 100644
> --- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
> +++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
> @@ -17,8 +17,42 @@
>
> #define DRV_NAME "acp5x_i2s_dma"
>
> -static const struct snd_soc_component_driver acp5x_i2s_component = {
> - .name = DRV_NAME,
> +static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
> + .info = SNDRV_PCM_INFO_INTERLEAVED |
> + SNDRV_PCM_INFO_BLOCK_TRANSFER |
> + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
> + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
> + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
is S24_4LE supported? seems more useful than 8-bit audio these days, no?
> +static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
> +{
> + u16 page_idx;
> + u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
> + u32 reg_dma_size, reg_fifo_size;
> + dma_addr_t addr;
> +
> + addr = rtd->dma_addr;
> + if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
> + switch (rtd->i2s_instance) {
> + case I2S_HS_INSTANCE:
> + val = ACP_SRAM_HS_PB_PTE_OFFSET;
> + break;
> + case I2S_SP_INSTANCE:
> + default:
> + val = ACP_SRAM_SP_PB_PTE_OFFSET;
> + }
> + } else {
> + switch (rtd->i2s_instance) {
> + case I2S_HS_INSTANCE:
> + val = ACP_SRAM_HS_CP_PTE_OFFSET;
> + break;
> + case I2S_SP_INSTANCE:
> + default:
> + val = ACP_SRAM_SP_CP_PTE_OFFSET;
> + }
> + }
> + /* Group Enable */
> + acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
> + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
> + acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
> + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
> +
> + for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
> + /* Load the low address of page int ACP SRAM through SRBM */
> + low = lower_32_bits(addr);
> + high = upper_32_bits(addr);
> +
> + acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
> + high |= BIT(31);
> + acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val
> + + 4);
use single line? I find the indentation style quite an eyesore...
> + /* Move to next physically contiguous page */
> + val += 8;
> + addr += PAGE_SIZE;
> + }
> +
> + if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
> + switch (rtd->i2s_instance) {
> + case I2S_HS_INSTANCE:
> + reg_dma_size = ACP_HS_TX_DMA_SIZE;
> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> + HS_PB_FIFO_ADDR_OFFSET;
> + reg_fifo_addr = ACP_HS_TX_FIFOADDR;
> + reg_fifo_size = ACP_HS_TX_FIFOSIZE;
> + acp_writel(I2S_HS_TX_MEM_WINDOW_START,
> + rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
> + break;
> +
> + case I2S_SP_INSTANCE:
> + default:
> + reg_dma_size = ACP_I2S_TX_DMA_SIZE;
> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> + SP_PB_FIFO_ADDR_OFFSET;
> + reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
> + reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
> + acp_writel(I2S_SP_TX_MEM_WINDOW_START,
> + rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
> + }
> + } else {
> + switch (rtd->i2s_instance) {
> + case I2S_HS_INSTANCE:
> + reg_dma_size = ACP_HS_RX_DMA_SIZE;
> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> + HS_CAPT_FIFO_ADDR_OFFSET;
> + reg_fifo_addr = ACP_HS_RX_FIFOADDR;
> + reg_fifo_size = ACP_HS_RX_FIFOSIZE;
> + acp_writel(I2S_HS_RX_MEM_WINDOW_START,
> + rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
> + break;
> +
> + case I2S_SP_INSTANCE:
> + default:
> + reg_dma_size = ACP_I2S_RX_DMA_SIZE;
> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> + SP_CAPT_FIFO_ADDR_OFFSET;
> + reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
> + reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
> + acp_writel(I2S_SP_RX_MEM_WINDOW_START,
> + rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
> + }
> + }
> + acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
> + acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
> + acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
> + acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
> + | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
> + rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
> +}
> +
> +static int acp5x_dma_hw_params(struct snd_soc_component *component,
> + struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params)
> +{
> + struct i2s_stream_instance *rtd;
> + struct snd_soc_pcm_runtime *prtd;
> + struct snd_soc_card *card;
> + struct acp5x_platform_info *pinfo;
> + struct i2s_dev_data *adata;
> + u64 size;
> +
> + prtd = asoc_substream_to_rtd(substream);
> + card = prtd->card;
> + pinfo = snd_soc_card_get_drvdata(card);
> + adata = dev_get_drvdata(component->dev);
> + rtd = substream->runtime->private_data;
> +
> + if (!rtd)
> + return -EINVAL;
> +
> + if (pinfo) {
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + rtd->i2s_instance = pinfo->play_i2s_instance;
> + switch (rtd->i2s_instance) {
> + case I2S_HS_INSTANCE:
> + adata->play_stream = substream;
> + break;
> + case I2S_SP_INSTANCE:
> + default:
> + adata->i2ssp_play_stream = substream;
> + }
> + } else {
> + rtd->i2s_instance = pinfo->cap_i2s_instance;
> + switch (rtd->i2s_instance) {
> + case I2S_HS_INSTANCE:
> + adata->capture_stream = substream;
> + break;
> + case I2S_SP_INSTANCE:
> + default:
> + adata->i2ssp_capture_stream = substream;
> + }
> + }
> + } else {
> + pr_err("pinfo failed\n");
that seems like a rather useless message. if you want a log at least use dev_err(component->dev
> + }
> + size = params_buffer_bytes(params);
> + rtd->dma_addr = substream->dma_buffer.addr;
> + rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
> + config_acp5x_dma(rtd, substream->stream);
> + return 0;
> +}
> +
On 7/7/21 10:00 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:18AM +0530, Vijendar Mukunda wrote:
>
>> + /* Group Enable */
>> + acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
>> + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
>> + acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
>> + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
>
> This isn't connected to the kernel page size is it? If so we might've
> configured to 16K or 64K, or possibly even some other options - I know
> those two are out there in the wild.
>
No this is not connected to kernel page size. This is internal to ACP IP.
On 7/7/21 9:57 PM, Pierre-Louis Bossart wrote:
>
>
> On 7/7/21 12:56 AM, Vijendar Mukunda wrote:
>> This patch adds ACP5x PCM driver DMA operations.
>>
>> Signed-off-by: Vijendar Mukunda <[email protected]>
>> ---
>> sound/soc/amd/vangogh/acp5x-pcm-dma.c | 306 +++++++++++++++++++++++++-
>> sound/soc/amd/vangogh/acp5x.h | 106 +++++++++
>> 2 files changed, 410 insertions(+), 2 deletions(-)
>>
>> diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
>> index d79712587d30..a4235cf33548 100644
>> --- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
>> +++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
>> @@ -17,8 +17,42 @@
>>
>> #define DRV_NAME "acp5x_i2s_dma"
>>
>> -static const struct snd_soc_component_driver acp5x_i2s_component = {
>> - .name = DRV_NAME,
>> +static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
>> + .info = SNDRV_PCM_INFO_INTERLEAVED |
>> + SNDRV_PCM_INFO_BLOCK_TRANSFER |
>> + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
>> + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
>> + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
>> + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
>
> is S24_4LE supported? seems more useful than 8-bit audio these days, no?
AMD I2S controller doesn't support S24_LE format.
>
>> +static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
>> +{
>> + u16 page_idx;
>> + u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
>> + u32 reg_dma_size, reg_fifo_size;
>> + dma_addr_t addr;
>> +
>> + addr = rtd->dma_addr;
>> + if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
>> + switch (rtd->i2s_instance) {
>> + case I2S_HS_INSTANCE:
>> + val = ACP_SRAM_HS_PB_PTE_OFFSET;
>> + break;
>> + case I2S_SP_INSTANCE:
>> + default:
>> + val = ACP_SRAM_SP_PB_PTE_OFFSET;
>> + }
>> + } else {
>> + switch (rtd->i2s_instance) {
>> + case I2S_HS_INSTANCE:
>> + val = ACP_SRAM_HS_CP_PTE_OFFSET;
>> + break;
>> + case I2S_SP_INSTANCE:
>> + default:
>> + val = ACP_SRAM_SP_CP_PTE_OFFSET;
>> + }
>> + }
>> + /* Group Enable */
>> + acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
>> + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
>> + acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
>> + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
>> +
>> + for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
>> + /* Load the low address of page int ACP SRAM through SRBM */
>> + low = lower_32_bits(addr);
>> + high = upper_32_bits(addr);
>> +
>> + acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
>> + high |= BIT(31);
>> + acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val
>> + + 4);
>
> use single line? I find the indentation style quite an eyesore...
will fix the indentation style.
>
>
>> + /* Move to next physically contiguous page */
>> + val += 8;
>> + addr += PAGE_SIZE;
>> + }
>> +
>> + if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
>> + switch (rtd->i2s_instance) {
>> + case I2S_HS_INSTANCE:
>> + reg_dma_size = ACP_HS_TX_DMA_SIZE;
>> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> + HS_PB_FIFO_ADDR_OFFSET;
>> + reg_fifo_addr = ACP_HS_TX_FIFOADDR;
>> + reg_fifo_size = ACP_HS_TX_FIFOSIZE;
>> + acp_writel(I2S_HS_TX_MEM_WINDOW_START,
>> + rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
>> + break;
>> +
>> + case I2S_SP_INSTANCE:
>> + default:
>> + reg_dma_size = ACP_I2S_TX_DMA_SIZE;
>> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> + SP_PB_FIFO_ADDR_OFFSET;
>> + reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
>> + reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
>> + acp_writel(I2S_SP_TX_MEM_WINDOW_START,
>> + rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
>> + }
>> + } else {
>> + switch (rtd->i2s_instance) {
>> + case I2S_HS_INSTANCE:
>> + reg_dma_size = ACP_HS_RX_DMA_SIZE;
>> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> + HS_CAPT_FIFO_ADDR_OFFSET;
>> + reg_fifo_addr = ACP_HS_RX_FIFOADDR;
>> + reg_fifo_size = ACP_HS_RX_FIFOSIZE;
>> + acp_writel(I2S_HS_RX_MEM_WINDOW_START,
>> + rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
>> + break;
>> +
>> + case I2S_SP_INSTANCE:
>> + default:
>> + reg_dma_size = ACP_I2S_RX_DMA_SIZE;
>> + acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> + SP_CAPT_FIFO_ADDR_OFFSET;
>> + reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
>> + reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
>> + acp_writel(I2S_SP_RX_MEM_WINDOW_START,
>> + rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
>> + }
>> + }
>> + acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
>> + acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
>> + acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
>> + acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
>> + | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
>> + rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
>> +}
>> +
>
>> +static int acp5x_dma_hw_params(struct snd_soc_component *component,
>> + struct snd_pcm_substream *substream,
>> + struct snd_pcm_hw_params *params)
>> +{
>> + struct i2s_stream_instance *rtd;
>> + struct snd_soc_pcm_runtime *prtd;
>> + struct snd_soc_card *card;
>> + struct acp5x_platform_info *pinfo;
>> + struct i2s_dev_data *adata;
>> + u64 size;
>> +
>> + prtd = asoc_substream_to_rtd(substream);
>> + card = prtd->card;
>> + pinfo = snd_soc_card_get_drvdata(card);
>> + adata = dev_get_drvdata(component->dev);
>> + rtd = substream->runtime->private_data;
>> +
>> + if (!rtd)
>> + return -EINVAL;
>> +
>> + if (pinfo) {
>> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
>> + rtd->i2s_instance = pinfo->play_i2s_instance;
>> + switch (rtd->i2s_instance) {
>> + case I2S_HS_INSTANCE:
>> + adata->play_stream = substream;
>> + break;
>> + case I2S_SP_INSTANCE:
>> + default:
>> + adata->i2ssp_play_stream = substream;
>> + }
>> + } else {
>> + rtd->i2s_instance = pinfo->cap_i2s_instance;
>> + switch (rtd->i2s_instance) {
>> + case I2S_HS_INSTANCE:
>> + adata->capture_stream = substream;
>> + break;
>> + case I2S_SP_INSTANCE:
>> + default:
>> + adata->i2ssp_capture_stream = substream;
>> + }
>> + }
>> + } else {
>> + pr_err("pinfo failed\n");
>
> that seems like a rather useless message. if you want a log at least use dev_err(component->dev
will fix it and post the new version.
>
>> + }
>> + size = params_buffer_bytes(params);
>> + rtd->dma_addr = substream->dma_buffer.addr;
>> + rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
>> + config_acp5x_dma(rtd, substream->stream);
>> + return 0;
>> +}
>> +