2022-03-18 18:13:56

by Sherry Sun

Subject: [PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR

V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
to change to use the ECC Clear Register to disable the interrupts.

Signed-off-by: Sherry Sun <[email protected]>
---
drivers/edac/synopsys_edac.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index f05ff02c0656..1b630f0be119 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -859,8 +859,11 @@ static void enable_intr(struct synps_edac_priv *priv)
static void disable_intr(struct synps_edac_priv *priv)
{
/* Disable UE/CE Interrupts */
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
}

static int setup_irq(struct mem_ctl_info *mci,
--
2.17.1

2022-04-21 23:29:44

by Michal Simek

Subject: Re: [PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR

On 3/18/22 12:17, Sherry Sun wrote:
> V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
> to change to use the ECC Clear Register to disable the interrupts.
>
> Signed-off-by: Sherry Sun <[email protected]>
> ---
> drivers/edac/synopsys_edac.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> index f05ff02c0656..1b630f0be119 100644
> --- a/drivers/edac/synopsys_edac.c
> +++ b/drivers/edac/synopsys_edac.c
> @@ -859,8 +859,11 @@ static void enable_intr(struct synps_edac_priv *priv)
> static void disable_intr(struct synps_edac_priv *priv)
> {
> /* Disable UE/CE Interrupts */
> - writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> - priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
> + if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
> + writel(0x0, priv->baseaddr + ECC_CLR_OFST);
> + else
> + writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> + priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
> }
>
> static int setup_irq(struct mem_ctl_info *mci,

Acked-by: Michal Simek <[email protected]>

Thanks,
Michal