Hi all,
The patch set fixes clock settings for the Exynos5420/5422/5800 SoCs which
can be found in Odroid XU3/4, Google Peach Pi. Support for DT board files
with Exynos5420 (like Google Peach Pit) are under development. The old
implementation did not configure properly the clock rates or the
connections which could cause performance issues or instability. The
Exynos5x SoC has complex clocks topology. Some of the NoC clock branches
provide clock to the device internal buses or AXI interface and had wrong
settings.
In the old configuration the OPP values where not reflecting the actually
set frequencies, which were possible by setting the divider value on the
clock tree. The algorithms in governors, which use these frequencies,
relied on wrong assumption during their calculations. It also applies to
device drivers code, which does not check the rate of the clock but relay
on OPP values, which in some cases are different. It is not only the bus
frequency but also the connected component internal buses (accelerators
like e.g. G2D, scaler, rotator) frequency. Wrong frequency set due to
impossible division from PLL rate caused that some devices had lower than
possible clock for internal logic and for the AXI bus which transfers the
data. For example fixes for MMC controller, where OPP max frequency
changed from 150MHz to 240MHz, changing the PLL rate to proper value caused
performance increase up to 20% (FSYS2 OPP table).
Affected components inside SoC: image rotator, usb3.0 and 2.0 controller,
jpeg accelerator, image/video scaler, mmc controller, ISP, display
controller, all NoC buses.
Some of the clocks have name which might indicate their max speed, e.g.
CLK_DOUT_ACLK266 but it is not true. The max speed clock from this example
is 300MHz (according to the RM) and has been reflected accordingly in this
patch set.
Main changes:
- defined new clocks or added IDs to take them from DT nodes
- set proper PLLs frequency for: MPLL, DPLL, which would handle children
clock requirements down in the tree,
- changed parents of some clocks to proper PLL or to proper parent clock,
- properly calculated OPP values for the buses keeping in mind the parent
clock frequency and possible values derived from there by one clock
divider with proper bit length indicating maximum allowed divider; thanks
to that it is possible to set the requested frequency in all children
without changing the PLL frequency, which also makes the governor frequency
values assumption true,
- some OPPs were removed because it was not possible to set them due to
different base frequency, which would require of changing PLL rate, which
might affect other devices connected to this PLL and their misscalculated
rates.
The last two patches touches Exynos5800 and are optional. They have been
checked due to some issues with disabling parent, which accidently was
populated up to MPLL and shut down the PLL. They might be used for testing
on Peach Pi.
The patch set is based on Samsung clock repo and branch 'for-v5.3/next'
[1].
Regards,
Lukasz Luba
[1] https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git/log/?h=for-v5.3/next
Lukasz Luba (50):
clk: samsung: add new IDs for Exynos5420 clocks
clk: samsung: add IDs for Exynos5420 NoC clocks
clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
clk: samsung: add IDs to aclk400_isp in Exynos5420
clk: samsung: add IDs to ACLK266 clocks in Exynos5420
clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420
clk: samsung: change aclk266_isp clocks definitions Exynos5420
clk: samsung: add IDs to FSYS clocks in Exynos5x
clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
clk: samsung: add IDs to UART clocks in Exynos5420
clk: add ID to PWM MUX in Exynos5420
clk: samsung: add DPLL rate table in Exynos5420
clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420
clk: samsung: add MPLL rate table in Exynos5420
clk: samsung: add SPLL rate table in Exynos5420
clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420
ARM: dts: exynos: add bus_isp with OPP table
ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420
ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420
ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420
ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420
ARM: dts: exynos: align OPPs of bus_gen in Exynos5420
ARM: dts: exynos: add bus_isp266 into Exynos5800
ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420
ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
ARM: dts: exynos: set parent clocks to PWM in Exynos5420
ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
ARM: dts: exynos: change ACLK100_NOC config in Exynos5422
ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422
ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422
ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422
ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422
ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422
ARM: dts: exynos: add bus_isp in Exynos5422
ARM: dts: exynos: change rate of bus_jpeg in Exynos5422
ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422
ARM: dts: exynos: change rates of bus_disp1 in Exynos5422
ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422
ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422
ARM: dts: exynos: add buses support for Exynos5800 Peach Pi
ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi
arch/arm/boot/dts/exynos5420.dtsi | 116 +++++++-----
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 74 ++++++++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 175 ++++++++++++++++++
arch/arm/boot/dts/exynos5800.dtsi | 10 +
drivers/clk/samsung/clk-exynos5420.c | 109 +++++++----
include/dt-bindings/clock/exynos5420.h | 27 ++-
6 files changed, 429 insertions(+), 82 deletions(-)
--
2.17.1
Add ID to mout_mmc0 MUX to make possible children connection in
the DT.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ead569a164cf..8d58801baf2c 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -763,7 +763,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
/* FSYS Block */
MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
- MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
+ MUX(CLK_MOUT_MMC0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
--
2.17.1
The OPPs values for FSYS2 does not reflect the real possible frequencies.
According to the documentation the maximum frequency is 240MHz. This clock
is important to MMC controller controlling the AXI data bus speed and
internal buses. The new OPP values are aligned to parent PLL rate so that
there is no need of reprogramming PLL and the integer values are possible
to get using only a clock divider.
Signed-off-by: Lukasz Luba <[email protected]>
---
arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1b717c5c3b1a..941c58bdd809 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1161,13 +1161,13 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <75000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
- opp-hz = /bits/ 64 <100000000>;
+ opp-hz = /bits/ 64 <200000000>;
};
opp02 {
- opp-hz = /bits/ 64 <150000000>;
+ opp-hz = /bits/ 64 <240000000>;
};
};
--
2.17.1
Add ID to PWM MUX to manage it from DT to reflect proper topology.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7bf74401c4e7..7f8221527633 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -772,7 +772,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
- MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+ MUX(CLK_MOUT_PWM, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
--
2.17.1
The DPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the DPLL gets rate table the same for the
whole PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the DPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7f8221527633..2395b02ce8c5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
CLK_SET_RATE_PARENT, 0),
- MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+ MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
+ SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
@@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
if (_get_rate("fin_pll") == 24 * MHZ) {
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
--
2.17.1
The ACLK266_ISP has different topology in Exynos5420 and 5422/5800. In
Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
it takes the clock from 2-level mux from ACLK266. In Exynos5422 there is a
dedicated clock tree and the PLL can be chosen. The patch adds needed
MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
DT.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d54856dbcda..5f251279b4c8 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2",
"mout_sclk_spll", "mout_sclk_epll"};
+PNAME(mout_group17_5800_p) = { "dout_aclk266_isp", "dout_sclk_sw" };
+PNAME(mout_group18_5800_p) = { "dout_osc_div", "mout_sw_aclk266_isp" };
+PNAME(mout_group19_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_ipll"};
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock
@@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
+ MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
+ SRC_TOP8, 12, 2),
MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
@@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
+ MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
+ mout_group18_5800_p, SRC_TOP9, 12, 1),
MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
SRC_TOP9, 16, 1),
MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
@@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
SRC_TOP9, 28, 1),
+ MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
+ SRC_TOP13, 12, 1),
MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
SRC_TOP13, 20, 1),
@@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+ DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
+ DIV_TOP8, 12, 3),
DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
DIV_TOP8, 16, 3),
DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
@@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
+ MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
+ mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
+
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
mout_group5_5800_p, SRC_TOP7, 16, 2),
MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
@@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
SRC_TOP4, 8, 1),
MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
SRC_TOP4, 12, 1),
- MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
- SRC_TOP4, 16, 1),
MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
--
2.17.1
Add needed IDs to MUXes which are used from DT to properly set clock
hierarchy.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 361ee53fc9fc..8f1d39cb2f1e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
- MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
+ MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
+ SRC_TOP0, 4, 3),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
SRC_TOP0, 16, 3),
MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
TOP_SPARE2, 4, 1),
MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
- MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
+ MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
+ SRC_TOP0, 4, 2),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
SRC_TOP0, 16, 2),
MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
@@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
SRC_TOP10, 0, 1),
- MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
- SRC_TOP10, 4, 1),
+ MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
+ mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
SRC_TOP10, 8, 1),
MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
--
2.17.1
Hi,
The patch4~patch7 just add the ID to control the clock from DT.
You can squash them to one patch instead of splitting out according to
the type of clock.
On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> Add needed IDs to MUXes which are used from DT to properly set clock
> hierarchy.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 361ee53fc9fc..8f1d39cb2f1e 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
>
> static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
> - MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
> + MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
> + SRC_TOP0, 4, 3),
> MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
> SRC_TOP0, 16, 3),
> MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
> @@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
> TOP_SPARE2, 4, 1),
>
> MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
> - MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
> + MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
> + SRC_TOP0, 4, 2),
> MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
> SRC_TOP0, 16, 2),
> MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
> @@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>
> MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
> SRC_TOP10, 0, 1),
> - MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
> - SRC_TOP10, 4, 1),
> + MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
> + mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
> MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
> SRC_TOP10, 8, 1),
> MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi,
Also, you better to merge patch13/patch15/patch16 to one patch
in order to add the PLL table for DPLL/MPLL/SPLL.
And I have a question. Are there any use-case to change
the PLL frequency for DPLL/MPLL/SPLL?
On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> The DPLL has fixed frequency left by the bootloader and it is not possible
> to change it. With this patch the DPLL gets rate table the same for the
> whole PLL family (similar as APLL, KPLL according to RM) so the frequency
> might be changed to one of the values defined there.
> It is needed for further patches which change the DPLL frequency to feed
> the clocks with proper base.
> It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
> disable master clock, which is then populated higher and tries to disable
> PLL, which casues system crash. The flag is needed for this kind of use
> cases.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 7f8221527633..2395b02ce8c5 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
> MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
> MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
> CLK_SET_RATE_PARENT, 0),
> - MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
> + MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
> + SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
> MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
>
> MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
> @@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>
> if (_get_rate("fin_pll") == 24 * MHZ) {
> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> + exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> }
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi,
On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> The ACLK266_ISP has different topology in Exynos5420 and 5422/5800. In
> Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
> it takes the clock from 2-level mux from ACLK266. In Exynos5422 there is a
> dedicated clock tree and the PLL can be chosen. The patch adds needed
> MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
> exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
> DT.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 9d54856dbcda..5f251279b4c8 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
> PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
> "mout_sclk_mpll", "ff_dout_spll2",
> "mout_sclk_spll", "mout_sclk_epll"};
> +PNAME(mout_group17_5800_p) = { "dout_aclk266_isp", "dout_sclk_sw" };
> +PNAME(mout_group18_5800_p) = { "dout_osc_div", "mout_sw_aclk266_isp" };
> +PNAME(mout_group19_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
> + "mout_sclk_mpll", "mout_sclk_ipll"};
>
> /* fixed rate clocks generated outside the soc */
> static struct samsung_fixed_rate_clock
> @@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
> MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>
> + MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
> + SRC_TOP8, 12, 2),
> MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
> MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
> MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
> @@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>
> MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
> SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
> + MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
> + mout_group18_5800_p, SRC_TOP9, 12, 1),
> MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
> SRC_TOP9, 16, 1),
> MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
> @@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
> SRC_TOP9, 28, 1),
>
> + MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
> + SRC_TOP13, 12, 1),
> MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
> MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
> SRC_TOP13, 20, 1),
> @@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
> DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
> "mout_aclk400_wcore", DIV_TOP0, 16, 3),
> + DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
> + DIV_TOP8, 12, 3),
> DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
> DIV_TOP8, 16, 3),
> DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
> @@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
> MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
> MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
>
> + MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
> + mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
> +
> MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
> mout_group5_5800_p, SRC_TOP7, 16, 2),
> MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
> @@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
> SRC_TOP4, 8, 1),
> MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
> SRC_TOP4, 12, 1),
> - MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
> - SRC_TOP4, 16, 1),
> MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
> MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
> MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
>
I checked it on Exynos5420/5422 TRM.
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Chanwoo,
On 7/16/19 11:17 AM, Chanwoo Choi wrote:
> Hi,
>
> The patch4~patch7 just add the ID to control the clock from DT.
> You can squash them to one patch instead of splitting out according to
> the type of clock.
Thank you for the review. Yes, you are right it needs to be squashed.
Regards,
Lukasz
>
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> Add needed IDs to MUXes which are used from DT to properly set clock
>> hierarchy.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
>> 1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 361ee53fc9fc..8f1d39cb2f1e 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
>>
>> static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>> MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
>> - MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
>> + MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
>> + SRC_TOP0, 4, 3),
>> MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
>> SRC_TOP0, 16, 3),
>> MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
>> @@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>> TOP_SPARE2, 4, 1),
>>
>> MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
>> - MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
>> + MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
>> + SRC_TOP0, 4, 2),
>> MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
>> SRC_TOP0, 16, 2),
>> MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
>> @@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>>
>> MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
>> SRC_TOP10, 0, 1),
>> - MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
>> - SRC_TOP10, 4, 1),
>> + MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
>> + mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
>> MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
>> SRC_TOP10, 8, 1),
>> MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
>>
>
>
Hi Chanwoo,
On 7/16/19 11:31 AM, Chanwoo Choi wrote:
> Hi,
>
> Also, you better to merge patch13/patch15/patch16 to one patch
> in order to add the PLL table for DPLL/MPLL/SPLL.
OK
>
> And I have a question. Are there any use-case to change
> the PLL frequency for DPLL/MPLL/SPLL?
Yes, when you set a PLL frequency i.e. DPLL to 1200MHz (from 600MHz)
you can attach a child to it which is running with 400, 300, 150 MHz
and these frequencies are set only on this child clock divider
(/3, /4, /8 - 3bit div) (and there is no set parent rate and
reprogramming the master PLL). While 600MHz cannot satisfy 400MHz
and 300MHz OPPs at the same time.
If the child cannot change the PLL, because it could affect other
children of this PLL and cause misalignment in their frequency after
their dividers, it is better to stick with a rule: pin children to the
PLL with frequency rate which could be divided without a rest and gives
all OPPs rates of all children. This PLL rate could be calculated by
hand, finding least common multiple, keeping in mind clock dividers
width (i.e. 3bit).
That's why I am changing the PLLs' rates and connect children to them
also aligning OPPs to the values which are possible after DIV (3bit).
Regards,
Lukasz
>
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> The DPLL has fixed frequency left by the bootloader and it is not possible
>> to change it. With this patch the DPLL gets rate table the same for the
>> whole PLL family (similar as APLL, KPLL according to RM) so the frequency
>> might be changed to one of the values defined there.
>> It is needed for further patches which change the DPLL frequency to feed
>> the clocks with proper base.
>> It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
>> disable master clock, which is then populated higher and tries to disable
>> PLL, which casues system crash. The flag is needed for this kind of use
>> cases.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> drivers/clk/samsung/clk-exynos5420.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 7f8221527633..2395b02ce8c5 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>> MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
>> MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
>> CLK_SET_RATE_PARENT, 0),
>> - MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
>> + MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
>> + SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
>> MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
>>
>> MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
>> @@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>>
>> if (_get_rate("fin_pll") == 24 * MHZ) {
>> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> + exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
>> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> }
>>
>
>
Hi Chanwoo,
On 7/16/19 12:22 PM, Chanwoo Choi wrote:
> Hi,
>
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> The ACLK266_ISP has different topology in Exynos5420 and 5422/5800. In
>> Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
>> it takes the clock from 2-level mux from ACLK266. In Exynos5422 there is a
>> dedicated clock tree and the PLL can be chosen. The patch adds needed
>> MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
>> exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
>> DT.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
>> 1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 9d54856dbcda..5f251279b4c8 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
>> PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
>> "mout_sclk_mpll", "ff_dout_spll2",
>> "mout_sclk_spll", "mout_sclk_epll"};
>> +PNAME(mout_group17_5800_p) = { "dout_aclk266_isp", "dout_sclk_sw" };
>> +PNAME(mout_group18_5800_p) = { "dout_osc_div", "mout_sw_aclk266_isp" };
>> +PNAME(mout_group19_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
>> + "mout_sclk_mpll", "mout_sclk_ipll"};
>>
>> /* fixed rate clocks generated outside the soc */
>> static struct samsung_fixed_rate_clock
>> @@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>> MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
>> MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>>
>> + MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
>> + SRC_TOP8, 12, 2),
>> MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
>> MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
>> MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
>> @@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>
>> MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
>> SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
>> + MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
>> + mout_group18_5800_p, SRC_TOP9, 12, 1),
>> MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
>> SRC_TOP9, 16, 1),
>> MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
>> @@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>> MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
>> SRC_TOP9, 28, 1),
>>
>> + MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
>> + SRC_TOP13, 12, 1),
>> MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
>> MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
>> SRC_TOP13, 20, 1),
>> @@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>> static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
>> DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
>> "mout_aclk400_wcore", DIV_TOP0, 16, 3),
>> + DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
>> + DIV_TOP8, 12, 3),
>> DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
>> DIV_TOP8, 16, 3),
>> DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
>> @@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>> MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
>> MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
>>
>> + MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
>> + mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
>> +
>> MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
>> mout_group5_5800_p, SRC_TOP7, 16, 2),
>> MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
>> @@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>> SRC_TOP4, 8, 1),
>> MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
>> SRC_TOP4, 12, 1),
>> - MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
>> - SRC_TOP4, 16, 1),
>> MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
>> MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
>> MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
>>
>
> I checked it on Exynos5420/5422 TRM.
>
> Acked-by: Chanwoo Choi <[email protected]>
Thank you!
Regards,
Lukasz
>