This series uses the abstraction added in past kernel cycles to provide
support for the ACE2.x integration. The existing SHIM and Cadence
registers are now split in 3 (SHIM, IP, SHIM vendor-specific), with some
parts also moved to the HDaudio Extended Multi link structures. Nothing
fundamentally different except for the register map.
This series only provides the basic mechanisms to expose SoundWire-based
DAIs. The PCI parts and DSP management will be contributed later, and the
DAI ops are now empty as well.
The change is mainly on SoundWire. It would be better to go through
SoundWire tree.
v2:
- Some cleanup for free, trigger, hw_params callbacks before introducing
ACE2.x callbacks.
Pierre-Louis Bossart (26):
ASoC: SOF: Intel: shim: add enum for ACE 2.0 IP used in LunarLake
soundwire: intel: add ACE2.x SHIM definitions
soundwire: intel_ace2x: add empty new ops for LunarLake
soundwire/ASOC: Intel: update offsets for LunarLake
soundwire: intel/cadence: set ip_offset at run-time
ASoC/soundwire: intel: pass hdac_bus pointer for link management
soundwire: intel: add eml_lock in the interface for new platforms
ASoC: SOF: Intel: hda: retrieve SoundWire eml_lock and pass pointer
soundwire: intel_init: use eml_lock parameter
soundwire: intel_ace2x: add debugfs support
soundwire: intel_ace2x: add link power-up/down helpers
soundwire: intel_ace2x: set SYNCPRD before powering-up
soundwire: intel_ace2x: configure link PHY
soundwire: intel_ace2x: add DAI registration
soundwire: intel_ace2x: add sync_arm/sync_go helpers
soundwire: intel_ace2x: use common helpers for bus start/stop
soundwire: intel_ace2x: enable wake support
soundwire: intel_ace2x: add check_cmdsync_unlocked helper
soundwire: bus: add new manager callback to deal with peripheral
enumeration
soundwire: intel_ace2x: add new_peripheral_assigned callback
soundwire: intel_ace2x: add pre/post bank switch callbacks
ASoC: SOF/soundwire: re-add substream in params_stream structure
soundwire: intel: remove .trigger callback implementation
soundwire: intel: use substream for .trigger callback
soundwire: intel: remove .free callback implementation
soundwire: intel: use substream for .free callback
drivers/soundwire/Makefile | 3 +-
drivers/soundwire/bus.c | 3 +
drivers/soundwire/cadence_master.h | 2 +
drivers/soundwire/intel.c | 54 +---
drivers/soundwire/intel.h | 16 +
drivers/soundwire/intel_ace2x.c | 393 ++++++++++++++++++++++++
drivers/soundwire/intel_ace2x_debugfs.c | 147 +++++++++
drivers/soundwire/intel_auxdevice.c | 17 +
drivers/soundwire/intel_init.c | 21 +-
include/linux/soundwire/sdw.h | 3 +-
include/linux/soundwire/sdw_intel.h | 94 +++++-
sound/soc/sof/intel/hda.c | 33 +-
sound/soc/sof/intel/shim.h | 1 +
13 files changed, 723 insertions(+), 64 deletions(-)
create mode 100644 drivers/soundwire/intel_ace2x.c
create mode 100644 drivers/soundwire/intel_ace2x_debugfs.c
--
2.25.1
From: Pierre-Louis Bossart <[email protected]>
With the HDaudio extended link integration, the SHIM and IP registers
are split in blocks
a) SHIM generic registers
b) IP registers (same offsets for Cadence IP as before)
c) SHIM vendor-specific registers
Add offsets and definitions as defined in the hardware specifications.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Reviewed-by: Péter Ujfalusi <[email protected]>
Reviewed-by: Ranjani Sridharan <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
include/linux/soundwire/sdw_intel.h | 75 +++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 207701aeeb47..8e6183e029fa 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -7,6 +7,10 @@
#include <linux/irqreturn.h>
#include <linux/soundwire/sdw.h>
+/*********************************************************************
+ * cAVS and ACE1.x definitions
+ *********************************************************************/
+
#define SDW_SHIM_BASE 0x2C000
#define SDW_ALH_BASE 0x2C800
#define SDW_SHIM_BASE_ACE 0x38000
@@ -101,6 +105,77 @@
#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
+/*********************************************************************
+ * ACE2.x definitions for SHIM registers - only accessible when the
+ * HDAudio extended link LCTL.SPA/CPA = 1.
+ *********************************************************************/
+/* x variable is link index */
+#define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x))
+#define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x))
+#define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x))
+
+/* SHIM2 Generic Registers */
+/* Read-only capabilities */
+#define SDW_SHIM2_LECAP 0x00
+#define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */
+#define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */
+
+/* PCM Stream capabilities */
+#define SDW_SHIM2_PCMSCAP 0x10
+#define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */
+#define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */
+#define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */
+
+/* Read-only PCM Stream Channel Count, y variable is stream */
+#define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y)))
+#define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */
+
+/* PCM Stream Channel Map */
+#define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y)))
+#define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */
+#define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */
+#define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */
+#define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */
+
+/* SHIM2 vendor-specific registers */
+#define SDW_SHIM2_INTEL_VS_LVSCTL 0x04
+#define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26)
+#define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27)
+#define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30)
+#define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31)
+
+#define SDW_SHIM2_MLCS_XTAL_CLK 0x0
+#define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1
+#define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2
+#define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3
+#define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4
+
+#define SDW_SHIM2_INTEL_VS_WAKEEN 0x08
+#define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0)
+
+#define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A
+#define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0)
+
+#define SDW_SHIM2_INTEL_VS_IOCTL 0x0C
+#define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0)
+#define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1)
+#define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2)
+#define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3)
+#define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4)
+#define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5)
+#define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6)
+#define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7)
+#define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8)
+#define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9)
+#define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10)
+
+#define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E
+#define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0)
+#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1)
+#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
+#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
+#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
+
/**
* struct sdw_intel_stream_params_data: configuration passed during
* the @params_stream callback, e.g. for interaction with DSP
--
2.25.1
From: Pierre-Louis Bossart <[email protected]>
The interface is not needed for IPC3 solution but will be needed with
an updated parameter list for ACE2.x+IPC4 combinations.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Reviewed-by: Ranjani Sridharan <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/intel.c | 37 +------------------------------------
1 file changed, 1 insertion(+), 36 deletions(-)
diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index 15cecd2e062d..f52167aa48db 100644
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -663,25 +663,6 @@ static int intel_params_stream(struct sdw_intel *sdw,
return -EIO;
}
-static int intel_free_stream(struct sdw_intel *sdw,
- int stream,
- struct snd_soc_dai *dai,
- int link_id)
-{
- struct sdw_intel_link_res *res = sdw->link_res;
- struct sdw_intel_stream_free_data free_data;
-
- free_data.stream = stream; /* direction */
- free_data.dai = dai;
- free_data.link_id = link_id;
-
- if (res->ops && res->ops->free_stream && res->dev)
- return res->ops->free_stream(res->dev,
- &free_data);
-
- return 0;
-}
-
/*
* DAI routines
*/
@@ -817,7 +798,6 @@ static int
intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
- struct sdw_intel *sdw = cdns_to_intel(cdns);
struct sdw_cdns_dai_runtime *dai_runtime;
int ret;
@@ -838,12 +818,6 @@ intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
return ret;
}
- ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
- if (ret < 0) {
- dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
- return ret;
- }
-
dai_runtime->pdi = NULL;
return 0;
@@ -871,7 +845,6 @@ static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
{
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
- struct sdw_intel *sdw = cdns_to_intel(cdns);
struct sdw_cdns_dai_runtime *dai_runtime;
int ret = 0;
@@ -894,7 +867,6 @@ static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct sn
dai_runtime->suspended = true;
- ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
@@ -940,9 +912,7 @@ static int intel_component_dais_suspend(struct snd_soc_component *component)
*/
for_each_component_dais(component, dai) {
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
- struct sdw_intel *sdw = cdns_to_intel(cdns);
struct sdw_cdns_dai_runtime *dai_runtime;
- int ret;
dai_runtime = cdns->dai_runtime_array[dai->id];
@@ -952,13 +922,8 @@ static int intel_component_dais_suspend(struct snd_soc_component *component)
if (dai_runtime->suspended)
continue;
- if (dai_runtime->paused) {
+ if (dai_runtime->paused)
dai_runtime->suspended = true;
-
- ret = intel_free_stream(sdw, dai_runtime->direction, dai, sdw->instance);
- if (ret < 0)
- return ret;
- }
}
return 0;
--
2.25.1
On 15-05-23, 15:10, Bard Liao wrote:
> This series uses the abstraction added in past kernel cycles to provide
> support for the ACE2.x integration. The existing SHIM and Cadence
> registers are now split in 3 (SHIM, IP, SHIM vendor-specific), with some
> parts also moved to the HDaudio Extended Multi link structures. Nothing
> fundamentally different except for the register map.
>
> This series only provides the basic mechanisms to expose SoundWire-based
> DAIs. The PCI parts and DSP management will be contributed later, and the
> DAI ops are now empty as well.
>
> The change is mainly on SoundWire. It would be better to go through
> SoundWire tree.
Applied, thanks
--
~Vinod
On 5/27/23 05:36, Vinod Koul wrote:
> On 15-05-23, 15:10, Bard Liao wrote:
>> This series uses the abstraction added in past kernel cycles to provide
>> support for the ACE2.x integration. The existing SHIM and Cadence
>> registers are now split in 3 (SHIM, IP, SHIM vendor-specific), with some
>> parts also moved to the HDaudio Extended Multi link structures. Nothing
>> fundamentally different except for the register map.
>>
>> This series only provides the basic mechanisms to expose SoundWire-based
>> DAIs. The PCI parts and DSP management will be contributed later, and the
>> DAI ops are now empty as well.
>>
>> The change is mainly on SoundWire. It would be better to go through
>> SoundWire tree.
>
> Applied, thanks
Hi Vinod, is there a way you could provide an immutable tag for Mark
Brown, the patch1 in this set is required for my next set of ASoC
LunarLake patches?
"ASoC: SOF: Intel: shim: add enum for ACE 2.0 IP used in LunarLake" adds
the SOF_INTEL_ACE_2_0 definition to select different ops for LunarLake.
Thank you
-Pierre
Hi Pierre,
On 02-06-23, 15:46, Pierre-Louis Bossart wrote:
> On 5/27/23 05:36, Vinod Koul wrote:
> > On 15-05-23, 15:10, Bard Liao wrote:
> >> This series uses the abstraction added in past kernel cycles to provide
> >> support for the ACE2.x integration. The existing SHIM and Cadence
> >> registers are now split in 3 (SHIM, IP, SHIM vendor-specific), with some
> >> parts also moved to the HDaudio Extended Multi link structures. Nothing
> >> fundamentally different except for the register map.
> >>
> >> This series only provides the basic mechanisms to expose SoundWire-based
> >> DAIs. The PCI parts and DSP management will be contributed later, and the
> >> DAI ops are now empty as well.
> >>
> >> The change is mainly on SoundWire. It would be better to go through
> >> SoundWire tree.
> >
> > Applied, thanks
>
> Hi Vinod, is there a way you could provide an immutable tag for Mark
> Brown, the patch1 in this set is required for my next set of ASoC
> LunarLake patches?
Unfortunately, I have picked the whole series into next. If I was aware
I would have pushed them to a topic.
Mark can pull sdw/next but that would bring other things as well which
may not be preferred. I guess next best would be wait few weeks (rc1)
>
> "ASoC: SOF: Intel: shim: add enum for ACE 2.0 IP used in LunarLake" adds
> the SOF_INTEL_ACE_2_0 definition to select different ops for LunarLake.
>
> Thank you
> -Pierre
--
~Vinod
On 6/7/23 08:07, Vinod Koul wrote:
>
> Hi Pierre,
>
> On 02-06-23, 15:46, Pierre-Louis Bossart wrote:
>> On 5/27/23 05:36, Vinod Koul wrote:
>>> On 15-05-23, 15:10, Bard Liao wrote:
>>>> This series uses the abstraction added in past kernel cycles to provide
>>>> support for the ACE2.x integration. The existing SHIM and Cadence
>>>> registers are now split in 3 (SHIM, IP, SHIM vendor-specific), with some
>>>> parts also moved to the HDaudio Extended Multi link structures. Nothing
>>>> fundamentally different except for the register map.
>>>>
>>>> This series only provides the basic mechanisms to expose SoundWire-based
>>>> DAIs. The PCI parts and DSP management will be contributed later, and the
>>>> DAI ops are now empty as well.
>>>>
>>>> The change is mainly on SoundWire. It would be better to go through
>>>> SoundWire tree.
>>>
>>> Applied, thanks
>>
>> Hi Vinod, is there a way you could provide an immutable tag for Mark
>> Brown, the patch1 in this set is required for my next set of ASoC
>> LunarLake patches?
>
> Unfortunately, I have picked the whole series into next. If I was aware
> I would have pushed them to a topic.
>
> Mark can pull sdw/next but that would bring other things as well which
> may not be preferred. I guess next best would be wait few weeks (rc1)
Yeah, it's a miss on my side, I forgot about this one-line enum
dependency for DMIC/SSP.
SoundWire has more dependencies so we expected to send the relevant
patches in the next cycle. DMIC/SSP is quite simple and could have been
part of 6.5.
Oh well.
>> "ASoC: SOF: Intel: shim: add enum for ACE 2.0 IP used in LunarLake" adds
>> the SOF_INTEL_ACE_2_0 definition to select different ops for LunarLake.
>>
>> Thank you
>> -Pierre
>