2023-03-15 09:24:33

by Siddharth Vadapalli

Subject: [PATCH] dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G

The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
additional PHY modes like QSGMII. Add a compatible for it.

Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.

Signed-off-by: Siddharth Vadapalli <[email protected]>
---
Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index 6d46f57fa1b4..3f2c5e2a11d5 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -55,6 +55,7 @@ properties:
- ti,am654-phy-gmii-sel
- ti,j7200-cpsw5g-phy-gmii-sel
- ti,j721e-cpsw9g-phy-gmii-sel
+ - ti,j784s4-cpsw9g-phy-gmii-sel

reg:
maxItems: 1
@@ -87,6 +88,7 @@ allOf:
- ti,am654-phy-gmii-sel
- ti,j7200-cpsw5g-phy-gmii-sel
- ti,j721e-cpsw9g-phy-gmii-sel
+ - ti,j784s4-cpsw9g-phy-gmii-sel
then:
properties:
'#phy-cells':
@@ -113,6 +115,7 @@ allOf:
contains:
enum:
- ti,j721e-cpsw9g-phy-gmii-sel
+ - ti,j784s4-cpsw9g-phy-gmii-sel
then:
properties:
ti,qsgmii-main-ports:
@@ -130,6 +133,7 @@ allOf:
enum:
- ti,j7200-cpsw5g-phy-gmii-sel
- ti,j721e-cpsw9g-phy-gmii-sel
+ - ti,j784s4-cpsw9g-phy-gmii-sel
then:
properties:
ti,qsgmii-main-ports: false
--
2.25.1

2023-03-19 12:45:36

by Krzysztof Kozlowski

Subject: Re: [PATCH] dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G

On 15/03/2023 10:24, Siddharth Vadapalli wrote:
> The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
> additional PHY modes like QSGMII. Add a compatible for it.
>
> Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++
> 1 file changed, 4 insertions(+)

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2023-04-04 07:24:05

by Siddharth Vadapalli

Subject: Re: [PATCH] dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G

Hello Vinod,

Can this patch please be merged in case of no concerns?

Regards,
Siddharth.

On 19/03/23 18:15, Krzysztof Kozlowski wrote:
> On 15/03/2023 10:24, Siddharth Vadapalli wrote:
>> The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
>> additional PHY modes like QSGMII. Add a compatible for it.
>>
>> Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.
>>
>> Signed-off-by: Siddharth Vadapalli <[email protected]>
>> ---
>> Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
>
> Best regards,
> Krzysztof
>

2023-04-12 16:44:56

by Vinod Koul

Subject: Re: [PATCH] dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G

On 15-03-23, 14:54, Siddharth Vadapalli wrote:
> The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
> additional PHY modes like QSGMII. Add a compatible for it.
>
> Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.

Applied, thanks

--
~Vinod