Hi,
The series of patches add AMD Nolan (NL) SoC support for DesignWare USB3
OTG IP with PCI bus glue layer. This controller supported hibernation, LPM
erratum and used the 2.80a IP version and amd own phy. Current
implementation support both simulation and SoC platform. And already tested
with gadget zero and msc tool. It works well on file storage gadget.
These patches are generated on balbi/testing/next
Changes from v2 -> v3
- Confirmed these quirks will be needed in product level
- Move AMD configuration patch to the last one with all quirk flags
- Make all quirks as 1-bit field instead of single-bits on a 32-bit
variable
- Add all quirks DeviceTree counterparts
- Make LPM erratum configurable
- Add PCI ID into pci_ids.h because it will be used both on PCI and DWC3
device driver.
Changes from v1 -> v2
- Remove dual role function temporarily
- Add pci quirk to avoid to bind with xhci driver
- Distinguish between simulation board and soc
- Break down all the special quirks
Patch 1:
- Enable hibernation
Patch 2:
- Distinguish between simulation board and SoC
Patch 3:
- Initialize platform data at pci glue layer
Patch 4 - 16:
- Break down all the special quirks
Patch 17:
- Add PCI device ID of AMD NL USB3 DRD
Patch 18:
- Add PCI quirk to prevent DRD to bind with xHCI driver
Patch 19:
- Add support AMD NL USB3 DRD for dwc3 driver
Patch set already passed all the MSC testing on simulation board with low
clock frequency, so the speed will slower than true SoC. Detailed result
without verbose debug option is below:
root@hr-bak:/home/ray/felipe/usb-tools# ./msc.sh -o /dev/sdb1
Starting test suite: 2014年 10月 28日 星期二 19:30:28 CST
test 0a: simple 4k read/write
test 0: sent 3.91 MB read 7.18 MB/s write 6.51 MB/s ... success
test 0b: simple 8k read/write
test 0: sent 7.81 MB read 11.26 MB/s write 10.40 MB/s ... success
test 0c: simple 16k read/write
test 0: sent 15.62 MB read 14.82 MB/s write 12.41 MB/s ... success
test 0d: simple 32k read/write
test 0: sent 31.25 MB read 21.52 MB/s write 17.43 MB/s ... success
test 0e: simple 64k read/write
test 0: sent 62.50 MB read 24.14 MB/s write 19.44 MB/s ... success
test 1: simple 1-sector read/write
test 1: sent 500.00 kB read 1.19 MB/s write 1.03 MB/s ... success
test 2: simple 8-sectors read/write
test 2: sent 3.91 MB read 7.14 MB/s write 6.13 MB/s ... success
test 3: simple 32-sectors read/write
test 3: sent 15.62 MB read 15.49 MB/s write 12.25 MB/s ... success
test 4: simple 64-sectors read/write
test 4: sent 31.25 MB read 19.98 MB/s write 17.44 MB/s ... success
test 5a: scatter/gather for 2-sectors buflen 4k
test 5: sent 1000.00 kB read 2.42 MB/s write 2.15 MB/s ... success
test 5b: scatter/gather for 2-sectors buflen 8k
test 5: sent 1000.00 kB read 2.39 MB/s write 2.09 MB/s ... success
test 5c: scatter/gather for 2-sectors buflen 16k
test 5: sent 1000.00 kB read 2.37 MB/s write 1.91 MB/s ... success
test 5d: scatter/gather for 2-sectors buflen 32k
test 5: sent 1000.00 kB read 2.36 MB/s write 1.90 MB/s ... success
test 5e: scatter/gather for 2-sectors buflen 64k
test 5: sent 1000.00 kB read 2.37 MB/s write 1.88 MB/s ... success
test 6a: scatter/gather for 8-sectors buflen 4k
test 6: sent 3.91 MB read 7.08 MB/s write 6.26 MB/s ... success
test 6b: scatter/gather for 8-sectors buflen 8k
test 6: sent 3.91 MB read 7.12 MB/s write 6.35 MB/s ... success
test 6c: scatter/gather for 8-sectors buflen 16k
test 6: sent 3.91 MB read 7.11 MB/s write 6.34 MB/s ... success
test 6d: scatter/gather for 8-sectors buflen 32k
test 6: sent 3.91 MB read 7.14 MB/s write 6.30 MB/s ... success
test 6e: scatter/gather for 8-sectors buflen 64k
test 6: sent 3.91 MB read 7.13 MB/s write 6.34 MB/s ... success
test 7a: scatter/gather for 32-sectors buflen 16k
test 7: sent 15.62 MB read 15.25 MB/s write 12.48 MB/s ... success
test 7b: scatter/gather for 32-sectors buflen 32k
test 7: sent 15.62 MB read 15.36 MB/s write 12.33 MB/s ... success
test 7c: scatter/gather for 32-sectors buflen 64k
test 7: sent 15.62 MB read 15.21 MB/s write 12.01 MB/s ... success
test 8a: scatter/gather for 64-sectors buflen 32k
test 8: sent 31.25 MB read 21.46 MB/s write 17.75 MB/s ... success
test 8b: scatter/gather for 64-sectors buflen 64k
test 8: sent 31.25 MB read 20.00 MB/s write 17.37 MB/s ... success
test 9: scatter/gather for 128-sectors buflen 64k
test 9: sent 62.50 MB read 22.34 MB/s write 19.13 MB/s ... success
test 10: read over the end of the block device
test 10: sent 62.01 MB read 0.00 MB/s write 0.00 MB/s ... success
test 11: lseek past the end of the block device
test 11: sent 0.00 B read 0.00 MB/s write 0.00 MB/s ... success
test 12: write over the end of the block device
test 12: sent 0.00 B read 0.00 MB/s write 0.00 MB/s ... success
test 13: write 1 sg, read 8 random size sgs
test 13: sent 62.50 MB read 22.91 MB/s write 19.63 MB/s ... success
test 14: write 8 random size sgs, read 1 sg
test 14: sent 62.50 MB read 23.84 MB/s write 19.25 MB/s ... success
test 15: write and read 8 random size sgs
test 15: sent 62.50 MB read 23.56 MB/s write 19.07 MB/s ... success
test 16a: read with heap allocated buffer
test 16: sent 62.50 MB read 22.42 MB/s write 0.00 MB/s ... success
test 16b: read with stack allocated buffer
test 16: sent 62.50 MB read 21.77 MB/s write 0.00 MB/s ... success
test 17a: write with heap allocated buffer
test 17: sent 0.00 B read 0.00 MB/s write 20.26 MB/s ... success
test 17b: write with stack allocated buffer
test 17: sent 0.00 B read 0.00 MB/s write 21.71 MB/s ... success
test 18a: write 0x00 and read it back
test 18: sent 62.50 MB read 22.36 MB/s write 19.00 MB/s ... success
test 18b: write 0xff and read it back
test 18: sent 62.50 MB read 21.25 MB/s write 17.80 MB/s ... success
test 18c: write 0x55 and read it back
test 18: sent 62.50 MB read 24.99 MB/s write 18.85 MB/s ... success
test 18d: write 0xaa and read it back
test 18: sent 62.50 MB read 22.74 MB/s write 19.07 MB/s ... success
test 18e: write 0x11 and read it back
test 18: sent 62.50 MB read 22.81 MB/s write 19.04 MB/s ... success
test 18f: write 0x22 and read it back
test 18: sent 62.50 MB read 22.37 MB/s write 18.90 MB/s ... success
test 18g: write 0x44 and read it back
test 18: sent 62.50 MB read 22.54 MB/s write 18.91 MB/s ... success
test 18h: write 0x88 and read it back
test 18: sent 62.50 MB read 22.31 MB/s write 19.05 MB/s ... success
test 18i: write 0x33 and read it back
test 18: sent 62.50 MB read 22.55 MB/s write 18.86 MB/s ... success
test 18j: write 0x66 and read it back
test 18: sent 62.50 MB read 22.60 MB/s write 18.85 MB/s ... success
test 18k: write 0x99 and read it back
test 18: sent 62.50 MB read 22.57 MB/s write 18.86 MB/s ... success
test 18l: write 0xcc and read it back
test 18: sent 62.50 MB read 22.54 MB/s write 18.83 MB/s ... success
test 18m: write 0x77 and read it back
test 18: sent 62.50 MB read 22.80 MB/s write 18.98 MB/s ... success
test 18n: write 0xbb and read it back
test 18: sent 62.50 MB read 22.87 MB/s write 18.79 MB/s ... success
test 18o: write 0xdd and read it back
test 18: sent 62.50 MB read 22.34 MB/s write 18.99 MB/s ... success
test 18p: write 0xee and read it back
test 18: sent 62.50 MB read 24.95 MB/s write 19.33 MB/s ... success
Test suite ended: 2014年 10月 28日 星期二 19:33:50 CST
Thanks,
Rui
Huang Rui (19):
usb: dwc3: enable hibernation if to be supported
usb: dwc3: add a flag to check if it is fpga board
usb: dwc3: initialize platform data at pci glue layer
usb: dwc3: add disscramble quirk
usb: dwc3: add lpm erratum support
usb: dwc3: add u2exit lfps quirk
usb: dwc3: add P3 in U2 SS inactive quirk
usb: dwc3: add request p1p2p3 quirk
usb: dwc3: add delay p1p2p3 quirk
usb: dwc3: add delay phy power change quirk
usb: dwc3: add lfps filter quirk
usb: dwc3: add rx_detect to polling lfps quirk
usb: dwc3: add tx demphasis quirk
usb: dwc3: set SUSPHY bit for all cores
usb: dwc3: add disable usb3 suspend phy quirk
usb: dwc3: add disable usb2 suspend phy quirk
PCI: Add support for AMD Nolan USB3 DRD
PCI: Add quirk to prevent AMD NL USB3 DRD to bind with xHCI driver
usb: dwc3: add support for AMD NL platform
drivers/pci/quirks.c | 20 +++++
drivers/usb/dwc3/core.c | 158 ++++++++++++++++++++++++++++++++++++++-
drivers/usb/dwc3/core.h | 74 +++++++++++++++---
drivers/usb/dwc3/dwc3-pci.c | 28 +++++++
drivers/usb/dwc3/gadget.c | 13 ++++
drivers/usb/dwc3/platform_data.h | 17 +++++
include/linux/pci_ids.h | 1 +
7 files changed, 300 insertions(+), 11 deletions(-)
--
1.9.1
Some chip vendor is on pre-silicon phase, which needs to use the simulation
board. It should have the same product and vendor id with the true soc, but
might have some minor different configurations.
Below thread discussion proposes to find a method to distinguish between
simulation board and soc.
http://marc.info/?l=linux-usb&m=141194772206369&w=2
In Andvanced Configuration of coreConsultant, there is the parameter of
DWC_USB_EN_FPGA. This bit has the function we need. And it would response as 7
bit of GHWPARAMS6 register. So it's able to check this functional bit to confirm
if works on FPGA board.
Reported-by: Felipe Balbi <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 5 +++++
2 files changed, 11 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index bf77509..ddac372 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -455,6 +455,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
dev_dbg(dwc->dev, "No power optimization available\n");
}
+ /* check if current dwc3 is on simulation board */
+ if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
+ dev_dbg(dwc->dev, "it is on FPGA board\n");
+ dwc->is_fpga = true;
+ }
+
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a715ee1..f6ee623 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -210,6 +210,9 @@
#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
#define DWC3_MAX_HIBER_SCRATCHBUFS 15
+/* Global HWPARAMS6 Register */
+#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
+
/* Device Configuration Register */
#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
@@ -662,6 +665,7 @@ struct dwc3_scratchpad_array {
* @ep0_expect_in: true when we expect a DATA IN transfer
* @has_hibernation: true when dwc3 was configured with Hibernation
* @is_selfpowered: true when we are selfpowered
+ * @is_fpga: true when we are using the FPGA board
* @needs_fifo_resize: not all users might want fifo resizing, flag it
* @pullups_connected: true when Run/Stop bit is set
* @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
@@ -765,6 +769,7 @@ struct dwc3 {
unsigned ep0_expect_in:1;
unsigned has_hibernation:1;
unsigned is_selfpowered:1;
+ unsigned is_fpga:1;
unsigned needs_fifo_resize:1;
unsigned pullups_connected:1;
unsigned resize_fifos:1;
--
1.9.1
This patch adds u2exit lfps quirk, and some special platforms can configure
that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 4f37a43..6abf4e9 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -468,6 +468,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
else
reg &= ~DWC3_GCTL_DISSCRAMBLE;
+ if (dwc->u2exit_lfps_quirk)
+ reg |= DWC3_GCTL_U2EXIT_LFPS;
+
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
@@ -724,6 +727,8 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->disable_scramble_quirk = of_property_read_bool(node,
"snps,disable_scramble_quirk");
+ dwc->u2exit_lfps_quirk = of_property_read_bool(node,
+ "snps,u2exit_lfps_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -734,6 +739,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->dr_mode = pdata->dr_mode;
dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
+ dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 19d1ecb..03e0505 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -166,6 +166,7 @@
#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
+#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
@@ -679,6 +680,7 @@ struct dwc3_scratchpad_array {
* @start_config_issued: true when StartConfig command has been issued
* @three_stage_setup: set if we perform a three phase setup
* @disable_scramble_quirk: set if we enable the disable scramble quirk
+ * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -787,6 +789,7 @@ struct dwc3 {
unsigned three_stage_setup:1;
unsigned disable_scramble_quirk:1;
+ unsigned u2exit_lfps_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 2e546ac..4e91e09 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -28,4 +28,5 @@ struct dwc3_platform_data {
unsigned disable_scramble_quirk:1;
unsigned has_lpm_erratum:1;
unsigned lpm_nyet_thres:4;
+ unsigned u2exit_lfps_quirk:1;
};
--
1.9.1
This patch adds P3 in U2 SS inactive quirk, and some special platforms can
configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 27 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 6abf4e9..ccc54df 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -365,6 +365,24 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
}
/**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ */
+static void dwc3_phy_setup(struct dwc3 *dwc)
+{
+ u32 reg;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+
+ if (dwc->u2ss_inp3_quirk)
+ reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
+
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+
+ mdelay(100);
+}
+
+/**
* dwc3_core_init - Low-level initialization of DWC3 Core
* @dwc: Pointer to our controller context structure
*
@@ -484,6 +502,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+ dwc3_phy_setup(dwc);
+
ret = dwc3_alloc_scratch_buffers(dwc);
if (ret)
goto err1;
@@ -729,6 +749,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,disable_scramble_quirk");
dwc->u2exit_lfps_quirk = of_property_read_bool(node,
"snps,u2exit_lfps_quirk");
+ dwc->u2ss_inp3_quirk = of_property_read_bool(node,
+ "snps,u2ss_inp3_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -740,6 +762,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
+ dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 03e0505..f230668 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -176,6 +176,7 @@
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
+#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
@@ -681,6 +682,7 @@ struct dwc3_scratchpad_array {
* @three_stage_setup: set if we perform a three phase setup
* @disable_scramble_quirk: set if we enable the disable scramble quirk
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
+ * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -790,6 +792,7 @@ struct dwc3 {
unsigned disable_scramble_quirk:1;
unsigned u2exit_lfps_quirk:1;
+ unsigned u2ss_inp3_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 4e91e09..b5906a3 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -29,4 +29,5 @@ struct dwc3_platform_data {
unsigned has_lpm_erratum:1;
unsigned lpm_nyet_thres:4;
unsigned u2exit_lfps_quirk:1;
+ unsigned u2ss_inp3_quirk:1;
};
--
1.9.1
This patch adds delay P0 to P1/P2/P3 quirk for U2/U2/U3, and some special
platforms can configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 5 +++++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 12 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 021ebf3..244c71a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -380,6 +380,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->req_p1p2p3_quirk)
reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
+ if (dwc->del_p1p2p3_quirk)
+ reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -756,6 +759,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,u2ss_inp3_quirk");
dwc->req_p1p2p3_quirk = of_property_read_bool(node,
"snps,req_p1p2p3_quirk");
+ dwc->del_p1p2p3_quirk = of_property_read_bool(node,
+ "snps,del_p1p2p3_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -769,6 +774,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
+ dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e1aca71..a91f42d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -178,6 +178,9 @@
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
+#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
+#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
+#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
@@ -685,6 +688,7 @@ struct dwc3_scratchpad_array {
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
* @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
+ * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -796,6 +800,7 @@ struct dwc3 {
unsigned u2exit_lfps_quirk:1;
unsigned u2ss_inp3_quirk:1;
unsigned req_p1p2p3_quirk:1;
+ unsigned del_p1p2p3_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 457ee9c..6dca665 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -31,4 +31,5 @@ struct dwc3_platform_data {
unsigned u2exit_lfps_quirk:1;
unsigned u2ss_inp3_quirk:1;
unsigned req_p1p2p3_quirk:1;
+ unsigned del_p1p2p3_quirk:1;
};
--
1.9.1
This patch adds delay PHY power change from P0 to P1/P2/P3 when link state
changing from U0 to U1/U2/U3 respectively, and some special platforms can
configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 244c71a..97796d7 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -383,6 +383,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->del_p1p2p3_quirk)
reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
+ if (dwc->del_phy_power_chg_quirk)
+ reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -761,6 +764,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,req_p1p2p3_quirk");
dwc->del_p1p2p3_quirk = of_property_read_bool(node,
"snps,del_p1p2p3_quirk");
+ dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
+ "snps,del_phy_power_chg_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -775,6 +780,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
+ dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a91f42d..13bc46b 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -181,6 +181,7 @@
#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
+#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
@@ -689,6 +690,7 @@ struct dwc3_scratchpad_array {
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
* @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
* @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
+ * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -801,6 +803,7 @@ struct dwc3 {
unsigned u2ss_inp3_quirk:1;
unsigned req_p1p2p3_quirk:1;
unsigned del_p1p2p3_quirk:1;
+ unsigned del_phy_power_chg_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 6dca665..1dea0c0 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -32,4 +32,5 @@ struct dwc3_platform_data {
unsigned u2ss_inp3_quirk:1;
unsigned req_p1p2p3_quirk:1;
unsigned del_p1p2p3_quirk:1;
+ unsigned del_phy_power_chg_quirk:1;
};
--
1.9.1
This patch adds RX_DETECT to Polling.LFPS control quirk, and some special
platforms can configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 86ed064..19019dc 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -389,6 +389,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->lfps_filter_quirk)
reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
+ if (dwc->rx_detect_poll_quirk)
+ reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -771,6 +774,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,del_phy_power_chg_quirk");
dwc->lfps_filter_quirk = of_property_read_bool(node,
"snps,lfps_filter_quirk");
+ dwc->rx_detect_poll_quirk = of_property_read_bool(node,
+ "snps,rx_detect_poll_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -787,6 +792,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
+ dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 23b48a0..57a203a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -184,6 +184,7 @@
#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
+#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
/* Global TX Fifo Size Register */
#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
@@ -693,6 +694,7 @@ struct dwc3_scratchpad_array {
* @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
* @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
* @lfps_filter_quirk: set if we enable LFPS filter quirk
+ * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -807,6 +809,7 @@ struct dwc3 {
unsigned del_p1p2p3_quirk:1;
unsigned del_phy_power_chg_quirk:1;
unsigned lfps_filter_quirk:1;
+ unsigned rx_detect_poll_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 89918e5..9776764 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -34,4 +34,5 @@ struct dwc3_platform_data {
unsigned del_p1p2p3_quirk:1;
unsigned del_phy_power_chg_quirk:1;
unsigned lfps_filter_quirk:1;
+ unsigned rx_detect_poll_quirk:1;
};
--
1.9.1
It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core
initialization is completed above the dwc3 revision 1.94a.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index e36fcd0..7b5cd76 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -374,6 +374,15 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+ /*
+ * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
+ * to '0' during coreConsultant configuration. So default value
+ * will be '0' when the core is reset. Application needs to set it
+ * to '1' after the core initialization is completed.
+ */
+ if (dwc->revision > DWC3_REVISION_194A)
+ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+
if (dwc->u2ss_inp3_quirk)
reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
@@ -398,6 +407,21 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+
+ /*
+ * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
+ * '0' during coreConsultant configuration. So default value will
+ * be '0' when the core is reset. Application needs to set it to
+ * '1' after the core initialization is completed.
+ */
+ if (dwc->revision > DWC3_REVISION_194A)
+ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+
+ mdelay(100);
}
/**
--
1.9.1
This patch adds disable usb3 suspend phy quirk, and some special platforms
can configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 2 ++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7b5cd76..aec393b 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -404,6 +404,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->tx_deemph_quirk)
reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_deemph);
+ if (dwc->dis_u3_susphy_quirk)
+ reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -807,6 +810,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,lfps_filter_quirk");
dwc->rx_detect_poll_quirk = of_property_read_bool(node,
"snps,rx_detect_poll_quirk");
+ dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
+ "snps,dis_u3_susphy_quirk");
dwc->tx_deemph_quirk = of_property_read_bool(node,
"snps,tx_deemph_quirk");
@@ -829,6 +834,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
+ dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
dwc->tx_deemph_quirk = pdata->tx_deemph_quirk;
if (pdata->tx_deemph)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 1277dcf..686d3b9 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -697,6 +697,7 @@ struct dwc3_scratchpad_array {
* @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
* @lfps_filter_quirk: set if we enable LFPS filter quirk
* @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
+ * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
* @tx_deemph_quirk: set if we enable Tx deemphasis quirk
* @tx_deemph: Tx deemphasis value
* 0 - -6dB de-emphasis
@@ -818,6 +819,7 @@ struct dwc3 {
unsigned del_phy_power_chg_quirk:1;
unsigned lfps_filter_quirk:1;
unsigned rx_detect_poll_quirk:1;
+ unsigned dis_u3_susphy_quirk:1;
unsigned tx_deemph_quirk:1;
unsigned tx_deemph:2;
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index ea631dc..c8115c7 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -35,6 +35,7 @@ struct dwc3_platform_data {
unsigned del_phy_power_chg_quirk:1;
unsigned lfps_filter_quirk:1;
unsigned rx_detect_poll_quirk:1;
+ unsigned dis_u3_susphy_quirk:1;
unsigned tx_deemph_quirk:1;
unsigned tx_deemph:2;
--
1.9.1
This patch adds disable usb2 suspend phy quirk, and some special platforms
can configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 2 ++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index aec393b..33a8f3c 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -422,6 +422,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->revision > DWC3_REVISION_194A)
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+ if (dwc->dis_u2_susphy_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100);
@@ -812,6 +815,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,rx_detect_poll_quirk");
dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
"snps,dis_u3_susphy_quirk");
+ dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
+ "snps,dis_u2_susphy_quirk");
dwc->tx_deemph_quirk = of_property_read_bool(node,
"snps,tx_deemph_quirk");
@@ -835,6 +840,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
+ dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
dwc->tx_deemph_quirk = pdata->tx_deemph_quirk;
if (pdata->tx_deemph)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 686d3b9..8b94ad5 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -698,6 +698,7 @@ struct dwc3_scratchpad_array {
* @lfps_filter_quirk: set if we enable LFPS filter quirk
* @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
* @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
+ * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
* @tx_deemph_quirk: set if we enable Tx deemphasis quirk
* @tx_deemph: Tx deemphasis value
* 0 - -6dB de-emphasis
@@ -820,6 +821,7 @@ struct dwc3 {
unsigned lfps_filter_quirk:1;
unsigned rx_detect_poll_quirk:1;
unsigned dis_u3_susphy_quirk:1;
+ unsigned dis_u2_susphy_quirk:1;
unsigned tx_deemph_quirk:1;
unsigned tx_deemph:2;
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index c8115c7..1cfd384 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -36,6 +36,7 @@ struct dwc3_platform_data {
unsigned lfps_filter_quirk:1;
unsigned rx_detect_poll_quirk:1;
unsigned dis_u3_susphy_quirk:1;
+ unsigned dis_u2_susphy_quirk:1;
unsigned tx_deemph_quirk:1;
unsigned tx_deemph:2;
--
1.9.1
This patch adds PCI id for USB3 Dual-Role Device of AMD Nolan (NL) SoC.
It will be used for PCI quirks and DWC3 device driver.
Signed-off-by: Jason Chang <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
---
include/linux/pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1fa99a3..5decad7 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -562,6 +562,7 @@
#define PCI_DEVICE_ID_AMD_8131_BRIDGE 0x7450
#define PCI_DEVICE_ID_AMD_8131_APIC 0x7451
#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458
+#define PCI_DEVICE_ID_AMD_NL_USB 0x7912
#define PCI_DEVICE_ID_AMD_CS5535_IDE 0x208F
#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090
#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091
--
1.9.1
The AMD Nolan (NL) SoC contains a DesignWare USB3 Dual-Role Device that can
be operated either as a USB Host or a USB Device. In the AMD NL platform,
this device ([1022:7912]) has a class code of PCI_CLASS_SERIAL_USB_XHCI
(0x0c0330), which means the xhci driver will claim it.
But the dwc3 driver is a more specific driver for this device, and we'd
prefer to use it instead of xhci. To prevent xhci from claiming the
device, change the class code to 0x0c03fe, which the PCI r3.0 spec defines
as "USB device (not host controller)". The dwc3 driver can then claim it
based on its Vendor and Device ID.
Suggested-by: Heikki Krogerus <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Jason Chang <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
---
drivers/pci/quirks.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 90acb32..1152bef 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -379,6 +379,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
/*
+ * In the AMD NL platform, this device ([1022:7912]) has a class code of
+ * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
+ * claim it.
+ * But the dwc3 driver is a more specific driver for this device, and we'd
+ * prefer to use it instead of xhci. To prevent xhci from claiming the
+ * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
+ * defines as "USB device (not host controller)". The dwc3 driver can then
+ * claim it based on its Vendor and Device ID.
+ */
+static void quirk_amd_nl_class(struct pci_dev *pdev)
+{
+ /*
+ * Use 'USB Device' (0x0x03fe) instead of PCI header provided
+ */
+ pdev->class = 0x0c03fe;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
+ quirk_amd_nl_class);
+
+/*
* Let's make the southbridge information explicit instead
* of having to worry about people probing the ACPI areas,
* for example.. (Yes, it happens, and if you read the wrong
--
1.9.1
This patch adds support for AMD Nolan (NL) FPGA and SoC platform.
Cc: Jason Chang <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 9 +++++++++
drivers/usb/dwc3/core.h | 2 ++
drivers/usb/dwc3/dwc3-pci.c | 19 +++++++++++++++++++
drivers/usb/dwc3/platform_data.h | 1 +
4 files changed, 31 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 33a8f3c..7ab867b 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -526,6 +526,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc->is_fpga = true;
}
+ if (dwc->amd_nl_plat && dwc->is_fpga) {
+ dwc->disable_scramble_quirk = true;
+ dwc->dis_u3_susphy_quirk = true;
+ dwc->dis_u2_susphy_quirk = true;
+ }
+
WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
"disable_scramble cannot be used on non-FPGA builds\n");
@@ -817,6 +823,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,dis_u3_susphy_quirk");
dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
"snps,dis_u2_susphy_quirk");
+ dwc->amd_nl_plat = of_property_read_bool(node,
+ "snps,amd_nl_plat");
dwc->tx_deemph_quirk = of_property_read_bool(node,
"snps,tx_deemph_quirk");
@@ -841,6 +849,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
+ dwc->amd_nl_plat = pdata->amd_nl_plat;
dwc->tx_deemph_quirk = pdata->tx_deemph_quirk;
if (pdata->tx_deemph)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8b94ad5..b08a2f9 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -699,6 +699,7 @@ struct dwc3_scratchpad_array {
* @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
* @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
* @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
+ * @amd_nl_plat: set if we use AMD NL platform
* @tx_deemph_quirk: set if we enable Tx deemphasis quirk
* @tx_deemph: Tx deemphasis value
* 0 - -6dB de-emphasis
@@ -822,6 +823,7 @@ struct dwc3 {
unsigned rx_detect_poll_quirk:1;
unsigned dis_u3_susphy_quirk:1;
unsigned dis_u2_susphy_quirk:1;
+ unsigned amd_nl_plat:1;
unsigned tx_deemph_quirk:1;
unsigned tx_deemph:2;
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index ada975f..3af9b47 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -145,6 +145,24 @@ static int dwc3_pci_probe(struct pci_dev *pci,
res[1].name = "dwc_usb3";
res[1].flags = IORESOURCE_IRQ;
+ if (pci->vendor == PCI_VENDOR_ID_AMD &&
+ pci->device == PCI_DEVICE_ID_AMD_NL_USB) {
+ dwc3_pdata.has_lpm_erratum = true;
+ dwc3_pdata.lpm_nyet_thres = 0xf;
+
+ dwc3_pdata.u2exit_lfps_quirk = true;
+ dwc3_pdata.u2ss_inp3_quirk = true;
+ dwc3_pdata.req_p1p2p3_quirk = true;
+ dwc3_pdata.del_p1p2p3_quirk = true;
+ dwc3_pdata.del_phy_power_chg_quirk = true;
+ dwc3_pdata.lfps_filter_quirk = true;
+ dwc3_pdata.rx_detect_poll_quirk = true;
+ dwc3_pdata.amd_nl_plat = true;
+
+ dwc3_pdata.tx_deemph_quirk = true;
+ dwc3_pdata.tx_deemph = 1;
+ }
+
ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
if (ret) {
dev_err(dev, "couldn't add resources to dwc3 device\n");
@@ -194,6 +212,7 @@ static const struct pci_device_id dwc3_pci_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
{ } /* Terminating Entry */
};
MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 1cfd384..c2c3511 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -37,6 +37,7 @@ struct dwc3_platform_data {
unsigned rx_detect_poll_quirk:1;
unsigned dis_u3_susphy_quirk:1;
unsigned dis_u2_susphy_quirk:1;
+ unsigned amd_nl_plat:1;
unsigned tx_deemph_quirk:1;
unsigned tx_deemph:2;
--
1.9.1
This patch adds Tx demphasis quirk, and the Tx demphasis value is
configurable according to PIPE3 specification.
Value Description
0 -6dB de-emphasis
1 -3.5dB de-emphasis
2 No de-emphasis
3 Reserved
It can be configured on DT or platform data.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 17 +++++++++++++++++
drivers/usb/dwc3/core.h | 11 +++++++++++
drivers/usb/dwc3/platform_data.h | 3 +++
3 files changed, 31 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 19019dc..e36fcd0 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -392,6 +392,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->rx_detect_poll_quirk)
reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
+ if (dwc->tx_deemph_quirk)
+ reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_deemph);
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -691,6 +694,7 @@ static int dwc3_probe(struct platform_device *pdev)
struct resource *res;
struct dwc3 *dwc;
u8 lpm_nyet_thres;
+ u8 tx_deemph;
int ret;
@@ -749,6 +753,9 @@ static int dwc3_probe(struct platform_device *pdev)
/* default to highest possible threshold */
lpm_nyet_thres = 0xff;
+ /* default to -3.5dB de-emphasis */
+ tx_deemph = 1;
+
if (node) {
dwc->maximum_speed = of_usb_get_maximum_speed(node);
dwc->has_lpm_erratum = of_property_read_bool(node,
@@ -776,6 +783,11 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,lfps_filter_quirk");
dwc->rx_detect_poll_quirk = of_property_read_bool(node,
"snps,rx_detect_poll_quirk");
+
+ dwc->tx_deemph_quirk = of_property_read_bool(node,
+ "snps,tx_deemph_quirk");
+ of_property_read_u8(node, "snps,tx_deemph",
+ &tx_deemph);
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -793,6 +805,10 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
+
+ dwc->tx_deemph_quirk = pdata->tx_deemph_quirk;
+ if (pdata->tx_deemph)
+ tx_deemph = pdata->tx_deemph;
}
/* default to superspeed if no maximum_speed passed */
@@ -800,6 +816,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->maximum_speed = USB_SPEED_SUPER;
dwc->lpm_nyet_thres = lpm_nyet_thres;
+ dwc->tx_deemph = tx_deemph;
ret = dwc3_core_get_phy(dwc);
if (ret)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 57a203a..1277dcf 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -185,6 +185,8 @@
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
+#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
+#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
/* Global TX Fifo Size Register */
#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
@@ -695,6 +697,12 @@ struct dwc3_scratchpad_array {
* @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
* @lfps_filter_quirk: set if we enable LFPS filter quirk
* @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
+ * @tx_deemph_quirk: set if we enable Tx deemphasis quirk
+ * @tx_deemph: Tx deemphasis value
+ * 0 - -6dB de-emphasis
+ * 1 - -3.5dB de-emphasis
+ * 2 - No de-emphasis
+ * 3 - Reserved
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -810,6 +818,9 @@ struct dwc3 {
unsigned del_phy_power_chg_quirk:1;
unsigned lfps_filter_quirk:1;
unsigned rx_detect_poll_quirk:1;
+
+ unsigned tx_deemph_quirk:1;
+ unsigned tx_deemph:2;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 9776764..ea631dc 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -35,4 +35,7 @@ struct dwc3_platform_data {
unsigned del_phy_power_chg_quirk:1;
unsigned lfps_filter_quirk:1;
unsigned rx_detect_poll_quirk:1;
+
+ unsigned tx_deemph_quirk:1;
+ unsigned tx_deemph:2;
};
--
1.9.1
This patch adds LFPS filter quirk, and some special platforms can configure
that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 97796d7..86ed064 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -386,6 +386,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->del_phy_power_chg_quirk)
reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
+ if (dwc->lfps_filter_quirk)
+ reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -766,6 +769,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,del_p1p2p3_quirk");
dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
"snps,del_phy_power_chg_quirk");
+ dwc->lfps_filter_quirk = of_property_read_bool(node,
+ "snps,lfps_filter_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -781,6 +786,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
+ dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 13bc46b..23b48a0 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -183,6 +183,7 @@
#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
+#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
/* Global TX Fifo Size Register */
#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
@@ -691,6 +692,7 @@ struct dwc3_scratchpad_array {
* @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
* @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
* @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
+ * @lfps_filter_quirk: set if we enable LFPS filter quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -804,6 +806,7 @@ struct dwc3 {
unsigned req_p1p2p3_quirk:1;
unsigned del_p1p2p3_quirk:1;
unsigned del_phy_power_chg_quirk:1;
+ unsigned lfps_filter_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 1dea0c0..89918e5 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -33,4 +33,5 @@ struct dwc3_platform_data {
unsigned req_p1p2p3_quirk:1;
unsigned del_p1p2p3_quirk:1;
unsigned del_phy_power_chg_quirk:1;
+ unsigned lfps_filter_quirk:1;
};
--
1.9.1
This patch adds request P1/P2/P3 quirk for U2/U2/U3, and some special
platforms can configure that if it is needed.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 6 ++++++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ccc54df..021ebf3 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -377,6 +377,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->u2ss_inp3_quirk)
reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
+ if (dwc->req_p1p2p3_quirk)
+ reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
mdelay(100);
@@ -751,6 +754,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,u2exit_lfps_quirk");
dwc->u2ss_inp3_quirk = of_property_read_bool(node,
"snps,u2ss_inp3_quirk");
+ dwc->req_p1p2p3_quirk = of_property_read_bool(node,
+ "snps,req_p1p2p3_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -763,6 +768,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
+ dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index f230668..e1aca71 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -177,6 +177,7 @@
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
+#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
@@ -683,6 +684,7 @@ struct dwc3_scratchpad_array {
* @disable_scramble_quirk: set if we enable the disable scramble quirk
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
+ * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -793,6 +795,7 @@ struct dwc3 {
unsigned disable_scramble_quirk:1;
unsigned u2exit_lfps_quirk:1;
unsigned u2ss_inp3_quirk:1;
+ unsigned req_p1p2p3_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index b5906a3..457ee9c 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -30,4 +30,5 @@ struct dwc3_platform_data {
unsigned lpm_nyet_thres:4;
unsigned u2exit_lfps_quirk:1;
unsigned u2ss_inp3_quirk:1;
+ unsigned req_p1p2p3_quirk:1;
};
--
1.9.1
When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced
Configuration of coreConsultant, it supports of xHCI BESL Errata Dated
10/19/2011 is enabled in host mode. In device mode it adds the capability
to send NYET response threshold based on the BESL value received in the LPM
token, and the threhold is configurable for each soc platform.
This patch adds an entry that soc platform is able to define the lpm
capacity with their own device tree or bus glue layer.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 16 +++++++++++++++-
drivers/usb/dwc3/core.h | 26 +++++++++++++++++---------
drivers/usb/dwc3/gadget.c | 13 +++++++++++++
drivers/usb/dwc3/platform_data.h | 2 ++
4 files changed, 47 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index c320835..4f37a43 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -652,6 +652,7 @@ static int dwc3_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
struct resource *res;
struct dwc3 *dwc;
+ u8 lpm_nyet_thres;
int ret;
@@ -707,16 +708,27 @@ static int dwc3_probe(struct platform_device *pdev)
*/
res->start -= DWC3_GLOBALS_REGS_START;
+ /* default to highest possible threshold */
+ lpm_nyet_thres = 0xff;
+
if (node) {
dwc->maximum_speed = of_usb_get_maximum_speed(node);
+ dwc->has_lpm_erratum = of_property_read_bool(node,
+ "snps,has-lpm-erratum");
+ of_property_read_u8(node, "snps,lpm-nyet-thres",
+ &lpm_nyet_thres);
- dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
+ dwc->needs_fifo_resize = of_property_read_bool(node,
+ "tx-fifo-resize");
dwc->dr_mode = of_usb_get_dr_mode(node);
dwc->disable_scramble_quirk = of_property_read_bool(node,
"snps,disable_scramble_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
+ dwc->has_lpm_erratum = pdata->has_lpm_erratum;
+ if (pdata->lpm_nyet_thres)
+ lpm_nyet_thres = pdata->lpm_nyet_thres;
dwc->needs_fifo_resize = pdata->tx_fifo_resize;
dwc->dr_mode = pdata->dr_mode;
@@ -728,6 +740,8 @@ static int dwc3_probe(struct platform_device *pdev)
if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
dwc->maximum_speed = USB_SPEED_SUPER;
+ dwc->lpm_nyet_thres = lpm_nyet_thres;
+
ret = dwc3_core_get_phy(dwc);
if (ret)
return ret;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 56bada6..19d1ecb 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -246,16 +246,19 @@
#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
/* These apply for core versions 1.94a and later */
-#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
-#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
-#define DWC3_DCTL_CRS (1 << 17)
-#define DWC3_DCTL_CSS (1 << 16)
+#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
+#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
-#define DWC3_DCTL_INITU2ENA (1 << 12)
-#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
-#define DWC3_DCTL_INITU1ENA (1 << 10)
-#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
-#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
+#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
+#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
+#define DWC3_DCTL_CRS (1 << 17)
+#define DWC3_DCTL_CSS (1 << 16)
+
+#define DWC3_DCTL_INITU2ENA (1 << 12)
+#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
+#define DWC3_DCTL_INITU1ENA (1 << 10)
+#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
+#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
@@ -664,6 +667,9 @@ struct dwc3_scratchpad_array {
* @ep0_bounced: true when we used bounce buffer
* @ep0_expect_in: true when we expect a DATA IN transfer
* @has_hibernation: true when dwc3 was configured with Hibernation
+ * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
+ * there's now way for software to detect this in runtime.
+ * @lpm_nyet_thres: LPM NYET response threshold
* @is_selfpowered: true when we are selfpowered
* @is_fpga: true when we are using the FPGA board
* @needs_fifo_resize: not all users might want fifo resizing, flag it
@@ -769,6 +775,8 @@ struct dwc3 {
unsigned ep0_bounced:1;
unsigned ep0_expect_in:1;
unsigned has_hibernation:1;
+ unsigned has_lpm_erratum:1;
+ unsigned lpm_nyet_thres:4;
unsigned is_selfpowered:1;
unsigned is_fpga:1;
unsigned needs_fifo_resize:1;
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 7a64c2f..b918a65 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2297,6 +2297,19 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
*/
reg |= DWC3_DCTL_HIRD_THRES(12);
+ /*
+ * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
+ * DCFG.LPMCap is set, core responses with an ACK and the
+ * BESL value in the LPM token is less than or equal to lPM
+ * NYET threshold.
+ */
+ WARN(dwc->revision < DWC3_REVISION_240A
+ && dwc->has_lpm_erratum,
+ "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
+
+ if (dwc->has_lpm_erratum)
+ reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_thres);
+
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
} else {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 9209d02..2e546ac 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -26,4 +26,6 @@ struct dwc3_platform_data {
bool tx_fifo_resize;
unsigned disable_scramble_quirk:1;
+ unsigned has_lpm_erratum:1;
+ unsigned lpm_nyet_thres:4;
};
--
1.9.1
This patch adds disscramble quirk, and it only needs to be enabled at fpga
board on some vendor platforms.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 14 +++++++++++++-
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/platform_data.h | 2 ++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ddac372..c320835 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
- reg &= ~DWC3_GCTL_DISSCRAMBLE;
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
@@ -461,6 +460,14 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc->is_fpga = true;
}
+ WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
+ "disable_scramble cannot be used on non-FPGA builds\n");
+
+ if (dwc->disable_scramble_quirk && dwc->is_fpga)
+ reg |= DWC3_GCTL_DISSCRAMBLE;
+ else
+ reg &= ~DWC3_GCTL_DISSCRAMBLE;
+
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
@@ -705,11 +712,16 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
dwc->dr_mode = of_usb_get_dr_mode(node);
+
+ dwc->disable_scramble_quirk = of_property_read_bool(node,
+ "snps,disable_scramble_quirk");
} else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed;
dwc->needs_fifo_resize = pdata->tx_fifo_resize;
dwc->dr_mode = pdata->dr_mode;
+
+ dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index f6ee623..56bada6 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -672,6 +672,7 @@ struct dwc3_scratchpad_array {
* @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
* @start_config_issued: true when StartConfig command has been issued
* @three_stage_setup: set if we perform a three phase setup
+ * @disable_scramble_quirk: set if we enable the disable scramble quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -776,6 +777,8 @@ struct dwc3 {
unsigned setup_packet_pending:1;
unsigned start_config_issued:1;
unsigned three_stage_setup:1;
+
+ unsigned disable_scramble_quirk:1;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 7db34f0..9209d02 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -24,4 +24,6 @@ struct dwc3_platform_data {
enum usb_device_speed maximum_speed;
enum usb_dr_mode dr_mode;
bool tx_fifo_resize;
+
+ unsigned disable_scramble_quirk:1;
};
--
1.9.1
This patch initializes platform data at pci glue layer, and SoCs x86-based
platform vendor is able to define their flags in platform data at bus glue
layer. Then do some independent behaviors at dwc3 core level.
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/dwc3-pci.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index a36cf66..ada975f 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -25,6 +25,8 @@
#include <linux/usb/otg.h>
#include <linux/usb/usb_phy_generic.h>
+#include "platform_data.h"
+
/* FIXME define these in <linux/pci_ids.h> */
#define PCI_VENDOR_ID_SYNOPSYS 0x16c3
#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
@@ -102,6 +104,9 @@ static int dwc3_pci_probe(struct pci_dev *pci,
struct dwc3_pci *glue;
int ret;
struct device *dev = &pci->dev;
+ struct dwc3_platform_data dwc3_pdata;
+
+ memset(&dwc3_pdata, 0x00, sizeof(dwc3_pdata));
glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
if (!glue)
@@ -148,6 +153,10 @@ static int dwc3_pci_probe(struct pci_dev *pci,
pci_set_drvdata(pci, glue);
+ ret = platform_device_add_data(dwc3, &dwc3_pdata, sizeof(dwc3_pdata));
+ if (ret)
+ goto err3;
+
dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
dwc3->dev.dma_mask = dev->dma_mask;
--
1.9.1
It enables hibernation if the function is set in coreConsultant.
Suggested-by: Felipe Balbi <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
---
drivers/usb/dwc3/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fa396fc..bf77509 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
/* enable hibernation here */
dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
+ reg |= DWC3_GCTL_GBLHIBERNATIONEN;
break;
default:
dev_dbg(dwc->dev, "No power optimization available\n");
--
1.9.1
Hello.
On 10/28/2014 2:54 PM, Huang Rui wrote:
> The AMD Nolan (NL) SoC contains a DesignWare USB3 Dual-Role Device that can
> be operated either as a USB Host or a USB Device. In the AMD NL platform,
> this device ([1022:7912]) has a class code of PCI_CLASS_SERIAL_USB_XHCI
> (0x0c0330), which means the xhci driver will claim it.
> But the dwc3 driver is a more specific driver for this device, and we'd
> prefer to use it instead of xhci. To prevent xhci from claiming the
> device, change the class code to 0x0c03fe, which the PCI r3.0 spec defines
> as "USB device (not host controller)". The dwc3 driver can then claim it
> based on its Vendor and Device ID.
> Suggested-by: Heikki Krogerus <[email protected]>
> Cc: Bjorn Helgaas <[email protected]>
> Cc: Jason Chang <[email protected]>
> Signed-off-by: Huang Rui <[email protected]>
> ---
> drivers/pci/quirks.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 90acb32..1152bef 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -379,6 +379,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
>
> /*
> + * In the AMD NL platform, this device ([1022:7912]) has a class code of
> + * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
> + * claim it.
> + * But the dwc3 driver is a more specific driver for this device, and we'd
> + * prefer to use it instead of xhci. To prevent xhci from claiming the
> + * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
> + * defines as "USB device (not host controller)". The dwc3 driver can then
> + * claim it based on its Vendor and Device ID.
> + */
> +static void quirk_amd_nl_class(struct pci_dev *pdev)
> +{
> + /*
> + * Use 'USB Device' (0x0x03fe) instead of PCI header provided
0x0c03fe, you mean?
> + */
> + pdev->class = 0x0c03fe;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
I'm not sure it was a good idea to declare the ID in pci_ids.h -- it's
been long discouraged.
WBR, Sergei
On Tue, Oct 28, 2014 at 03:06:31PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 10/28/2014 2:54 PM, Huang Rui wrote:
>
> >The AMD Nolan (NL) SoC contains a DesignWare USB3 Dual-Role Device that can
> >be operated either as a USB Host or a USB Device. In the AMD NL platform,
> >this device ([1022:7912]) has a class code of PCI_CLASS_SERIAL_USB_XHCI
> >(0x0c0330), which means the xhci driver will claim it.
>
> >But the dwc3 driver is a more specific driver for this device, and we'd
> >prefer to use it instead of xhci. To prevent xhci from claiming the
> >device, change the class code to 0x0c03fe, which the PCI r3.0 spec defines
> >as "USB device (not host controller)". The dwc3 driver can then claim it
> >based on its Vendor and Device ID.
>
> >Suggested-by: Heikki Krogerus <[email protected]>
> >Cc: Bjorn Helgaas <[email protected]>
> >Cc: Jason Chang <[email protected]>
> >Signed-off-by: Huang Rui <[email protected]>
> >---
> > drivers/pci/quirks.c | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
>
> >diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> >index 90acb32..1152bef 100644
> >--- a/drivers/pci/quirks.c
> >+++ b/drivers/pci/quirks.c
> >@@ -379,6 +379,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
> >
> > /*
> >+ * In the AMD NL platform, this device ([1022:7912]) has a class code of
> >+ * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
> >+ * claim it.
> >+ * But the dwc3 driver is a more specific driver for this device, and we'd
> >+ * prefer to use it instead of xhci. To prevent xhci from claiming the
> >+ * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
> >+ * defines as "USB device (not host controller)". The dwc3 driver can then
> >+ * claim it based on its Vendor and Device ID.
> >+ */
> >+static void quirk_amd_nl_class(struct pci_dev *pdev)
> >+{
> >+ /*
> >+ * Use 'USB Device' (0x0x03fe) instead of PCI header provided
>
> 0x0c03fe, you mean?
Yes. That's a typo, 'USB Device' class code should be 0x0c03fe, will
update.
>
> >+ */
> >+ pdev->class = 0x0c03fe;
> >+}
> >+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
>
> I'm not sure it was a good idea to declare the ID in pci_ids.h --
> it's been long discouraged.
>
You're right. But PCI_DEVICE_ID_AMD_NL_USB will be used on two
drivers(pci and dwc3). It also might be used for identifying AMD NL
chip for another drivers in future.
Thanks,
Rui
I suggest a subject like this:
PCI: Prevent xHCI driver from claiming AMD Nolan USB3 DRD device
On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> The AMD Nolan (NL) SoC contains a DesignWare USB3 Dual-Role Device that can
> be operated either as a USB Host or a USB Device. In the AMD NL platform,
> this device ([1022:7912]) has a class code of PCI_CLASS_SERIAL_USB_XHCI
> (0x0c0330), which means the xhci driver will claim it.
>
> But the dwc3 driver is a more specific driver for this device, and we'd
> prefer to use it instead of xhci. To prevent xhci from claiming the
> device, change the class code to 0x0c03fe, which the PCI r3.0 spec defines
> as "USB device (not host controller)". The dwc3 driver can then claim it
> based on its Vendor and Device ID.
>
> Suggested-by: Heikki Krogerus <[email protected]>
> Cc: Bjorn Helgaas <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Please merge along with the rest of your series.
> Cc: Jason Chang <[email protected]>
> Signed-off-by: Huang Rui <[email protected]>
> ---
> drivers/pci/quirks.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 90acb32..1152bef 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -379,6 +379,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
>
> /*
> + * In the AMD NL platform, this device ([1022:7912]) has a class code of
> + * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
> + * claim it.
> + * But the dwc3 driver is a more specific driver for this device, and we'd
> + * prefer to use it instead of xhci. To prevent xhci from claiming the
> + * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
> + * defines as "USB device (not host controller)". The dwc3 driver can then
> + * claim it based on its Vendor and Device ID.
> + */
> +static void quirk_amd_nl_class(struct pci_dev *pdev)
> +{
> + /*
> + * Use 'USB Device' (0x0x03fe) instead of PCI header provided
> + */
> + pdev->class = 0x0c03fe;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
> + quirk_amd_nl_class);
> +
> +/*
> * Let's make the southbridge information explicit instead
> * of having to worry about people probing the ACPI areas,
> * for example.. (Yes, it happens, and if you read the wrong
> --
> 1.9.1
>
On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> This patch adds PCI id for USB3 Dual-Role Device of AMD Nolan (NL) SoC.
> It will be used for PCI quirks and DWC3 device driver.
>
> Signed-off-by: Jason Chang <[email protected]>
> Signed-off-by: Huang Rui <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Please merge along with the rest of your series.
> ---
> include/linux/pci_ids.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 1fa99a3..5decad7 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -562,6 +562,7 @@
> #define PCI_DEVICE_ID_AMD_8131_BRIDGE 0x7450
> #define PCI_DEVICE_ID_AMD_8131_APIC 0x7451
> #define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458
> +#define PCI_DEVICE_ID_AMD_NL_USB 0x7912
> #define PCI_DEVICE_ID_AMD_CS5535_IDE 0x208F
> #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090
> #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091
> --
> 1.9.1
>
Hi,
almost there...
On Tue, Oct 28, 2014 at 07:54:40PM +0800, Huang Rui wrote:
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 8b94ad5..b08a2f9 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -699,6 +699,7 @@ struct dwc3_scratchpad_array {
> * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
> * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
> * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
> + * @amd_nl_plat: set if we use AMD NL platform
however, as I mentioned before, the core shouldn't have to know that
it's running on an AMD platform. We already support several different
platforms (OMAP5, AM437x, DRA7xx, Exynos5, Exynos7, Qcom, Merrifield,
Baytrail, Braswell, HAPS PCIe, and STiH407) and none of them get their
$my_awesome_platform flag in dwc3, why should AMD be any different ?
This is the only part of $subject that I cannot accept because it would
mean we would be giving AMD a special treatment when there shouldn't be
any, for anybody.
--
balbi
On Tue, Oct 28, 2014 at 08:38:56AM -0500, Felipe Balbi wrote:
> Hi,
>
> almost there...
>
> On Tue, Oct 28, 2014 at 07:54:40PM +0800, Huang Rui wrote:
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index 8b94ad5..b08a2f9 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -699,6 +699,7 @@ struct dwc3_scratchpad_array {
> > * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
> > * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
> > * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
> > + * @amd_nl_plat: set if we use AMD NL platform
>
> however, as I mentioned before, the core shouldn't have to know that
> it's running on an AMD platform. We already support several different
> platforms (OMAP5, AM437x, DRA7xx, Exynos5, Exynos7, Qcom, Merrifield,
> Baytrail, Braswell, HAPS PCIe, and STiH407) and none of them get their
> $my_awesome_platform flag in dwc3, why should AMD be any different ?
>
> This is the only part of $subject that I cannot accept because it would
> mean we would be giving AMD a special treatment when there shouldn't be
> any, for anybody.
>
That's because I used this flag to enable below quirks on AMD NL FPGA
board, and FPGA flag only can be detected on core. Can I set
disable_scramble_quirk, dis_u3_susphy_quirk, and dis_u2_susphy_quirk
for all the FPGA platforms?
if (dwc->amd_nl_plat && dwc->is_fpga) {
dwc->disable_scramble_quirk = true;
dwc->dis_u3_susphy_quirk = true;
dwc->dis_u2_susphy_quirk = true;
}
Thanks,
Rui
Hi,
On Tue, Oct 28, 2014 at 07:54:21PM +0800, Huang Rui wrote:
> Hi,
>
> The series of patches add AMD Nolan (NL) SoC support for DesignWare USB3
> OTG IP with PCI bus glue layer. This controller supported hibernation, LPM
> erratum and used the 2.80a IP version and amd own phy. Current
> implementation support both simulation and SoC platform. And already tested
> with gadget zero and msc tool. It works well on file storage gadget.
>
>
> These patches are generated on balbi/testing/next
>
> Changes from v2 -> v3
> - Confirmed these quirks will be needed in product level
> - Move AMD configuration patch to the last one with all quirk flags
> - Make all quirks as 1-bit field instead of single-bits on a 32-bit
> variable
> - Add all quirks DeviceTree counterparts
> - Make LPM erratum configurable
> - Add PCI ID into pci_ids.h because it will be used both on PCI and DWC3
> device driver.
>
> Changes from v1 -> v2
> - Remove dual role function temporarily
> - Add pci quirk to avoid to bind with xhci driver
> - Distinguish between simulation board and soc
> - Break down all the special quirks
In all patches touching DeviceTree, you should add the matching binding
documentation under Documentation/devicetree/bindings/usb/dwc3.txt
There are still a few cases where you're clipping words too harshly, for
example tx_deemph doesn't look very intuitive, if you spell it out as
tx_deemphasis, it's easier to read. Remember that humans will be the
ones fiddling with those quirks.
A few of your patches I have fixed myself and they now sit on
testing/next, please rebase your remaining changes there and make sure
to add DeviceTree documentation.
When resending, please resend the entire series (even the ones I have
already taken) because you also didn't Cc devicetree mailing list.
cheers
--
balbi
On Tue, Oct 28, 2014 at 09:41:56AM -0500, Felipe Balbi wrote:
> Hi,
>
> On Tue, Oct 28, 2014 at 07:54:21PM +0800, Huang Rui wrote:
> > Hi,
> >
> > The series of patches add AMD Nolan (NL) SoC support for DesignWare USB3
> > OTG IP with PCI bus glue layer. This controller supported hibernation, LPM
> > erratum and used the 2.80a IP version and amd own phy. Current
> > implementation support both simulation and SoC platform. And already tested
> > with gadget zero and msc tool. It works well on file storage gadget.
> >
> >
> > These patches are generated on balbi/testing/next
> >
> > Changes from v2 -> v3
> > - Confirmed these quirks will be needed in product level
> > - Move AMD configuration patch to the last one with all quirk flags
> > - Make all quirks as 1-bit field instead of single-bits on a 32-bit
> > variable
> > - Add all quirks DeviceTree counterparts
> > - Make LPM erratum configurable
> > - Add PCI ID into pci_ids.h because it will be used both on PCI and DWC3
> > device driver.
> >
> > Changes from v1 -> v2
> > - Remove dual role function temporarily
> > - Add pci quirk to avoid to bind with xhci driver
> > - Distinguish between simulation board and soc
> > - Break down all the special quirks
>
> In all patches touching DeviceTree, you should add the matching binding
> documentation under Documentation/devicetree/bindings/usb/dwc3.txt
>
OK, will add this documentation.
> There are still a few cases where you're clipping words too harshly, for
> example tx_deemph doesn't look very intuitive, if you spell it out as
> tx_deemphasis, it's easier to read. Remember that humans will be the
> ones fiddling with those quirks.
>
> A few of your patches I have fixed myself and they now sit on
> testing/next, please rebase your remaining changes there and make sure
> to add DeviceTree documentation.
>
> When resending, please resend the entire series (even the ones I have
> already taken) because you also didn't Cc devicetree mailing list.
>
Got it, could I also Cc stable mailing list and make them back port to
stable trees?
Thanks,
Rui
On Tue, Oct 28, 2014 at 11:17:16PM +0800, Huang Rui wrote:
> On Tue, Oct 28, 2014 at 09:41:56AM -0500, Felipe Balbi wrote:
> > Hi,
> >
> > On Tue, Oct 28, 2014 at 07:54:21PM +0800, Huang Rui wrote:
> > > Hi,
> > >
> > > The series of patches add AMD Nolan (NL) SoC support for DesignWare USB3
> > > OTG IP with PCI bus glue layer. This controller supported hibernation, LPM
> > > erratum and used the 2.80a IP version and amd own phy. Current
> > > implementation support both simulation and SoC platform. And already tested
> > > with gadget zero and msc tool. It works well on file storage gadget.
> > >
> > >
> > > These patches are generated on balbi/testing/next
> > >
> > > Changes from v2 -> v3
> > > - Confirmed these quirks will be needed in product level
> > > - Move AMD configuration patch to the last one with all quirk flags
> > > - Make all quirks as 1-bit field instead of single-bits on a 32-bit
> > > variable
> > > - Add all quirks DeviceTree counterparts
> > > - Make LPM erratum configurable
> > > - Add PCI ID into pci_ids.h because it will be used both on PCI and DWC3
> > > device driver.
> > >
> > > Changes from v1 -> v2
> > > - Remove dual role function temporarily
> > > - Add pci quirk to avoid to bind with xhci driver
> > > - Distinguish between simulation board and soc
> > > - Break down all the special quirks
> >
> > In all patches touching DeviceTree, you should add the matching binding
> > documentation under Documentation/devicetree/bindings/usb/dwc3.txt
> >
>
> OK, will add this documentation.
>
> > There are still a few cases where you're clipping words too harshly, for
> > example tx_deemph doesn't look very intuitive, if you spell it out as
> > tx_deemphasis, it's easier to read. Remember that humans will be the
> > ones fiddling with those quirks.
> >
> > A few of your patches I have fixed myself and they now sit on
> > testing/next, please rebase your remaining changes there and make sure
> > to add DeviceTree documentation.
> >
> > When resending, please resend the entire series (even the ones I have
> > already taken) because you also didn't Cc devicetree mailing list.
> >
>
> Got it, could I also Cc stable mailing list and make them back port to
> stable trees?
there are no bug fixes, are there ? Please read
Documentation/stable_kernel_rules.txt
--
balbi
On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> This patch adds Tx demphasis quirk, and the Tx demphasis value is
"demphasis" (above and in subject) should be "de-emphasis" as used in
the code and comments below.
> configurable according to PIPE3 specification.
>
> Value Description
> 0 -6dB de-emphasis
> 1 -3.5dB de-emphasis
> 2 No de-emphasis
> 3 Reserved
>
> It can be configured on DT or platform data.
>
> Signed-off-by: Huang Rui <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 17 +++++++++++++++++
> drivers/usb/dwc3/core.h | 11 +++++++++++
> drivers/usb/dwc3/platform_data.h | 3 +++
> 3 files changed, 31 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 19019dc..e36fcd0 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -392,6 +392,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->rx_detect_poll_quirk)
> reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
>
> + if (dwc->tx_deemph_quirk)
> + reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_deemph);
> +
> dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
>
> mdelay(100);
> @@ -691,6 +694,7 @@ static int dwc3_probe(struct platform_device *pdev)
> struct resource *res;
> struct dwc3 *dwc;
> u8 lpm_nyet_thres;
> + u8 tx_deemph;
>
> int ret;
>
> @@ -749,6 +753,9 @@ static int dwc3_probe(struct platform_device *pdev)
> /* default to highest possible threshold */
> lpm_nyet_thres = 0xff;
>
> + /* default to -3.5dB de-emphasis */
> + tx_deemph = 1;
> +
> if (node) {
> dwc->maximum_speed = of_usb_get_maximum_speed(node);
> dwc->has_lpm_erratum = of_property_read_bool(node,
> @@ -776,6 +783,11 @@ static int dwc3_probe(struct platform_device *pdev)
> "snps,lfps_filter_quirk");
> dwc->rx_detect_poll_quirk = of_property_read_bool(node,
> "snps,rx_detect_poll_quirk");
> +
> + dwc->tx_deemph_quirk = of_property_read_bool(node,
> + "snps,tx_deemph_quirk");
> + of_property_read_u8(node, "snps,tx_deemph",
> + &tx_deemph);
> } else if (pdata) {
> dwc->maximum_speed = pdata->maximum_speed;
> dwc->has_lpm_erratum = pdata->has_lpm_erratum;
> @@ -793,6 +805,10 @@ static int dwc3_probe(struct platform_device *pdev)
> dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
> dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
> dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
> +
> + dwc->tx_deemph_quirk = pdata->tx_deemph_quirk;
> + if (pdata->tx_deemph)
> + tx_deemph = pdata->tx_deemph;
> }
>
> /* default to superspeed if no maximum_speed passed */
> @@ -800,6 +816,7 @@ static int dwc3_probe(struct platform_device *pdev)
> dwc->maximum_speed = USB_SPEED_SUPER;
>
> dwc->lpm_nyet_thres = lpm_nyet_thres;
> + dwc->tx_deemph = tx_deemph;
>
> ret = dwc3_core_get_phy(dwc);
> if (ret)
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 57a203a..1277dcf 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -185,6 +185,8 @@
> #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
> #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
> #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
> +#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
> +#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
>
> /* Global TX Fifo Size Register */
> #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
> @@ -695,6 +697,12 @@ struct dwc3_scratchpad_array {
> * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
> * @lfps_filter_quirk: set if we enable LFPS filter quirk
> * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
> + * @tx_deemph_quirk: set if we enable Tx deemphasis quirk
> + * @tx_deemph: Tx deemphasis value
> + * 0 - -6dB de-emphasis
> + * 1 - -3.5dB de-emphasis
> + * 2 - No de-emphasis
> + * 3 - Reserved
> */
> struct dwc3 {
> struct usb_ctrlrequest *ctrl_req;
> @@ -810,6 +818,9 @@ struct dwc3 {
> unsigned del_phy_power_chg_quirk:1;
> unsigned lfps_filter_quirk:1;
> unsigned rx_detect_poll_quirk:1;
> +
> + unsigned tx_deemph_quirk:1;
> + unsigned tx_deemph:2;
> };
>
> /* -------------------------------------------------------------------------- */
> diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
> index 9776764..ea631dc 100644
> --- a/drivers/usb/dwc3/platform_data.h
> +++ b/drivers/usb/dwc3/platform_data.h
> @@ -35,4 +35,7 @@ struct dwc3_platform_data {
> unsigned del_phy_power_chg_quirk:1;
> unsigned lfps_filter_quirk:1;
> unsigned rx_detect_poll_quirk:1;
> +
> + unsigned tx_deemph_quirk:1;
> + unsigned tx_deemph:2;
> };
> --
> 1.9.1
>
On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced
"Advanced"
> Configuration of coreConsultant, it supports of xHCI BESL Errata Dated
I can't parse "is supports of" and I don't know enough to suggest an
alternate wording.
> 10/19/2011 is enabled in host mode. In device mode it adds the capability
> to send NYET response threshold based on the BESL value received in the LPM
> token, and the threhold is configurable for each soc platform.
"threshold"
> This patch adds an entry that soc platform is able to define the lpm
> capacity with their own device tree or bus glue layer.
>
> Signed-off-by: Huang Rui <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 16 +++++++++++++++-
> drivers/usb/dwc3/core.h | 26 +++++++++++++++++---------
> drivers/usb/dwc3/gadget.c | 13 +++++++++++++
> drivers/usb/dwc3/platform_data.h | 2 ++
> 4 files changed, 47 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index c320835..4f37a43 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -652,6 +652,7 @@ static int dwc3_probe(struct platform_device *pdev)
> struct device_node *node = dev->of_node;
> struct resource *res;
> struct dwc3 *dwc;
> + u8 lpm_nyet_thres;
>
> int ret;
>
> @@ -707,16 +708,27 @@ static int dwc3_probe(struct platform_device *pdev)
> */
> res->start -= DWC3_GLOBALS_REGS_START;
>
> + /* default to highest possible threshold */
> + lpm_nyet_thres = 0xff;
> +
> if (node) {
> dwc->maximum_speed = of_usb_get_maximum_speed(node);
> + dwc->has_lpm_erratum = of_property_read_bool(node,
> + "snps,has-lpm-erratum");
> + of_property_read_u8(node, "snps,lpm-nyet-thres",
> + &lpm_nyet_thres);
>
> - dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
> + dwc->needs_fifo_resize = of_property_read_bool(node,
> + "tx-fifo-resize");
> dwc->dr_mode = of_usb_get_dr_mode(node);
>
> dwc->disable_scramble_quirk = of_property_read_bool(node,
> "snps,disable_scramble_quirk");
> } else if (pdata) {
> dwc->maximum_speed = pdata->maximum_speed;
> + dwc->has_lpm_erratum = pdata->has_lpm_erratum;
> + if (pdata->lpm_nyet_thres)
> + lpm_nyet_thres = pdata->lpm_nyet_thres;
>
> dwc->needs_fifo_resize = pdata->tx_fifo_resize;
> dwc->dr_mode = pdata->dr_mode;
> @@ -728,6 +740,8 @@ static int dwc3_probe(struct platform_device *pdev)
> if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
> dwc->maximum_speed = USB_SPEED_SUPER;
>
> + dwc->lpm_nyet_thres = lpm_nyet_thres;
> +
> ret = dwc3_core_get_phy(dwc);
> if (ret)
> return ret;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 56bada6..19d1ecb 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -246,16 +246,19 @@
> #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
>
> /* These apply for core versions 1.94a and later */
> -#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
> -#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
> -#define DWC3_DCTL_CRS (1 << 17)
> -#define DWC3_DCTL_CSS (1 << 16)
> +#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
> +#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
>
> -#define DWC3_DCTL_INITU2ENA (1 << 12)
> -#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
> -#define DWC3_DCTL_INITU1ENA (1 << 10)
> -#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
> -#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
> +#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
> +#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
> +#define DWC3_DCTL_CRS (1 << 17)
> +#define DWC3_DCTL_CSS (1 << 16)
> +
> +#define DWC3_DCTL_INITU2ENA (1 << 12)
> +#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
> +#define DWC3_DCTL_INITU1ENA (1 << 10)
> +#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
> +#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
>
> #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
> #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
> @@ -664,6 +667,9 @@ struct dwc3_scratchpad_array {
> * @ep0_bounced: true when we used bounce buffer
> * @ep0_expect_in: true when we expect a DATA IN transfer
> * @has_hibernation: true when dwc3 was configured with Hibernation
> + * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
> + * there's now way for software to detect this in runtime.
"no way" (not "now way"). Also, "at runtime" is more idiomatic than
"in runtime."
> + * @lpm_nyet_thres: LPM NYET response threshold
> * @is_selfpowered: true when we are selfpowered
> * @is_fpga: true when we are using the FPGA board
> * @needs_fifo_resize: not all users might want fifo resizing, flag it
> @@ -769,6 +775,8 @@ struct dwc3 {
> unsigned ep0_bounced:1;
> unsigned ep0_expect_in:1;
> unsigned has_hibernation:1;
> + unsigned has_lpm_erratum:1;
> + unsigned lpm_nyet_thres:4;
> unsigned is_selfpowered:1;
> unsigned is_fpga:1;
> unsigned needs_fifo_resize:1;
> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> index 7a64c2f..b918a65 100644
> --- a/drivers/usb/dwc3/gadget.c
> +++ b/drivers/usb/dwc3/gadget.c
> @@ -2297,6 +2297,19 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
> */
> reg |= DWC3_DCTL_HIRD_THRES(12);
>
> + /*
> + * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
> + * DCFG.LPMCap is set, core responses with an ACK and the
> + * BESL value in the LPM token is less than or equal to lPM
> + * NYET threshold.
> + */
> + WARN(dwc->revision < DWC3_REVISION_240A
> + && dwc->has_lpm_erratum,
> + "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
> +
> + if (dwc->has_lpm_erratum)
> + reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_thres);
> +
> dwc3_writel(dwc->regs, DWC3_DCTL, reg);
> } else {
> reg = dwc3_readl(dwc->regs, DWC3_DCTL);
> diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
> index 9209d02..2e546ac 100644
> --- a/drivers/usb/dwc3/platform_data.h
> +++ b/drivers/usb/dwc3/platform_data.h
> @@ -26,4 +26,6 @@ struct dwc3_platform_data {
> bool tx_fifo_resize;
>
> unsigned disable_scramble_quirk:1;
> + unsigned has_lpm_erratum:1;
> + unsigned lpm_nyet_thres:4;
> };
> --
> 1.9.1
>
On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> This patch adds disscramble quirk, and it only needs to be enabled at fpga
"disscramble" (in subject and above) is not a real word.
I see that DWC3_GCTL_DISSCRAMBLE is already defined in
drivers/usb/dwc3/core.h even before your patches, so I suppose it's
something the hardware designers made up.
Maybe it means "descramble" (or "unscramble"). Or maybe it means
"disable scrambling"? A comment might make this clearer. A better
name would be even better.
> board on some vendor platforms.
>
> Signed-off-by: Huang Rui <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 14 +++++++++++++-
> drivers/usb/dwc3/core.h | 3 +++
> drivers/usb/dwc3/platform_data.h | 2 ++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ddac372..c320835 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
>
> reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> - reg &= ~DWC3_GCTL_DISSCRAMBLE;
>
> switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> @@ -461,6 +460,14 @@ static int dwc3_core_init(struct dwc3 *dwc)
> dwc->is_fpga = true;
> }
>
> + WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
> + "disable_scramble cannot be used on non-FPGA builds\n");
> +
> + if (dwc->disable_scramble_quirk && dwc->is_fpga)
> + reg |= DWC3_GCTL_DISSCRAMBLE;
> + else
> + reg &= ~DWC3_GCTL_DISSCRAMBLE;
> +
> /*
> * WORKAROUND: DWC3 revisions <1.90a have a bug
> * where the device can fail to connect at SuperSpeed
> @@ -705,11 +712,16 @@ static int dwc3_probe(struct platform_device *pdev)
>
> dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
> dwc->dr_mode = of_usb_get_dr_mode(node);
> +
> + dwc->disable_scramble_quirk = of_property_read_bool(node,
> + "snps,disable_scramble_quirk");
> } else if (pdata) {
> dwc->maximum_speed = pdata->maximum_speed;
>
> dwc->needs_fifo_resize = pdata->tx_fifo_resize;
> dwc->dr_mode = pdata->dr_mode;
> +
> + dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
> }
>
> /* default to superspeed if no maximum_speed passed */
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index f6ee623..56bada6 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -672,6 +672,7 @@ struct dwc3_scratchpad_array {
> * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
> * @start_config_issued: true when StartConfig command has been issued
> * @three_stage_setup: set if we perform a three phase setup
> + * @disable_scramble_quirk: set if we enable the disable scramble quirk
> */
> struct dwc3 {
> struct usb_ctrlrequest *ctrl_req;
> @@ -776,6 +777,8 @@ struct dwc3 {
> unsigned setup_packet_pending:1;
> unsigned start_config_issued:1;
> unsigned three_stage_setup:1;
> +
> + unsigned disable_scramble_quirk:1;
> };
>
> /* -------------------------------------------------------------------------- */
> diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
> index 7db34f0..9209d02 100644
> --- a/drivers/usb/dwc3/platform_data.h
> +++ b/drivers/usb/dwc3/platform_data.h
> @@ -24,4 +24,6 @@ struct dwc3_platform_data {
> enum usb_device_speed maximum_speed;
> enum usb_dr_mode dr_mode;
> bool tx_fifo_resize;
> +
> + unsigned disable_scramble_quirk:1;
> };
> --
> 1.9.1
>
Hi,
On Tue, Oct 28, 2014 at 10:39:26AM -0600, Bjorn Helgaas wrote:
> On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> > This patch adds disscramble quirk, and it only needs to be enabled at fpga
>
> "disscramble" (in subject and above) is not a real word.
>
> I see that DWC3_GCTL_DISSCRAMBLE is already defined in
> drivers/usb/dwc3/core.h even before your patches, so I suppose it's
> something the hardware designers made up.
hehe, disable scramble :-)
--
balbi
On Tue, Oct 28, 2014 at 10:27:27AM -0600, Bjorn Helgaas wrote:
> On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> > This patch adds Tx demphasis quirk, and the Tx demphasis value is
>
> "demphasis" (above and in subject) should be "de-emphasis" as used in
> the code and comments below.
+1
--
balbi
> From: Huang Rui [mailto:[email protected]]
> Sent: Tuesday, October 28, 2014 4:54 AM
>
> It enables hibernation if the function is set in coreConsultant.
>
> Suggested-by: Felipe Balbi <[email protected]>
> Signed-off-by: Huang Rui <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index fa396fc..bf77509 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> /* enable hibernation here */
> dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> break;
> default:
> dev_dbg(dwc->dev, "No power optimization available\n");
What effect does this have when the controller is in device mode? I
expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
events when this register bit is set. So the dev_WARN_ONCE in
dwc3_gadget_interrupt() will start firing, I think.
--
Paul
On Tue, Oct 28, 2014 at 06:47:08PM +0000, Paul Zimmerman wrote:
> > From: Huang Rui [mailto:[email protected]]
> > Sent: Tuesday, October 28, 2014 4:54 AM
> >
> > It enables hibernation if the function is set in coreConsultant.
> >
> > Suggested-by: Felipe Balbi <[email protected]>
> > Signed-off-by: Huang Rui <[email protected]>
> > ---
> > drivers/usb/dwc3/core.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index fa396fc..bf77509 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> > /* enable hibernation here */
> > dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> > + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> > break;
> > default:
> > dev_dbg(dwc->dev, "No power optimization available\n");
>
> What effect does this have when the controller is in device mode? I
> expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
> events when this register bit is set. So the dev_WARN_ONCE in
> dwc3_gadget_interrupt() will start firing, I think.
Ok, so this *has* to wait for proper hibernation support ?
--
balbi
> From: Felipe Balbi [mailto:[email protected]]
> Sent: Tuesday, October 28, 2014 11:51 AM
>
> On Tue, Oct 28, 2014 at 06:47:08PM +0000, Paul Zimmerman wrote:
> > > From: Huang Rui [mailto:[email protected]]
> > > Sent: Tuesday, October 28, 2014 4:54 AM
> > >
> > > It enables hibernation if the function is set in coreConsultant.
> > >
> > > Suggested-by: Felipe Balbi <[email protected]>
> > > Signed-off-by: Huang Rui <[email protected]>
> > > ---
> > > drivers/usb/dwc3/core.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index fa396fc..bf77509 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > > case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> > > /* enable hibernation here */
> > > dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> > > + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> > > break;
> > > default:
> > > dev_dbg(dwc->dev, "No power optimization available\n");
> >
> > What effect does this have when the controller is in device mode? I
> > expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
> > events when this register bit is set. So the dev_WARN_ONCE in
> > dwc3_gadget_interrupt() will start firing, I think.
>
> Ok, so this *has* to wait for proper hibernation support ?
Ah, never mind. Since the hibernation event is not enabled in the
DEVTEN register, the controller shouldn't generate that event after
all. So I think it should be OK. Sorry for the noise.
--
Paul
On Tue, Oct 28, 2014 at 06:55:50PM +0000, Paul Zimmerman wrote:
> > From: Felipe Balbi [mailto:[email protected]]
> > Sent: Tuesday, October 28, 2014 11:51 AM
> >
> > On Tue, Oct 28, 2014 at 06:47:08PM +0000, Paul Zimmerman wrote:
> > > > From: Huang Rui [mailto:[email protected]]
> > > > Sent: Tuesday, October 28, 2014 4:54 AM
> > > >
> > > > It enables hibernation if the function is set in coreConsultant.
> > > >
> > > > Suggested-by: Felipe Balbi <[email protected]>
> > > > Signed-off-by: Huang Rui <[email protected]>
> > > > ---
> > > > drivers/usb/dwc3/core.c | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > index fa396fc..bf77509 100644
> > > > --- a/drivers/usb/dwc3/core.c
> > > > +++ b/drivers/usb/dwc3/core.c
> > > > @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > > > case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> > > > /* enable hibernation here */
> > > > dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> > > > + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> > > > break;
> > > > default:
> > > > dev_dbg(dwc->dev, "No power optimization available\n");
> > >
> > > What effect does this have when the controller is in device mode? I
> > > expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
> > > events when this register bit is set. So the dev_WARN_ONCE in
> > > dwc3_gadget_interrupt() will start firing, I think.
> >
> > Ok, so this *has* to wait for proper hibernation support ?
>
> Ah, never mind. Since the hibernation event is not enabled in the
> DEVTEN register, the controller shouldn't generate that event after
> all. So I think it should be OK. Sorry for the noise.
do you think it's still nice to have a comment here ?
--
balbi
> From: Felipe Balbi [mailto:[email protected]]
> Sent: Tuesday, October 28, 2014 12:01 PM
>
> On Tue, Oct 28, 2014 at 06:55:50PM +0000, Paul Zimmerman wrote:
> > > From: Felipe Balbi [mailto:[email protected]]
> > > Sent: Tuesday, October 28, 2014 11:51 AM
> > >
> > > On Tue, Oct 28, 2014 at 06:47:08PM +0000, Paul Zimmerman wrote:
> > > > > From: Huang Rui [mailto:[email protected]]
> > > > > Sent: Tuesday, October 28, 2014 4:54 AM
> > > > >
> > > > > It enables hibernation if the function is set in coreConsultant.
> > > > >
> > > > > Suggested-by: Felipe Balbi <[email protected]>
> > > > > Signed-off-by: Huang Rui <[email protected]>
> > > > > ---
> > > > > drivers/usb/dwc3/core.c | 1 +
> > > > > 1 file changed, 1 insertion(+)
> > > > >
> > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > index fa396fc..bf77509 100644
> > > > > --- a/drivers/usb/dwc3/core.c
> > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > > > > case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> > > > > /* enable hibernation here */
> > > > > dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> > > > > + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> > > > > break;
> > > > > default:
> > > > > dev_dbg(dwc->dev, "No power optimization available\n");
> > > >
> > > > What effect does this have when the controller is in device mode? I
> > > > expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
> > > > events when this register bit is set. So the dev_WARN_ONCE in
> > > > dwc3_gadget_interrupt() will start firing, I think.
> > >
> > > Ok, so this *has* to wait for proper hibernation support ?
> >
> > Ah, never mind. Since the hibernation event is not enabled in the
> > DEVTEN register, the controller shouldn't generate that event after
> > all. So I think it should be OK. Sorry for the noise.
>
> do you think it's still nice to have a comment here ?
Maybe something along the lines of "enabling this bit so that host-mode
hibernation will work, device-mode hibernation is not implemented yet"?
--
Paul
On Tue, Oct 28, 2014 at 07:15:29PM +0000, Paul Zimmerman wrote:
> > From: Felipe Balbi [mailto:[email protected]]
> > Sent: Tuesday, October 28, 2014 12:01 PM
> >
> > On Tue, Oct 28, 2014 at 06:55:50PM +0000, Paul Zimmerman wrote:
> > > > From: Felipe Balbi [mailto:[email protected]]
> > > > Sent: Tuesday, October 28, 2014 11:51 AM
> > > >
> > > > On Tue, Oct 28, 2014 at 06:47:08PM +0000, Paul Zimmerman wrote:
> > > > > > From: Huang Rui [mailto:[email protected]]
> > > > > > Sent: Tuesday, October 28, 2014 4:54 AM
> > > > > >
> > > > > > It enables hibernation if the function is set in coreConsultant.
> > > > > >
> > > > > > Suggested-by: Felipe Balbi <[email protected]>
> > > > > > Signed-off-by: Huang Rui <[email protected]>
> > > > > > ---
> > > > > > drivers/usb/dwc3/core.c | 1 +
> > > > > > 1 file changed, 1 insertion(+)
> > > > > >
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index fa396fc..bf77509 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > > > > > case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> > > > > > /* enable hibernation here */
> > > > > > dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> > > > > > + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> > > > > > break;
> > > > > > default:
> > > > > > dev_dbg(dwc->dev, "No power optimization available\n");
> > > > >
> > > > > What effect does this have when the controller is in device mode? I
> > > > > expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
> > > > > events when this register bit is set. So the dev_WARN_ONCE in
> > > > > dwc3_gadget_interrupt() will start firing, I think.
> > > >
> > > > Ok, so this *has* to wait for proper hibernation support ?
> > >
> > > Ah, never mind. Since the hibernation event is not enabled in the
> > > DEVTEN register, the controller shouldn't generate that event after
> > > all. So I think it should be OK. Sorry for the noise.
> >
> > do you think it's still nice to have a comment here ?
>
> Maybe something along the lines of "enabling this bit so that host-mode
> hibernation will work, device-mode hibernation is not implemented yet"?
sounds good to me. Huang, can you update your patch to add this comment
Paul suggested ?
thanks
--
balbi
Hi Bjorn,
On Tue, Oct 28, 2014 at 10:39:26AM -0600, Bjorn Helgaas wrote:
> On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> > This patch adds disscramble quirk, and it only needs to be enabled at fpga
>
> "disscramble" (in subject and above) is not a real word.
>
> I see that DWC3_GCTL_DISSCRAMBLE is already defined in
> drivers/usb/dwc3/core.h even before your patches, so I suppose it's
> something the hardware designers made up.
>
> Maybe it means "descramble" (or "unscramble"). Or maybe it means
> "disable scrambling"? A comment might make this clearer. A better
> name would be even better.
>
Your mention is right. "disscramble" is writed by HW designers in
DesignWare databook. It could confuse reader, I will update subject
and add note (disscramble = disable scramble) at commit log.
Thanks,
Rui
On Tue, Oct 28, 2014 at 02:18:52PM -0500, Felipe Balbi wrote:
> On Tue, Oct 28, 2014 at 07:15:29PM +0000, Paul Zimmerman wrote:
> > > From: Felipe Balbi [mailto:[email protected]]
> > > Sent: Tuesday, October 28, 2014 12:01 PM
> > >
> > > On Tue, Oct 28, 2014 at 06:55:50PM +0000, Paul Zimmerman wrote:
> > > > > From: Felipe Balbi [mailto:[email protected]]
> > > > > Sent: Tuesday, October 28, 2014 11:51 AM
> > > > >
> > > > > On Tue, Oct 28, 2014 at 06:47:08PM +0000, Paul Zimmerman wrote:
> > > > > > > From: Huang Rui [mailto:[email protected]]
> > > > > > > Sent: Tuesday, October 28, 2014 4:54 AM
> > > > > > >
> > > > > > > It enables hibernation if the function is set in coreConsultant.
> > > > > > >
> > > > > > > Suggested-by: Felipe Balbi <[email protected]>
> > > > > > > Signed-off-by: Huang Rui <[email protected]>
> > > > > > > ---
> > > > > > > drivers/usb/dwc3/core.c | 1 +
> > > > > > > 1 file changed, 1 insertion(+)
> > > > > > >
> > > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > > index fa396fc..bf77509 100644
> > > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > > @@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > > > > > > case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
> > > > > > > /* enable hibernation here */
> > > > > > > dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
> > > > > > > + reg |= DWC3_GCTL_GBLHIBERNATIONEN;
> > > > > > > break;
> > > > > > > default:
> > > > > > > dev_dbg(dwc->dev, "No power optimization available\n");
> > > > > >
> > > > > > What effect does this have when the controller is in device mode? I
> > > > > > expect it will start generating DWC3_DEVICE_EVENT_HIBER_REQ interrupt
> > > > > > events when this register bit is set. So the dev_WARN_ONCE in
> > > > > > dwc3_gadget_interrupt() will start firing, I think.
> > > > >
> > > > > Ok, so this *has* to wait for proper hibernation support ?
> > > >
> > > > Ah, never mind. Since the hibernation event is not enabled in the
> > > > DEVTEN register, the controller shouldn't generate that event after
> > > > all. So I think it should be OK. Sorry for the noise.
> > >
> > > do you think it's still nice to have a comment here ?
> >
> > Maybe something along the lines of "enabling this bit so that host-mode
> > hibernation will work, device-mode hibernation is not implemented yet"?
>
> sounds good to me. Huang, can you update your patch to add this comment
> Paul suggested ?
>
OK, will update in V4.
Thanks,
Rui
On Tue, Oct 28, 2014 at 10:30:50AM -0600, Bjorn Helgaas wrote:
> On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> > When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced
>
> "Advanced"
>
> > Configuration of coreConsultant, it supports of xHCI BESL Errata Dated
>
> I can't parse "is supports of" and I don't know enough to suggest an
> alternate wording.
>
> > 10/19/2011 is enabled in host mode. In device mode it adds the capability
> > to send NYET response threshold based on the BESL value received in the LPM
> > token, and the threhold is configurable for each soc platform.
>
> "threshold"
>
Thanks to reminder.
It should be:
When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Advanced
Configuration of coreConsultant, support of xHCI BESL Errata Dated
10/19/2011 is enabled in host mode. In device mode it adds the
capability to send NYET response threshold based on the BESL value
received in the LPM token, and the threshold is configurable for each
SoC platform.
Thanks,
Rui
On Tue, Oct 28, 2014 at 01:43:03PM -0500, Felipe Balbi wrote:
> On Tue, Oct 28, 2014 at 10:27:27AM -0600, Bjorn Helgaas wrote:
> > On Tue, Oct 28, 2014 at 5:54 AM, Huang Rui <[email protected]> wrote:
> > > This patch adds Tx demphasis quirk, and the Tx demphasis value is
> >
> > "demphasis" (above and in subject) should be "de-emphasis" as used in
> > the code and comments below.
>
> +1
>
OK, will update
Hi Felipe, Paul,
On Tue, Oct 28, 2014 at 10:35:37PM +0800, Huang Rui wrote:
> On Tue, Oct 28, 2014 at 08:38:56AM -0500, Felipe Balbi wrote:
<snip>
> >
> > however, as I mentioned before, the core shouldn't have to know that
> > it's running on an AMD platform. We already support several different
> > platforms (OMAP5, AM437x, DRA7xx, Exynos5, Exynos7, Qcom, Merrifield,
> > Baytrail, Braswell, HAPS PCIe, and STiH407) and none of them get their
> > $my_awesome_platform flag in dwc3, why should AMD be any different ?
> >
> > This is the only part of $subject that I cannot accept because it would
> > mean we would be giving AMD a special treatment when there shouldn't be
> > any, for anybody.
> >
>
> That's because I used this flag to enable below quirks on AMD NL FPGA
> board, and FPGA flag only can be detected on core. Can I set
> disable_scramble_quirk, dis_u3_susphy_quirk, and dis_u2_susphy_quirk
> for all the FPGA platforms?
>
> if (dwc->amd_nl_plat && dwc->is_fpga) {
> dwc->disable_scramble_quirk = true;
> dwc->dis_u3_susphy_quirk = true;
> dwc->dis_u2_susphy_quirk = true;
> }
>
I confirmed with HW designer, these three quirks only will be needed
on FPGA board. And these should *not* be used on non-FPGA board, as you
known.
So I would like to use below conditions on dwc3 core. When I set these
quirk flags in pci glue layer, then core can filter them by is_fpga
flag to support both on FPGA and SoC. Is there any concern? If that, I
should remove WARN_ONCE at disable_scramble flag.
if (dwc->disable_scramble_quirk && dwc->is_fpga) {..}
if (dwc->dis_u2_susphy_quirk && dwc->is_fpga) {..}
if (dwc->dis_u3_susphy_quirk && dwc->is_fpga) {..}
Thanks,
Rui
On Wed, Oct 29, 2014 at 05:13:43PM +0800, Huang Rui wrote:
> Hi Felipe, Paul,
>
> On Tue, Oct 28, 2014 at 10:35:37PM +0800, Huang Rui wrote:
> > On Tue, Oct 28, 2014 at 08:38:56AM -0500, Felipe Balbi wrote:
>
> <snip>
>
> > >
> > > however, as I mentioned before, the core shouldn't have to know that
> > > it's running on an AMD platform. We already support several different
> > > platforms (OMAP5, AM437x, DRA7xx, Exynos5, Exynos7, Qcom, Merrifield,
> > > Baytrail, Braswell, HAPS PCIe, and STiH407) and none of them get their
> > > $my_awesome_platform flag in dwc3, why should AMD be any different ?
> > >
> > > This is the only part of $subject that I cannot accept because it would
> > > mean we would be giving AMD a special treatment when there shouldn't be
> > > any, for anybody.
> > >
> >
> > That's because I used this flag to enable below quirks on AMD NL FPGA
> > board, and FPGA flag only can be detected on core. Can I set
> > disable_scramble_quirk, dis_u3_susphy_quirk, and dis_u2_susphy_quirk
> > for all the FPGA platforms?
> >
> > if (dwc->amd_nl_plat && dwc->is_fpga) {
> > dwc->disable_scramble_quirk = true;
> > dwc->dis_u3_susphy_quirk = true;
> > dwc->dis_u2_susphy_quirk = true;
> > }
> >
>
> I confirmed with HW designer, these three quirks only will be needed
> on FPGA board. And these should *not* be used on non-FPGA board, as you
> known.
>
> So I would like to use below conditions on dwc3 core. When I set these
> quirk flags in pci glue layer, then core can filter them by is_fpga
> flag to support both on FPGA and SoC. Is there any concern? If that, I
> should remove WARN_ONCE at disable_scramble flag.
>
> if (dwc->disable_scramble_quirk && dwc->is_fpga) {..}
>
> if (dwc->dis_u2_susphy_quirk && dwc->is_fpga) {..}
>
> if (dwc->dis_u3_susphy_quirk && dwc->is_fpga) {..}
the problem is that somebody might need this on non-FPGA. Currently,
only AMD needs these and only on FPGA, but you never know.
I guess we can add it like this for now and once we have a real AMD
product, we drop FPGA support from AMD.
cheers
--
balbi
On Wed, Oct 29, 2014 at 09:11:46AM -0500, Felipe Balbi wrote:
> On Wed, Oct 29, 2014 at 05:13:43PM +0800, Huang Rui wrote:
> > Hi Felipe, Paul,
> >
> > On Tue, Oct 28, 2014 at 10:35:37PM +0800, Huang Rui wrote:
> > > On Tue, Oct 28, 2014 at 08:38:56AM -0500, Felipe Balbi wrote:
> >
> > <snip>
> >
> > > >
> > > > however, as I mentioned before, the core shouldn't have to know that
> > > > it's running on an AMD platform. We already support several different
> > > > platforms (OMAP5, AM437x, DRA7xx, Exynos5, Exynos7, Qcom, Merrifield,
> > > > Baytrail, Braswell, HAPS PCIe, and STiH407) and none of them get their
> > > > $my_awesome_platform flag in dwc3, why should AMD be any different ?
> > > >
> > > > This is the only part of $subject that I cannot accept because it would
> > > > mean we would be giving AMD a special treatment when there shouldn't be
> > > > any, for anybody.
> > > >
> > >
> > > That's because I used this flag to enable below quirks on AMD NL FPGA
> > > board, and FPGA flag only can be detected on core. Can I set
> > > disable_scramble_quirk, dis_u3_susphy_quirk, and dis_u2_susphy_quirk
> > > for all the FPGA platforms?
> > >
> > > if (dwc->amd_nl_plat && dwc->is_fpga) {
> > > dwc->disable_scramble_quirk = true;
> > > dwc->dis_u3_susphy_quirk = true;
> > > dwc->dis_u2_susphy_quirk = true;
> > > }
> > >
> >
> > I confirmed with HW designer, these three quirks only will be needed
> > on FPGA board. And these should *not* be used on non-FPGA board, as you
> > known.
> >
> > So I would like to use below conditions on dwc3 core. When I set these
> > quirk flags in pci glue layer, then core can filter them by is_fpga
> > flag to support both on FPGA and SoC. Is there any concern? If that, I
> > should remove WARN_ONCE at disable_scramble flag.
> >
> > if (dwc->disable_scramble_quirk && dwc->is_fpga) {..}
> >
> > if (dwc->dis_u2_susphy_quirk && dwc->is_fpga) {..}
> >
> > if (dwc->dis_u3_susphy_quirk && dwc->is_fpga) {..}
>
> the problem is that somebody might need this on non-FPGA. Currently,
> only AMD needs these and only on FPGA, but you never know.
>
> I guess we can add it like this for now and once we have a real AMD
> product, we drop FPGA support from AMD.
>
OK, agree.
Then I comments below WARN_ONCE, OK?
/* FIXME it should be used after AMD NL product taps out */
#if 0
WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
"disable_scramble cannot be used on non-FPGA builds\n");
#endif
Thanks,
Rui
On Wed, Oct 29, 2014 at 10:33:19PM +0800, Huang Rui wrote:
> On Wed, Oct 29, 2014 at 09:11:46AM -0500, Felipe Balbi wrote:
> > On Wed, Oct 29, 2014 at 05:13:43PM +0800, Huang Rui wrote:
> > > Hi Felipe, Paul,
> > >
> > > On Tue, Oct 28, 2014 at 10:35:37PM +0800, Huang Rui wrote:
> > > > On Tue, Oct 28, 2014 at 08:38:56AM -0500, Felipe Balbi wrote:
> > >
> > > <snip>
> > >
> > > > >
> > > > > however, as I mentioned before, the core shouldn't have to know that
> > > > > it's running on an AMD platform. We already support several different
> > > > > platforms (OMAP5, AM437x, DRA7xx, Exynos5, Exynos7, Qcom, Merrifield,
> > > > > Baytrail, Braswell, HAPS PCIe, and STiH407) and none of them get their
> > > > > $my_awesome_platform flag in dwc3, why should AMD be any different ?
> > > > >
> > > > > This is the only part of $subject that I cannot accept because it would
> > > > > mean we would be giving AMD a special treatment when there shouldn't be
> > > > > any, for anybody.
> > > > >
> > > >
> > > > That's because I used this flag to enable below quirks on AMD NL FPGA
> > > > board, and FPGA flag only can be detected on core. Can I set
> > > > disable_scramble_quirk, dis_u3_susphy_quirk, and dis_u2_susphy_quirk
> > > > for all the FPGA platforms?
> > > >
> > > > if (dwc->amd_nl_plat && dwc->is_fpga) {
> > > > dwc->disable_scramble_quirk = true;
> > > > dwc->dis_u3_susphy_quirk = true;
> > > > dwc->dis_u2_susphy_quirk = true;
> > > > }
> > > >
> > >
> > > I confirmed with HW designer, these three quirks only will be needed
> > > on FPGA board. And these should *not* be used on non-FPGA board, as you
> > > known.
> > >
> > > So I would like to use below conditions on dwc3 core. When I set these
> > > quirk flags in pci glue layer, then core can filter them by is_fpga
> > > flag to support both on FPGA and SoC. Is there any concern? If that, I
> > > should remove WARN_ONCE at disable_scramble flag.
> > >
> > > if (dwc->disable_scramble_quirk && dwc->is_fpga) {..}
> > >
> > > if (dwc->dis_u2_susphy_quirk && dwc->is_fpga) {..}
> > >
> > > if (dwc->dis_u3_susphy_quirk && dwc->is_fpga) {..}
> >
> > the problem is that somebody might need this on non-FPGA. Currently,
> > only AMD needs these and only on FPGA, but you never know.
> >
> > I guess we can add it like this for now and once we have a real AMD
> > product, we drop FPGA support from AMD.
> >
>
> OK, agree.
>
> Then I comments below WARN_ONCE, OK?
>
> /* FIXME it should be used after AMD NL product taps out */
> #if 0
> WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
> "disable_scramble cannot be used on non-FPGA builds\n");
> #endif
just remove it, we don't like commented out code.
--
balbi