From: Hou Zhiqiang <[email protected]>
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index f36efa73a470..215d2ee65c83 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -40,6 +40,10 @@ Required properties:
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+ this property.
+
Example:
pcie@3400000 {
--
2.25.1
On Fri, Mar 11, 2022 at 05:49:35PM -0600, Li Yang wrote:
> From: Hou Zhiqiang <[email protected]>
>
> This property is to indicate the endianness when accessing the
> PEX_LUT and PF register block, so if these registers are
> implemented in big-endian, specify this property.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index f36efa73a470..215d2ee65c83 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -40,6 +40,10 @@ Required properties:
> of the data transferred from/to the IP block. This can avoid the software
> cache flush/invalid actions, and improve the performance significantly.
>
> +Optional properties:
> +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
> + this property.
What's the purpose of this? I don't see any code that uses this
property.
I guess this might be related to of_device_is_big_endian()? I do see
some code that uses of_device_is_big_endian(), but nothing that looks
relevant to layerscape in particular.
> Example:
>
> pcie@3400000 {
> --
> 2.25.1
>
> -----Original Message-----
> From: Bjorn Helgaas <[email protected]>
> Sent: Thursday, April 14, 2022 2:28 PM
> To: Leo Li <[email protected]>
> Cc: Bjorn Helgaas <[email protected]>; Z.Q. Hou
> <[email protected]>; Rob Herring <[email protected]>; linux-
> [email protected]; [email protected]; linux-
> [email protected]
> Subject: Re: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional
> property big-endian
>
> On Fri, Mar 11, 2022 at 05:49:35PM -0600, Li Yang wrote:
> > From: Hou Zhiqiang <[email protected]>
> >
> > This property is to indicate the endianness when accessing the PEX_LUT
> > and PF register block, so if these registers are implemented in
> > big-endian, specify this property.
> >
> > Signed-off-by: Hou Zhiqiang <[email protected]>
> > Acked-by: Rob Herring <[email protected]>
> > ---
> > Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index f36efa73a470..215d2ee65c83 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -40,6 +40,10 @@ Required properties:
> > of the data transferred from/to the IP block. This can avoid the software
> > cache flush/invalid actions, and improve the performance significantly.
> >
> > +Optional properties:
> > +- big-endian: If the PEX_LUT and PF register block is in big-endian,
> > +specify
> > + this property.
>
> What's the purpose of this? I don't see any code that uses this property.
>
> I guess this might be related to of_device_is_big_endian()? I do see some
> code that uses of_device_is_big_endian(), but nothing that looks relevant to
> layerscape in particular.
These two register blocks are not used in basic operation but are needed for the power management support. There is patch in review from Zhiqiang ("PCI: layerscape: Add power management support") that need to use these registers.
But since this is an intrinsic property of the hardware, I think we should include it in the binding and dtses before the code using it hit the mainline.
>
> > Example:
> >
> > pcie@3400000 {
> > --
> > 2.25.1
> >