This patch is in the continuation to the discussions which happened on
'commit f89504300e94 ("spi: Stacked/parallel memories bindings")' for
adding dt-binding support for stacked/parallel memories.
This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI
driver to add stacked and parallel memories support.
The first nine patches
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
of the previous series got applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
But the rest of the patches in the series did not get applied as failure
was reported for spi driver with GPIO CS, so send the remaining patches
in the series after rebasing it on top of for-next branch and fixing the
issue.
CS GPIO is not tested due to unavailability of necessary hardware setup.
---
BRANCH: for-next
Changes in v10:
- Rebased patch series on top of latest for-next branch and fixed
merge conflicts.
Changes in v9:
- Updated 1/8 patch description to add an high-level overview of
parallel(multi-cs) & stacked design.
- Initialized all unused CS to 0xFF.
- Moved CS check from spi_add_device() to __spi_add_device().
- Updated __spi_add_device() to check to make sure that multiple logical CS
don't map to the same physical CS and same physical CS doesn't map to
different logical CS.
- Updated 1/8, 5/8 & 7/8 to support arbitrary number of flash devices
connected in parallel or stacked mode.
- Updated documentation for chip_select.
- Added a new spi-nor structure member nor->num_flash to keep track of the
number of flashes connected.
- Added a new patch in the series 4/8 to move write_enable call just before
spi_mem ops call in SPI-NOR.
- Added comments in SPI core & SPI-NOR.
- Rebased the patch series on top of the latest for-next branch.
Changes in v8:
- Updated __spi_add_device() and spi_set_cs() to fix spi driver failure
with GPIO CS.
- Rebased the patch series on top of latest for-next branch and fixed
merge conflicts.
- Updated cover letter description to add information regarding GPIO CS
testing and request Stefan to provide his Tested-by tag for 1/7 patch.
- Updated 1/7 patch description.
Changes in v7:
- Updated spi_dev_check() to avoid failures for spi driver GPIO CS and
moved the error message from __spi_add_device() to spi_dev_check().
- Resolved code indentation issue in spi_set_cs().
- In spi_set_cs() call spi_delay_exec( ) once if the controller supports
multi cs with both the CS backed by GPIO.
- Updated __spi_validate()to add checks for both the GPIO CS.
- Replaced cs_index_mask bit mask with SPI_CS_CNT_MAX.
- Updated struct spi_controller to represent multi CS capability of the
spi controller through a flag bit SPI_CONTROLLER_MULTI_CS instead of
a boolen structure member "multi_cs_cap".
- Updated 1/7 patch description .
Changes in v6:
- Rebased on top of latest v6.3-rc1 and fixed merge conflicts in
spi-mpc512x-psc.c, sfdp.c, spansion.c files and removed spi-omap-100k.c.
- Updated spi_dev_check( ) to reject new devices if any one of the
chipselect is used by another device.
Changes in v5:
- Rebased the patches on top of v6.3-rc1 and fixed the merge conflicts.
- Fixed compilation warnings in spi-sh-msiof.c with shmobile_defconfig
Changes in v4:
- Fixed build error in spi-pl022.c file - reported by Mark.
- Fixed build error in spi-sn-f-ospi.c file.
- Added Reviewed-by: Serge Semin <[email protected]> tag.
- Added two more patches to replace spi->chip_select with API calls in
mpc832x_rdb.c & cs35l41_hda_spi.c files.
Changes in v3:
- Rebased the patches on top of
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
- Added a patch to convert spi_nor_otp_region_len(nor) &
spi_nor_otp_n_regions(nor) macros into inline functions
- Added Reviewed-by & Acked-by tags
Changes in v2:
- Rebased the patches on top of v6.2-rc1
- Created separate patch to add get & set APIs for spi->chip_select &
spi->cs_gpiod, and replaced all spi->chip_select and spi->cs_gpiod
references with the API calls.
- Created separate patch to add get & set APIs for nor->params.
---
Amit Kumar Mahapatra (8):
spi: Add multi-cs memories support in SPI core
mtd: spi-nor: Convert macros with inline functions
mtd: spi-nor: Add APIs to set/get nor->params
mtd: spi-nor: Move write enable inside specific write & erase APIs
mtd: spi-nor: Add stacked memories support in spi-nor
spi: spi-zynqmp-gqspi: Add stacked memories support in GQSPI driver
mtd: spi-nor: Add parallel memories support in spi-nor
spi: spi-zynqmp-gqspi: Add parallel memories support in GQSPI driver
drivers/mtd/spi-nor/atmel.c | 17 +-
drivers/mtd/spi-nor/core.c | 683 +++++++++++++++++++++++++------
drivers/mtd/spi-nor/core.h | 8 +
drivers/mtd/spi-nor/debugfs.c | 4 +-
drivers/mtd/spi-nor/gigadevice.c | 4 +-
drivers/mtd/spi-nor/issi.c | 11 +-
drivers/mtd/spi-nor/macronix.c | 10 +-
drivers/mtd/spi-nor/micron-st.c | 35 +-
drivers/mtd/spi-nor/otp.c | 48 ++-
drivers/mtd/spi-nor/sfdp.c | 33 +-
drivers/mtd/spi-nor/spansion.c | 57 +--
drivers/mtd/spi-nor/sst.c | 7 +-
drivers/mtd/spi-nor/swp.c | 25 +-
drivers/mtd/spi-nor/winbond.c | 2 +-
drivers/mtd/spi-nor/xilinx.c | 18 +-
drivers/spi/spi-zynqmp-gqspi.c | 58 ++-
drivers/spi/spi.c | 192 +++++++--
include/linux/mtd/spi-nor.h | 21 +-
include/linux/spi/spi.h | 51 ++-
19 files changed, 1016 insertions(+), 268 deletions(-)
--
2.17.1
In most of the register write operations the spi_nor_write_enable is called
from within that API from where spi_mem APIs are called. Follwoing the same
trend move the write enable API from spi_nor_write & spi_nor_erase APIs to
the respective write & erase APIs.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/core.c | 40 ++++++++++++++------------------------
1 file changed, 15 insertions(+), 25 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 72c80d8b5858..93ae69b7ff83 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -301,6 +301,12 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
const u8 *buf)
{
+ int ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
if (nor->spimem)
return spi_nor_spimem_write_data(nor, to, len, buf);
@@ -1074,6 +1080,10 @@ static int spi_nor_erase_chip(struct spi_nor *nor)
dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
if (nor->spimem) {
struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP;
@@ -1481,10 +1491,14 @@ static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
*/
int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
{
- int i;
+ int i, ret;
addr = spi_nor_convert_addr(nor, addr);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
@@ -1777,12 +1791,6 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
if (ret)
goto destroy_erase_cmd_list;
- ret = spi_nor_write_enable(nor);
- if (ret) {
- spi_nor_unlock_device(nor);
- goto destroy_erase_cmd_list;
- }
-
ret = spi_nor_erase_sector(nor, addr);
spi_nor_unlock_device(nor);
if (ret)
@@ -1841,12 +1849,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (ret)
goto erase_err;
- ret = spi_nor_write_enable(nor);
- if (ret) {
- spi_nor_unlock_device(nor);
- goto erase_err;
- }
-
ret = spi_nor_erase_chip(nor);
spi_nor_unlock_device(nor);
if (ret)
@@ -1877,12 +1879,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (ret)
goto erase_err;
- ret = spi_nor_write_enable(nor);
- if (ret) {
- spi_nor_unlock_device(nor);
- goto erase_err;
- }
-
ret = spi_nor_erase_sector(nor, addr);
spi_nor_unlock_device(nor);
if (ret)
@@ -2177,12 +2173,6 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
if (ret)
goto write_err;
- ret = spi_nor_write_enable(nor);
- if (ret) {
- spi_nor_unlock_device(nor);
- goto write_err;
- }
-
ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
spi_nor_unlock_device(nor);
if (ret < 0)
--
2.17.1
Supporting multi-cs in spi-nor would require the *params member of
struct spi_nor to be an array. To make the transition smoother introduced
spi_nor_get_params() & spi_nor_set_params() APIs to get & set nor->params,
added a new local variable (struct spi_nor_flash_parameter *params) to hold
the return value of the spi_nor_get_params() function call and replaced all
nor->params references with the "params".
While adding multi-cs support in further patches the *params member of the
spi_nor structure would be converted to arrays & the "idx" parameter of
the APIs would be used as array index i.e., nor->params[idx].
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/atmel.c | 17 ++--
drivers/mtd/spi-nor/core.c | 136 ++++++++++++++++++++-----------
drivers/mtd/spi-nor/debugfs.c | 4 +-
drivers/mtd/spi-nor/gigadevice.c | 4 +-
drivers/mtd/spi-nor/issi.c | 11 ++-
drivers/mtd/spi-nor/macronix.c | 10 ++-
drivers/mtd/spi-nor/micron-st.c | 30 ++++---
drivers/mtd/spi-nor/otp.c | 29 +++++--
drivers/mtd/spi-nor/sfdp.c | 33 ++++----
drivers/mtd/spi-nor/spansion.c | 57 +++++++------
drivers/mtd/spi-nor/sst.c | 7 +-
drivers/mtd/spi-nor/swp.c | 25 ++++--
drivers/mtd/spi-nor/winbond.c | 2 +-
drivers/mtd/spi-nor/xilinx.c | 18 ++--
include/linux/mtd/spi-nor.h | 10 +++
15 files changed, 257 insertions(+), 136 deletions(-)
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index e13b8d2dd50a..b63cbe18162c 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -23,10 +23,11 @@ static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
/* We only support unlocking the whole flash array */
- if (ofs || len != nor->params->size)
+ if (ofs || len != params->size)
return -EINVAL;
/* Write 0x00 to the status register to disable write protection */
@@ -50,7 +51,9 @@ static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
static int at25fs_nor_late_init(struct spi_nor *nor)
{
- nor->params->locking_ops = &at25fs_nor_locking_ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->locking_ops = &at25fs_nor_locking_ops;
return 0;
}
@@ -71,11 +74,12 @@ static const struct spi_nor_fixups at25fs_nor_fixups = {
static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
uint64_t len, bool is_protect)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
u8 sr;
/* We only support locking the whole flash array */
- if (ofs || len != nor->params->size)
+ if (ofs || len != params->size)
return -EINVAL;
ret = spi_nor_read_sr(nor, nor->bouncebuf);
@@ -133,9 +137,10 @@ static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs,
static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
uint64_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
- if (ofs >= nor->params->size || (ofs + len) > nor->params->size)
+ if (ofs >= params->size || (ofs + len) > params->size)
return -EINVAL;
ret = spi_nor_read_sr(nor, nor->bouncebuf);
@@ -153,7 +158,9 @@ static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
static int atmel_nor_global_protection_late_init(struct spi_nor *nor)
{
- nor->params->locking_ops = &atmel_nor_global_protection_ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->locking_ops = &atmel_nor_global_protection_ops;
return 0;
}
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 1c443fe568cf..72c80d8b5858 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -448,14 +448,15 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
*/
int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
if (nor->spimem) {
struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
- op.addr.nbytes = nor->params->rdsr_addr_nbytes;
- op.dummy.nbytes = nor->params->rdsr_dummy;
+ op.addr.nbytes = params->rdsr_addr_nbytes;
+ op.dummy.nbytes = params->rdsr_dummy;
/*
* We don't want to read only one byte in DTR mode. So,
* read 2 and then discard the second byte.
@@ -688,14 +689,15 @@ static void spi_nor_unlock_rdst(struct spi_nor *nor)
static int spi_nor_ready(struct spi_nor *nor)
{
int ret;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
ret = spi_nor_lock_rdst(nor);
if (ret)
return 0;
/* Flashes might override the standard routine. */
- if (nor->params->ready)
- ret = nor->params->ready(nor);
+ if (params->ready)
+ ret = params->ready(nor);
else
ret = spi_nor_sr_ready(nor);
@@ -861,6 +863,7 @@ static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
*/
static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
u8 *sr_cr = nor->bouncebuf;
u8 cr_written;
@@ -872,7 +875,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
return ret;
} else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
spi_nor_get_protocol_width(nor->write_proto) == 4 &&
- nor->params->quad_enable) {
+ params->quad_enable) {
/*
* If the Status Register 2 Read command (35h) is not
* supported, we should at least be sure we don't
@@ -1150,17 +1153,21 @@ static u8 spi_nor_convert_3to4_erase(u8 opcode)
static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
{
- return !!nor->params->erase_map.uniform_erase_type;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ return !!params->erase_map.uniform_erase_type;
}
static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
if (!spi_nor_has_uniform_erase(nor)) {
- struct spi_nor_erase_map *map = &nor->params->erase_map;
+ struct spi_nor_erase_map *map = ¶ms->erase_map;
struct spi_nor_erase_type *erase;
int i;
@@ -1302,6 +1309,7 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor)
/* Internal locking helpers for program and erase operations */
static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_rww *rww = &nor->rww;
unsigned int used_banks = 0;
bool started = false;
@@ -1313,7 +1321,7 @@ static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)
if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
goto busy;
- spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
+ spi_nor_offset_to_banks(params->bank_size, start, len, &first, &last);
for (bank = first; bank <= last; bank++) {
if (rww->used_banks & BIT(bank))
goto busy;
@@ -1332,13 +1340,14 @@ static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)
static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_rww *rww = &nor->rww;
u8 first, last;
int bank;
mutex_lock(&nor->lock);
- spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
+ spi_nor_offset_to_banks(params->bank_size, start, len, &first, &last);
for (bank = first; bank <= last; bank++)
rww->used_banks &= ~BIT(bank);
@@ -1379,6 +1388,7 @@ static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size
/* Internal locking helpers for read operations */
static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_rww *rww = &nor->rww;
unsigned int used_banks = 0;
bool started = false;
@@ -1390,7 +1400,7 @@ static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)
if (rww->ongoing_io || rww->ongoing_rd)
goto busy;
- spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
+ spi_nor_offset_to_banks(params->bank_size, start, len, &first, &last);
for (bank = first; bank <= last; bank++) {
if (rww->used_banks & BIT(bank))
goto busy;
@@ -1410,13 +1420,14 @@ static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)
static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_rww *rww = &nor->rww;
u8 first, last;
int bank;
mutex_lock(&nor->lock);
- spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
+ spi_nor_offset_to_banks(params->bank_size, start, len, &first, &last);
for (bank = first; bank <= last; bank++)
nor->rww.used_banks &= ~BIT(bank);
@@ -1457,10 +1468,12 @@ static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size
static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
{
- if (!nor->params->convert_addr)
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ if (!params->convert_addr)
return addr;
- return nor->params->convert_addr(nor, addr);
+ return params->convert_addr(nor, addr);
}
/*
@@ -1680,7 +1693,8 @@ static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
struct list_head *erase_list,
u64 addr, u32 len)
{
- const struct spi_nor_erase_map *map = &nor->params->erase_map;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_erase_map *map = ¶ms->erase_map;
const struct spi_nor_erase_type *erase, *prev_erase = NULL;
struct spi_nor_erase_region *region;
struct spi_nor_erase_command *cmd = NULL;
@@ -2124,9 +2138,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ struct spi_nor_flash_parameter *params;
size_t page_offset, page_remain, i;
ssize_t ret;
- u32 page_size = nor->params->page_size;
+ u32 page_size;
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
@@ -2134,6 +2149,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
if (ret)
return ret;
+ params = spi_nor_get_params(nor, 0);
+ page_size = params->page_size;
+
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
@@ -2289,6 +2307,8 @@ int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
static int spi_nor_spimem_check_op(struct spi_nor *nor,
struct spi_mem_op *op)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
/*
* First test with 4 address bytes. The opcode itself might
* be a 3B addressing opcode but we don't care, because
@@ -2297,7 +2317,7 @@ static int spi_nor_spimem_check_op(struct spi_nor *nor,
*/
op->addr.nbytes = 4;
if (!spi_mem_supports_op(nor->spimem, op)) {
- if (nor->params->size > SZ_16M)
+ if (params->size > SZ_16M)
return -EOPNOTSUPP;
/* If flash size <= 16MB, 3 address bytes are sufficient */
@@ -2361,7 +2381,7 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor,
static void
spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
unsigned int cap;
/* X-X-X modes are not supported yet, mask them all. */
@@ -2462,6 +2482,7 @@ static int spi_nor_select_read(struct spi_nor *nor,
u32 shared_hwcaps)
{
int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
const struct spi_nor_read_command *read;
if (best_match < 0)
@@ -2471,7 +2492,7 @@ static int spi_nor_select_read(struct spi_nor *nor,
if (cmd < 0)
return -EINVAL;
- read = &nor->params->reads[cmd];
+ read = ¶ms->reads[cmd];
nor->read_opcode = read->opcode;
nor->read_proto = read->proto;
@@ -2492,6 +2513,7 @@ static int spi_nor_select_read(struct spi_nor *nor,
static int spi_nor_select_pp(struct spi_nor *nor,
u32 shared_hwcaps)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
const struct spi_nor_pp_command *pp;
@@ -2502,7 +2524,7 @@ static int spi_nor_select_pp(struct spi_nor *nor,
if (cmd < 0)
return -EINVAL;
- pp = &nor->params->page_programs[cmd];
+ pp = ¶ms->page_programs[cmd];
nor->program_opcode = pp->opcode;
nor->write_proto = pp->proto;
return 0;
@@ -2568,7 +2590,8 @@ spi_nor_select_uniform_erase(struct spi_nor_erase_map *map)
static int spi_nor_select_erase(struct spi_nor *nor)
{
- struct spi_nor_erase_map *map = &nor->params->erase_map;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ struct spi_nor_erase_map *map = ¶ms->erase_map;
const struct spi_nor_erase_type *erase = NULL;
struct mtd_info *mtd = &nor->mtd;
int i;
@@ -2611,7 +2634,7 @@ static int spi_nor_select_erase(struct spi_nor *nor)
static int spi_nor_default_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u32 ignored_mask, shared_mask;
int err;
@@ -2671,8 +2694,10 @@ static int spi_nor_default_setup(struct spi_nor *nor,
static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
{
- if (nor->params->addr_nbytes) {
- nor->addr_nbytes = nor->params->addr_nbytes;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ if (params->addr_nbytes) {
+ nor->addr_nbytes = params->addr_nbytes;
} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
/*
* In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
@@ -2693,7 +2718,7 @@ static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
nor->addr_nbytes = 3;
}
- if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) {
+ if (nor->addr_nbytes == 3 && params->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_nbytes = 4;
}
@@ -2715,10 +2740,11 @@ static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
static int spi_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
- if (nor->params->setup)
- ret = nor->params->setup(nor, hwcaps);
+ if (params->setup)
+ ret = params->setup(nor, hwcaps);
else
ret = spi_nor_default_setup(nor, hwcaps);
if (ret)
@@ -2753,7 +2779,7 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
*/
static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_erase_map *map = ¶ms->erase_map;
const struct flash_info *info = nor->info;
const u8 no_sfdp_flags = info->no_sfdp_flags;
@@ -2823,6 +2849,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
*/
static void spi_nor_init_flags(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct device_node *np = spi_nor_get_flash_node(nor);
const u16 flags = nor->info->flags;
@@ -2853,7 +2880,7 @@ static void spi_nor_init_flags(struct spi_nor *nor)
if (flags & NO_CHIP_ERASE)
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
- if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&
+ if (flags & SPI_NOR_RWW && params->n_banks > 1 &&
!nor->controller_ops)
nor->flags |= SNOR_F_RWW;
}
@@ -2887,7 +2914,7 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
*/
static int spi_nor_late_init_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
if (nor->manufacturer && nor->manufacturer->fixups &&
@@ -2914,7 +2941,7 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
* NOR protection support. When locking_ops are not provided, we pick
* the default ones.
*/
- if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
+ if (nor->flags & SNOR_F_HAS_LOCK && !params->locking_ops)
spi_nor_init_default_locking_ops(nor);
if (params->n_banks > 1)
@@ -2933,12 +2960,13 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
*/
static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_flash_parameter sfdp_params;
- memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
+ memcpy(&sfdp_params, params, sizeof(sfdp_params));
if (spi_nor_parse_sfdp(nor)) {
- memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
+ memcpy(params, &sfdp_params, sizeof(*params));
nor->flags &= ~SNOR_F_4B_OPCODES;
}
}
@@ -2973,7 +3001,7 @@ static void spi_nor_init_params_deprecated(struct spi_nor *nor)
*/
static void spi_nor_init_default_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
const struct flash_info *info = nor->info;
struct device_node *np = spi_nor_get_flash_node(nor);
@@ -3060,12 +3088,15 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
*/
static int spi_nor_init_params(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
- nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
- if (!nor->params)
+ params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL);
+ if (!params)
return -ENOMEM;
+ spi_nor_set_params(nor, 0, params);
+
spi_nor_init_default_params(nor);
if (spi_nor_needs_sfdp(nor)) {
@@ -3091,9 +3122,10 @@ static int spi_nor_init_params(struct spi_nor *nor)
*/
static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
- if (!nor->params->set_octal_dtr)
+ if (!params->set_octal_dtr)
return 0;
if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
@@ -3103,7 +3135,7 @@ static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
return 0;
- ret = nor->params->set_octal_dtr(nor, enable);
+ ret = params->set_octal_dtr(nor, enable);
if (ret)
return ret;
@@ -3123,14 +3155,16 @@ static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
*/
static int spi_nor_quad_enable(struct spi_nor *nor)
{
- if (!nor->params->quad_enable)
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ if (!params->quad_enable)
return 0;
if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
spi_nor_get_protocol_width(nor->write_proto) == 4))
return 0;
- return nor->params->quad_enable(nor);
+ return params->quad_enable(nor);
}
/**
@@ -3142,7 +3176,7 @@ static int spi_nor_quad_enable(struct spi_nor *nor)
*/
int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
ret = params->set_4byte_addr_mode(nor, enable);
@@ -3395,6 +3429,7 @@ static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
static void spi_nor_set_mtd_info(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
@@ -3413,9 +3448,9 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
mtd->flags |= MTD_NO_ERASE;
else
mtd->_erase = spi_nor_erase;
- mtd->writesize = nor->params->writesize;
- mtd->writebufsize = nor->params->page_size;
- mtd->size = nor->params->size;
+ mtd->writesize = params->writesize;
+ mtd->writebufsize = params->page_size;
+ mtd->size = params->size;
mtd->_read = spi_nor_read;
/* Might be already set by some SST flashes. */
if (!mtd->_write)
@@ -3469,7 +3504,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
* We need the bounce buffer early to read/write registers when going
* through the spi-mem layer (buffers have to be DMA-able).
* For spi-mem drivers, we'll reallocate a new buffer if
- * nor->params->page_size turns out to be greater than PAGE_SIZE (which
+ * params->page_size turns out to be greater than PAGE_SIZE (which
* shouldn't happen before long since NOR pages are usually less
* than 1KB) after spi_nor_scan() returns.
*/
@@ -3543,13 +3578,14 @@ EXPORT_SYMBOL_GPL(spi_nor_scan);
static int spi_nor_create_read_dirmap(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_dirmap_info info = {
.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
SPI_MEM_OP_DATA_IN(0, NULL, 0)),
.offset = 0,
- .length = nor->params->size,
+ .length = params->size,
};
struct spi_mem_op *op = &info.op_tmpl;
@@ -3574,13 +3610,14 @@ static int spi_nor_create_read_dirmap(struct spi_nor *nor)
static int spi_nor_create_write_dirmap(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_dirmap_info info = {
.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
.offset = 0,
- .length = nor->params->size,
+ .length = params->size,
};
struct spi_mem_op *op = &info.op_tmpl;
@@ -3603,6 +3640,7 @@ static int spi_nor_create_write_dirmap(struct spi_nor *nor)
static int spi_nor_probe(struct spi_mem *spimem)
{
+ struct spi_nor_flash_parameter *params;
struct spi_device *spi = spimem->spi;
struct flash_platform_data *data = dev_get_platdata(&spi->dev);
struct spi_nor *nor;
@@ -3649,13 +3687,15 @@ static int spi_nor_probe(struct spi_mem *spimem)
spi_nor_debugfs_register(nor);
+ params = spi_nor_get_params(nor, 0);
+
/*
* None of the existing parts have > 512B pages, but let's play safe
* and add this logic so that if anyone ever adds support for such
* a NOR we don't end up with buffer overflows.
*/
- if (nor->params->page_size > PAGE_SIZE) {
- nor->bouncebuf_size = nor->params->page_size;
+ if (params->page_size > PAGE_SIZE) {
+ nor->bouncebuf_size = params->page_size;
devm_kfree(nor->dev, nor->bouncebuf);
nor->bouncebuf = devm_kmalloc(nor->dev,
nor->bouncebuf_size,
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 6e163cb5b478..72a901b88ea9 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -76,7 +76,7 @@ static void spi_nor_print_flags(struct seq_file *s, unsigned long flags,
static int spi_nor_params_show(struct seq_file *s, void *data)
{
struct spi_nor *nor = s->private;
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_erase_map *erase_map = ¶ms->erase_map;
struct spi_nor_erase_region *region;
const struct flash_info *info = nor->info;
@@ -184,7 +184,7 @@ static void spi_nor_print_pp_cmd(struct seq_file *s,
static int spi_nor_capabilities_show(struct seq_file *s, void *data)
{
struct spi_nor *nor = s->private;
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u32 hwcaps = params->hwcaps.mask;
int i, cmd;
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index ef1edd0add70..338ce989df22 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -13,6 +13,8 @@ gd25q256_post_bfpt(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
/*
* GD25Q256C supports the first version of JESD216 which does not define
* the Quad Enable methods. Overwrite the default Quad Enable method.
@@ -24,7 +26,7 @@ gd25q256_post_bfpt(struct spi_nor *nor,
*/
if (bfpt_header->major == SFDP_JESD216_MAJOR &&
bfpt_header->minor == SFDP_JESD216_MINOR)
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ params->quad_enable = spi_nor_sr1_bit6_quad_enable;
return 0;
}
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 18d9a00aa22e..ea148a3a5e1f 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -13,6 +13,8 @@ is25lp256_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
/*
* IS25LP256 supports 4B opcodes, but the BFPT advertises
* BFPT_DWORD1_ADDRESS_BYTES_3_ONLY.
@@ -20,7 +22,7 @@ is25lp256_post_bfpt_fixups(struct spi_nor *nor,
*/
if ((bfpt->dwords[SFDP_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
- nor->params->addr_nbytes = 4;
+ params->addr_nbytes = 4;
return 0;
}
@@ -31,7 +33,8 @@ static const struct spi_nor_fixups is25lp256_fixups = {
static int pm25lv_nor_late_init(struct spi_nor *nor)
{
- struct spi_nor_erase_map *map = &nor->params->erase_map;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ struct spi_nor_erase_map *map = ¶ms->erase_map;
int i;
/* The PM25LV series has a different 4k sector erase opcode */
@@ -131,7 +134,9 @@ static const struct flash_info issi_nor_parts[] = {
static void issi_nor_default_init(struct spi_nor *nor)
{
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->quad_enable = spi_nor_sr1_bit6_quad_enable;
}
static const struct spi_nor_fixups issi_fixups = {
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index ea6be95e75a5..be1f273e3ce2 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -187,13 +187,17 @@ static const struct flash_info macronix_nor_parts[] = {
static void macronix_nor_default_init(struct spi_nor *nor)
{
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->quad_enable = spi_nor_sr1_bit6_quad_enable;
}
static int macronix_nor_late_init(struct spi_nor *nor)
{
- if (!nor->params->set_4byte_addr_mode)
- nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ if (!params->set_4byte_addr_mode)
+ params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
return 0;
}
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 8920547c12bf..813a5b1a269b 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -49,10 +49,11 @@
static int micron_st_nor_octal_dtr_en(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
int ret;
- u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
+ u8 addr_mode_nbytes = params->addr_mode_nbytes;
/* Use 20 dummy cycles for memory array reads. */
*buf = 20;
@@ -128,27 +129,31 @@ static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
static void mt35xu512aba_default_init(struct spi_nor *nor)
{
- nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->set_octal_dtr = micron_st_nor_set_octal_dtr;
}
static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
/* Set the Fast Read settings. */
- nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
- spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
0, 20, SPINOR_OP_MT_DTR_RD,
SNOR_PROTO_8_8_8_DTR);
nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
- nor->params->rdsr_dummy = 8;
- nor->params->rdsr_addr_nbytes = 0;
+ params->rdsr_dummy = 8;
+ params->rdsr_addr_nbytes = 0;
/*
* The BFPT quad enable field is set to a reserved value so the quad
* enable function is ignored by spi_nor_parse_bfpt(). Make sure we
* disable it.
*/
- nor->params->quad_enable = NULL;
+ params->quad_enable = NULL;
return 0;
}
@@ -457,14 +462,15 @@ static const struct flash_info st_nor_parts[] = {
*/
static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
if (nor->spimem) {
struct spi_mem_op op = MICRON_ST_RDFSR_OP(fsr);
if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
- op.addr.nbytes = nor->params->rdsr_addr_nbytes;
- op.dummy.nbytes = nor->params->rdsr_dummy;
+ op.addr.nbytes = params->rdsr_addr_nbytes;
+ op.dummy.nbytes = params->rdsr_dummy;
/*
* We don't want to read only one byte in DTR mode. So,
* read 2 and then discard the second byte.
@@ -567,14 +573,16 @@ static int micron_st_nor_ready(struct spi_nor *nor)
static void micron_st_nor_default_init(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
nor->flags |= SNOR_F_HAS_LOCK;
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- nor->params->quad_enable = NULL;
+ params->quad_enable = NULL;
}
static int micron_st_nor_late_init(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
if (nor->info->mfr_flags & USE_FSR)
params->ready = micron_st_nor_ready;
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
index 23fe75ddc9cf..16a9a0375aeb 100644
--- a/drivers/mtd/spi-nor/otp.c
+++ b/drivers/mtd/spi-nor/otp.c
@@ -19,7 +19,9 @@
*/
static inline unsigned int spi_nor_otp_region_len(struct spi_nor *nor)
{
- return nor->params->otp.org->len;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ return params->otp.org->len;
}
/**
@@ -30,7 +32,9 @@ static inline unsigned int spi_nor_otp_region_len(struct spi_nor *nor)
*/
static inline unsigned int spi_nor_otp_n_regions(struct spi_nor *nor)
{
- return nor->params->otp.org->n_regions;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ return params->otp.org->n_regions;
}
/**
@@ -241,7 +245,8 @@ int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region)
static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned int region)
{
- const struct spi_nor_otp_organization *org = nor->params->otp.org;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_otp_organization *org = params->otp.org;
return org->base + region * org->offset;
}
@@ -266,7 +271,8 @@ static int spi_nor_mtd_otp_info(struct mtd_info *mtd, size_t len,
size_t *retlen, struct otp_info *buf)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- const struct spi_nor_otp_ops *ops = nor->params->otp.ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_otp_ops *ops = params->otp.ops;
unsigned int n_regions = spi_nor_otp_n_regions(nor);
unsigned int i;
int ret, locked;
@@ -303,7 +309,8 @@ static int spi_nor_mtd_otp_info(struct mtd_info *mtd, size_t len,
static int spi_nor_mtd_otp_range_is_locked(struct spi_nor *nor, loff_t ofs,
size_t len)
{
- const struct spi_nor_otp_ops *ops = nor->params->otp.ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_otp_ops *ops = params->otp.ops;
unsigned int region;
int locked;
@@ -328,7 +335,8 @@ static int spi_nor_mtd_otp_read_write(struct mtd_info *mtd, loff_t ofs,
const u8 *buf, bool is_write)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- const struct spi_nor_otp_ops *ops = nor->params->otp.ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_otp_ops *ops = params->otp.ops;
const size_t rlen = spi_nor_otp_region_len(nor);
loff_t rstart, rofs;
unsigned int region;
@@ -414,7 +422,8 @@ static int spi_nor_mtd_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
static int spi_nor_mtd_otp_erase(struct mtd_info *mtd, loff_t from, size_t len)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- const struct spi_nor_otp_ops *ops = nor->params->otp.ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_otp_ops *ops = params->otp.ops;
const size_t rlen = spi_nor_otp_region_len(nor);
unsigned int region;
loff_t rstart;
@@ -467,7 +476,8 @@ static int spi_nor_mtd_otp_erase(struct mtd_info *mtd, loff_t from, size_t len)
static int spi_nor_mtd_otp_lock(struct mtd_info *mtd, loff_t from, size_t len)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- const struct spi_nor_otp_ops *ops = nor->params->otp.ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spi_nor_otp_ops *ops = params->otp.ops;
const size_t rlen = spi_nor_otp_region_len(nor);
unsigned int region;
int ret;
@@ -501,9 +511,10 @@ static int spi_nor_mtd_otp_lock(struct mtd_info *mtd, loff_t from, size_t len)
void spi_nor_set_mtd_otp_ops(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct mtd_info *mtd = &nor->mtd;
- if (!nor->params->otp.ops)
+ if (!params->otp.ops)
return;
if (WARN_ON(!is_power_of_2(spi_nor_otp_region_len(nor))))
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index b3b11dfed789..f7137c100569 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -436,7 +436,7 @@ static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
static int spi_nor_parse_bfpt(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_erase_map *map = ¶ms->erase_map;
struct spi_nor_erase_type *erase_type = map->erase_type;
struct sfdp_bfpt bfpt;
@@ -661,6 +661,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
*/
static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
case SMPT_CMD_ADDRESS_LEN_0:
return 0;
@@ -670,7 +672,7 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
return 4;
case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
default:
- return nor->params->addr_mode_nbytes;
+ return params->addr_mode_nbytes;
}
}
@@ -822,7 +824,8 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
static int spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
const u32 *smpt)
{
- struct spi_nor_erase_map *map = &nor->params->erase_map;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ struct spi_nor_erase_map *map = ¶ms->erase_map;
struct spi_nor_erase_type *erase = map->erase_type;
struct spi_nor_erase_region *region;
u64 offset;
@@ -910,6 +913,7 @@ static int spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
static int spi_nor_parse_smpt(struct spi_nor *nor,
const struct sfdp_parameter_header *smpt_header)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
const u32 *sector_map;
u32 *smpt;
size_t len;
@@ -940,7 +944,7 @@ static int spi_nor_parse_smpt(struct spi_nor *nor,
if (ret)
goto out;
- spi_nor_regions_sort_erase_types(&nor->params->erase_map);
+ spi_nor_regions_sort_erase_types(¶ms->erase_map);
/* fall through */
out:
kfree(smpt);
@@ -980,7 +984,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
{ 0u /* not used */, BIT(11) },
{ 0u /* not used */, BIT(12) },
};
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_pp_command *params_pp = params->page_programs;
struct spi_nor_erase_map *map = ¶ms->erase_map;
struct spi_nor_erase_type *erase_type = map->erase_type;
@@ -1143,6 +1147,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
static int spi_nor_parse_profile1(struct spi_nor *nor,
const struct sfdp_parameter_header *profile1_header)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u32 *dwords, addr;
size_t len;
int ret;
@@ -1165,14 +1170,14 @@ static int spi_nor_parse_profile1(struct spi_nor *nor,
/* Set the Read Status Register dummy cycles and dummy address bytes. */
if (dwords[SFDP_DWORD(1)] & PROFILE1_DWORD1_RDSR_DUMMY)
- nor->params->rdsr_dummy = 8;
+ params->rdsr_dummy = 8;
else
- nor->params->rdsr_dummy = 4;
+ params->rdsr_dummy = 4;
if (dwords[SFDP_DWORD(1)] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
- nor->params->rdsr_addr_nbytes = 4;
+ params->rdsr_addr_nbytes = 4;
else
- nor->params->rdsr_addr_nbytes = 0;
+ params->rdsr_addr_nbytes = 0;
/*
* We don't know what speed the controller is running at. Find the
@@ -1201,8 +1206,8 @@ static int spi_nor_parse_profile1(struct spi_nor *nor,
dummy = round_up(dummy, 2);
/* Update the fast read settings. */
- nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
- spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
0, dummy, opcode,
SNOR_PROTO_8_8_8_DTR);
@@ -1210,7 +1215,7 @@ static int spi_nor_parse_profile1(struct spi_nor *nor,
* Page Program is "Required Command" in the xSPI Profile 1.0. Update
* the params->hwcaps.mask here.
*/
- nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
out:
kfree(dwords);
@@ -1231,7 +1236,7 @@ static int spi_nor_parse_profile1(struct spi_nor *nor,
static int spi_nor_parse_sccr(struct spi_nor *nor,
const struct sfdp_parameter_header *sccr_header)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u32 *dwords, addr;
size_t len;
int ret;
@@ -1282,7 +1287,7 @@ static int spi_nor_parse_sccr(struct spi_nor *nor,
static int spi_nor_parse_sccr_mc(struct spi_nor *nor,
const struct sfdp_parameter_header *sccr_mc_header)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u32 *dwords, addr;
u8 i, n_dice;
size_t len;
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 12921344373d..63f46e443b29 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -78,7 +78,8 @@ struct spansion_nor_params {
*/
static void spansion_nor_clear_sr(struct spi_nor *nor)
{
- const struct spansion_nor_params *priv_params = nor->params->priv;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ const struct spansion_nor_params *priv_params = params->priv;
int ret;
if (nor->spimem) {
@@ -98,7 +99,7 @@ static void spansion_nor_clear_sr(struct spi_nor *nor)
static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op =
CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr,
0, nor->bouncebuf);
@@ -140,7 +141,7 @@ static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr)
*/
static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u64 addr;
int ret;
u8 i;
@@ -159,10 +160,11 @@ static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor)
static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
int ret;
- u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
+ u8 addr_mode_nbytes = params->addr_mode_nbytes;
op = (struct spi_mem_op)
CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf);
@@ -189,13 +191,14 @@ static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr)
static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
/* Set the octal and DTR enable bits. */
buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
op = (struct spi_mem_op)
- CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes,
+ CYPRESS_NOR_WR_ANY_REG_OP(params->addr_mode_nbytes,
addr, 1, buf);
return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
@@ -203,7 +206,7 @@ static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr)
static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
{
- const struct spi_nor_flash_parameter *params = nor->params;
+ const struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u8 *buf = nor->bouncebuf;
u64 addr;
int i, ret;
@@ -253,7 +256,7 @@ static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr)
static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
{
- const struct spi_nor_flash_parameter *params = nor->params;
+ const struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u8 *buf = nor->bouncebuf;
u64 addr;
int i, ret;
@@ -280,8 +283,9 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op;
- u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
+ u8 addr_mode_nbytes = params->addr_mode_nbytes;
u8 cfr1v_written;
int ret;
@@ -339,7 +343,7 @@ static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr)
*/
static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u64 addr;
u8 i;
int ret;
@@ -418,6 +422,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
*/
static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op;
u8 addr_mode;
int ret;
@@ -459,8 +464,8 @@ static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor)
return spi_nor_set_4byte_addr_mode(nor, true);
}
- nor->params->addr_nbytes = addr_mode;
- nor->params->addr_mode_nbytes = addr_mode;
+ params->addr_nbytes = addr_mode;
+ params->addr_mode_nbytes = addr_mode;
return 0;
}
@@ -477,10 +482,10 @@ static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor)
*/
static int cypress_nor_get_page_size(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op =
- CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
+ CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes,
0, 0, nor->bouncebuf);
- struct spi_nor_flash_parameter *params = nor->params;
int ret;
u8 i;
@@ -507,12 +512,14 @@ static int cypress_nor_get_page_size(struct spi_nor *nor)
static void cypress_nor_ecc_init(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
/*
* Programming is supported only in 16-byte ECC data unit granularity.
* Byte-programming, bit-walking, or multiple program operations to the
* same ECC data unit without an erase are not allowed.
*/
- nor->params->writesize = 16;
+ params->writesize = 16;
nor->flags |= SNOR_F_ECC;
}
@@ -521,6 +528,7 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_mem_op op;
int ret;
@@ -530,7 +538,7 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor,
/* Read Architecture Configuration Register (ARCFN) */
op = (struct spi_mem_op)
- CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
+ CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes,
SPINOR_REG_CYPRESS_ARCFN, 1,
nor->bouncebuf);
ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
@@ -546,7 +554,7 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor,
static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
/*
* S25FS256T does not define the SCCR map, but we would like to use the
@@ -588,20 +596,21 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_bfpt *bfpt)
{
int ret;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
ret = cypress_nor_set_addr_mode_nbytes(nor);
if (ret)
return ret;
/* Replace Quad Enable with volatile version */
- nor->params->quad_enable = cypress_nor_quad_enable_volatile;
+ params->quad_enable = cypress_nor_quad_enable_volatile;
return 0;
}
static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spi_nor_erase_type *erase_type = params->erase_map.erase_type;
unsigned int i;
@@ -637,7 +646,7 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
static int s25hx_t_late_init(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
/* Fast Read 4B requires mode cycles */
params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
@@ -671,7 +680,7 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
if (!params->n_dice || !params->vreg_offset) {
dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n",
@@ -720,7 +729,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
static int s28hx_t_late_init(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
params->set_octal_dtr = cypress_nor_set_octal_dtr;
params->ready = cypress_nor_sr_ready_and_clear;
@@ -740,13 +749,15 @@ s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
/*
* The S25FS-S chip family reports 512-byte pages in BFPT but
* in reality the write buffer still wraps at the safe default
* of 256 bytes. Overwrite the page size advertised by BFPT
* to get the writes working.
*/
- nor->params->page_size = 256;
+ params->page_size = 256;
return 0;
}
@@ -1045,7 +1056,7 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
static int spansion_nor_late_init(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct spansion_nor_params *priv_params;
u8 mfr_flags = nor->info->mfr_flags;
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index 44d2a546bf17..8d6e50cfef62 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -20,10 +20,11 @@ static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
/* We only support unlocking the entire flash array. */
- if (ofs != 0 || len != nor->params->size)
+ if (ofs != 0 || len != params->size)
return -EINVAL;
ret = spi_nor_read_cr(nor, nor->bouncebuf);
@@ -51,7 +52,9 @@ static const struct spi_nor_locking_ops sst26vf_nor_locking_ops = {
static int sst26vf_nor_late_init(struct spi_nor *nor)
{
- nor->params->locking_ops = &sst26vf_nor_locking_ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->locking_ops = &sst26vf_nor_locking_ops;
return 0;
}
diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
index 585813310ee1..78febd6e1a00 100644
--- a/drivers/mtd/spi-nor/swp.c
+++ b/drivers/mtd/spi-nor/swp.c
@@ -39,7 +39,8 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)
* the flash. For now, we need to have that ugly default.
*/
unsigned int sector_size = nor->info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE;
- u64 n_sectors = div_u64(nor->params->size, sector_size);
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ u64 n_sectors = div_u64(params->size, sector_size);
u8 mask = spi_nor_get_sr_bp_mask(nor);
/* Reserved one for "protect none" and one for "protect all". */
@@ -350,11 +351,14 @@ static const struct spi_nor_locking_ops spi_nor_sr_locking_ops = {
void spi_nor_init_default_locking_ops(struct spi_nor *nor)
{
- nor->params->locking_ops = &spi_nor_sr_locking_ops;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->locking_ops = &spi_nor_sr_locking_ops;
}
static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
+ struct spi_nor_flash_parameter *params;
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
@@ -362,7 +366,8 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params->locking_ops->lock(nor, ofs, len);
+ params = spi_nor_get_params(nor, 0);
+ ret = params->locking_ops->lock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor);
return ret;
@@ -370,6 +375,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
+ struct spi_nor_flash_parameter *params;
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
@@ -377,7 +383,8 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params->locking_ops->unlock(nor, ofs, len);
+ params = spi_nor_get_params(nor, 0);
+ ret = params->locking_ops->unlock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor);
return ret;
@@ -385,6 +392,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
+ struct spi_nor_flash_parameter *params;
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
@@ -392,7 +400,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params->locking_ops->is_locked(nor, ofs, len);
+ params = spi_nor_get_params(nor, 0);
+ ret = params->locking_ops->is_locked(nor, ofs, len);
spi_nor_unlock_and_unprep(nor);
return ret;
@@ -412,6 +421,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
*/
void spi_nor_try_unlock_all(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
int ret;
if (!(nor->flags & SNOR_F_HAS_LOCK))
@@ -419,16 +429,17 @@ void spi_nor_try_unlock_all(struct spi_nor *nor)
dev_dbg(nor->dev, "Unprotecting entire flash array\n");
- ret = spi_nor_unlock(&nor->mtd, 0, nor->params->size);
+ ret = spi_nor_unlock(&nor->mtd, 0, params->size);
if (ret)
dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n");
}
void spi_nor_set_mtd_locking_ops(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct mtd_info *mtd = &nor->mtd;
- if (!nor->params->locking_ops)
+ if (!params->locking_ops)
return;
mtd->_lock = spi_nor_lock;
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 142fb27b2ea9..cdbec66aed91 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -303,7 +303,7 @@ static const struct spi_nor_otp_ops winbond_nor_otp_ops = {
static int winbond_nor_late_init(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = nor->params;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
if (params->otp.org)
params->otp.ops = &winbond_nor_otp_ops;
diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c
index f99118c691b0..046dfba6b166 100644
--- a/drivers/mtd/spi-nor/xilinx.c
+++ b/drivers/mtd/spi-nor/xilinx.c
@@ -50,7 +50,8 @@ static const struct flash_info xilinx_nor_parts[] = {
*/
static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
{
- u32 page_size = nor->params->page_size;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ u32 page_size = params->page_size;
u32 offset, page;
offset = addr % page_size;
@@ -110,6 +111,7 @@ static int xilinx_nor_sr_ready(struct spi_nor *nor)
static int xilinx_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
u32 page_size;
int ret;
@@ -135,14 +137,14 @@ static int xilinx_nor_setup(struct spi_nor *nor,
*/
if (nor->bouncebuf[0] & XSR_PAGESIZE) {
/* Flash in Power of 2 mode */
- page_size = (nor->params->page_size == 264) ? 256 : 512;
- nor->params->page_size = page_size;
+ page_size = (params->page_size == 264) ? 256 : 512;
+ params->page_size = page_size;
nor->mtd.writebufsize = page_size;
- nor->params->size = nor->info->size;
+ params->size = nor->info->size;
nor->mtd.erasesize = 8 * page_size;
} else {
/* Flash in Default addressing mode */
- nor->params->convert_addr = s3an_nor_convert_addr;
+ params->convert_addr = s3an_nor_convert_addr;
nor->mtd.erasesize = nor->info->sector_size;
}
@@ -151,8 +153,10 @@ static int xilinx_nor_setup(struct spi_nor *nor,
static int xilinx_nor_late_init(struct spi_nor *nor)
{
- nor->params->setup = xilinx_nor_setup;
- nor->params->ready = xilinx_nor_sr_ready;
+ struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+
+ params->setup = xilinx_nor_setup;
+ params->ready = xilinx_nor_sr_ready;
return 0;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index cdcfe0fd2e7d..59909e7d6f53 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -433,6 +433,16 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
return mtd_get_of_node(&nor->mtd);
}
+static inline struct spi_nor_flash_parameter *spi_nor_get_params(const struct spi_nor *nor, u8 idx)
+{
+ return nor->params;
+}
+
+static inline void spi_nor_set_params(struct spi_nor *nor, u8 idx,
+ struct spi_nor_flash_parameter *params)
+{
+ nor->params = params;
+}
/**
* spi_nor_scan() - scan the SPI NOR
* @nor: the spi_nor structure
--
2.17.1
In further patches the nor->params references in
spi_nor_otp_region_len(nor) & spi_nor_otp_n_regions(nor) macros will be
replaced with spi_nor_get_params() API. To make the transition smoother,
first converting the macros into static inline functions.
Suggested-by: Michal Simek <[email protected]>
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/otp.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
index 9a729aa3452d..23fe75ddc9cf 100644
--- a/drivers/mtd/spi-nor/otp.c
+++ b/drivers/mtd/spi-nor/otp.c
@@ -11,8 +11,27 @@
#include "core.h"
-#define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
-#define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
+/**
+ * spi_nor_otp_region_len() - get size of one OTP region in bytes
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: size of one OTP region in bytes
+ */
+static inline unsigned int spi_nor_otp_region_len(struct spi_nor *nor)
+{
+ return nor->params->otp.org->len;
+}
+
+/**
+ * spi_nor_otp_n_regions() - get number of individual OTP regions
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: number of individual OTP regions
+ */
+static inline unsigned int spi_nor_otp_n_regions(struct spi_nor *nor)
+{
+ return nor->params->otp.org->n_regions;
+}
/**
* spi_nor_otp_read_secr() - read security register
--
2.17.1
AMD-Xilinx GQSPI controller has two advanced mode that allows the
controller to consider two flashes as one single device.
One of these two mode is the parallel mode in which each byte of data is
stored in both devices, the even bits in the lower flash & the odd bits in
the upper flash. The byte split is automatically handled by the QSPI
controller.
The other mode is the stacked mode in which both the flashes share the
same SPI bus but each of the device contain half of the data. In this mode,
the controller does not follow CS requests but instead internally wires the
two CS levels with the value of the most significant address bit.
For supporting both these modes SPI core need to be updated for providing
multiple CS for a single SPI device.
For adding multi CS support the SPI device need to be aware of all the CS
values. So, the "chip_select" member in the spi_device structure is now an
array that holds all the CS values.
spi_device structure now has a "cs_index_mask" member. This acts as an
index to the chip_select array. If nth bit of spi->cs_index_mask is set
then the driver would assert spi->chip_select[n].
In parallel mode all the chip selects are asserted/de-asserted
simultaneously and each byte of data is stored in both devices, the even
bits in one, the odd bits in the other. The split is automatically handled
by the GQSPI controller. The GQSPI controller supports a maximum of two
flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is
added in the spi controller flags, through ctlr->flags the spi core
will make sure that the controller is capable of handling multiple chip
selects at once.
For supporting multiple CS via GPIO the cs_gpiod member of the spi_device
structure is now an array that holds the gpio descriptor for each
chipselect.
CS GPIO is not tested due to unavailability of necessary hardware setup.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
Hello @Stefen,
We restructured the SPI core implementation, for handling arbitrary number
of devices connected in parallel(multi-cs) or stacked mode. We have tested
this updated patch on native-cs setup but couldn't test cs-gpio due to
unavailability of a proper setup. If possible, could you please retest
the cs-gpio use case with this updated patch and provide your feedback.
---
drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---------
include/linux/spi/spi.h | 51 ++++++++---
2 files changed, 191 insertions(+), 52 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 8ead7acb99f3..ff66147ba95f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev, void *data)
{
struct spi_device *spi = to_spi_device(dev);
struct spi_device *new_spi = data;
-
- if (spi->controller == new_spi->controller &&
- spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
- return -EBUSY;
+ int idx, nw_idx;
+ u8 cs, cs_nw;
+
+ if (spi->controller == new_spi->controller) {
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ cs = spi_get_chipselect(spi, idx);
+ for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
+ cs_nw = spi_get_chipselect(spi, nw_idx);
+ if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
+ dev_err(dev, "chipselect %d already in use\n", cs_nw);
+ return -EBUSY;
+ }
+ }
+ }
+ }
return 0;
}
@@ -629,13 +640,32 @@ static int __spi_add_device(struct spi_device *spi)
{
struct spi_controller *ctlr = spi->controller;
struct device *dev = ctlr->dev.parent;
- int status;
+ int status, idx, nw_idx;
+ u8 cs, nw_cs;
+
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ /* Chipselects are numbered 0..max; validate. */
+ cs = spi_get_chipselect(spi, idx);
+ if (cs != 0xFF && cs >= ctlr->num_chipselect) {
+ dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx),
+ ctlr->num_chipselect);
+ return -EINVAL;
+ }
+ }
- /* Chipselects are numbered 0..max; validate. */
- if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
- dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
- ctlr->num_chipselect);
- return -EINVAL;
+ /*
+ * Make sure that multiple logical CS doesn't map to the same physical CS.
+ * For example, spi->chip_select[0] != spi->chip_select[1] and so on.
+ */
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ cs = spi_get_chipselect(spi, idx);
+ for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
+ nw_cs = spi_get_chipselect(spi, nw_idx);
+ if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
+ dev_err(dev, "chipselect %d already in use\n", nw_cs);
+ return -EBUSY;
+ }
+ }
}
/* Set the bus ID string */
@@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device *spi)
* its configuration.
*/
status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
- if (status) {
- dev_err(dev, "chipselect %d already in use\n",
- spi_get_chipselect(spi, 0));
+ if (status)
return status;
- }
/* Controller may unregister concurrently */
if (IS_ENABLED(CONFIG_SPI_DYNAMIC) &&
@@ -659,8 +686,15 @@ static int __spi_add_device(struct spi_device *spi)
return -ENODEV;
}
- if (ctlr->cs_gpiods)
- spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi, 0)]);
+ if (ctlr->cs_gpiods) {
+ u8 cs;
+
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ cs = spi_get_chipselect(spi, idx);
+ if (cs != 0xFF)
+ spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]);
+ }
+ }
/*
* Drivers may modify this initial i/o setup, but will
@@ -701,6 +735,9 @@ int spi_add_device(struct spi_device *spi)
struct spi_controller *ctlr = spi->controller;
int status;
+ /* Set the bus ID string */
+ spi_dev_set_name(spi);
+
mutex_lock(&ctlr->add_lock);
status = __spi_add_device(spi);
mutex_unlock(&ctlr->add_lock);
@@ -942,32 +979,51 @@ static void spi_res_release(struct spi_controller *ctlr, struct spi_message *mes
}
/*-------------------------------------------------------------------------*/
+static inline bool spi_is_last_cs(struct spi_device *spi)
+{
+ u8 idx;
+ bool last = false;
+
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ if ((spi->cs_index_mask >> idx) & 0x01) {
+ if (spi->controller->last_cs[idx] == spi_get_chipselect(spi, idx))
+ last = true;
+ }
+ }
+ return last;
+}
+
static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
{
bool activate = enable;
+ u8 idx;
/*
* Avoid calling into the driver (or doing delays) if the chip select
* isn't actually changing from the last time this was called.
*/
- if (!force && ((enable && spi->controller->last_cs == spi_get_chipselect(spi, 0)) ||
- (!enable && spi->controller->last_cs != spi_get_chipselect(spi, 0))) &&
+ if (!force && ((enable && spi->controller->last_cs_index_mask == spi->cs_index_mask &&
+ spi_is_last_cs(spi)) ||
+ (!enable && spi->controller->last_cs_index_mask == spi->cs_index_mask &&
+ !spi_is_last_cs(spi))) &&
(spi->controller->last_cs_mode_high == (spi->mode & SPI_CS_HIGH)))
return;
trace_spi_set_cs(spi, activate);
- spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
+ spi->controller->last_cs_index_mask = spi->cs_index_mask;
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi, 0) : -1;
spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
- if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) && !activate)
- spi_delay_exec(&spi->cs_hold, NULL);
-
if (spi->mode & SPI_CS_HIGH)
enable = !enable;
- if (spi_get_csgpiod(spi, 0)) {
+ if (spi_is_csgpiod(spi)) {
+ if (!spi->controller->set_cs_timing && !activate)
+ spi_delay_exec(&spi->cs_hold, NULL);
+
if (!(spi->mode & SPI_NO_CS)) {
/*
* Historically ACPI has no means of the GPIO polarity and
@@ -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
* ambiguity. That's why we use enable, that takes SPI_CS_HIGH
* into account.
*/
- if (has_acpi_companion(&spi->dev))
- gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
- else
- /* Polarity handled by GPIO library */
- gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ if (((spi->cs_index_mask >> idx) & 0x01) &&
+ spi_get_csgpiod(spi, idx)) {
+ if (has_acpi_companion(&spi->dev))
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
+ !enable);
+ else
+ /* Polarity handled by GPIO library */
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
+ activate);
+
+ if (activate)
+ spi_delay_exec(&spi->cs_setup, NULL);
+ else
+ spi_delay_exec(&spi->cs_inactive, NULL);
+ }
+ }
}
/* Some SPI masters need both GPIO CS & slave_select */
if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
spi->controller->set_cs)
spi->controller->set_cs(spi, !enable);
+
+ if (!spi->controller->set_cs_timing) {
+ if (activate)
+ spi_delay_exec(&spi->cs_setup, NULL);
+ else
+ spi_delay_exec(&spi->cs_inactive, NULL);
+ }
} else if (spi->controller->set_cs) {
spi->controller->set_cs(spi, !enable);
}
-
- if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
- if (activate)
- spi_delay_exec(&spi->cs_setup, NULL);
- else
- spi_delay_exec(&spi->cs_inactive, NULL);
- }
}
#ifdef CONFIG_HAS_DMA
@@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct device_node *nc,
static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
struct device_node *nc)
{
- u32 value;
- int rc;
+ u32 value, cs[SPI_CS_CNT_MAX];
+ int rc, idx;
/* Mode (clock phase/polarity/etc.) */
if (of_property_read_bool(nc, "spi-cpha"))
@@ -2295,14 +2363,52 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
return 0;
}
+ if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
+ dev_err(&ctlr->dev, "No. of CS is more than max. no. of supported CS\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Zero(0) is a valid physical CS value and can be located at any
+ * logical CS in the spi->chip_select[]. If all the physical CS
+ * are initialized to 0 then It would be difficult to differentiate
+ * between a valid physical CS 0 & an unused logical CS whose physical
+ * CS can be 0. As a solution to this issue initialize all the CS to 0xFF.
+ * Now all the unused logical CS will have 0xFF physical CS value & can be
+ * ignore while performing physical CS validity checks.
+ */
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(spi, idx, 0xFF);
+
/* Device address */
- rc = of_property_read_u32(nc, "reg", &value);
- if (rc) {
+ rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
+ SPI_CS_CNT_MAX);
+ if (rc < 0) {
dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n",
nc, rc);
return rc;
}
- spi_set_chipselect(spi, 0, value);
+ if (rc > ctlr->num_chipselect) {
+ dev_err(&ctlr->dev, "%pOF has number of CS > ctlr->num_chipselect (%d)\n",
+ nc, rc);
+ return rc;
+ }
+ if ((of_property_read_bool(nc, "parallel-memories")) &&
+ (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
+ dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n");
+ return -EINVAL;
+ }
+ for (idx = 0; idx < rc; idx++)
+ spi_set_chipselect(spi, idx, cs[idx]);
+
+ /* spi->chip_select[i] gives the corresponding physical CS for logical CS i
+ * logical CS number is represented by setting the ith bit in spi->cs_index_mask
+ * So, for example, if spi->cs_index_mask = 0x01 then logical CS number is 0 and
+ * spi->chip_select[0] will give the physical CS.
+ * By default spi->chip_select[0] will hold the physical CS number so, set
+ * spi->cs_index_mask as 0x01.
+ */
+ spi->cs_index_mask = 0x01;
/* Device speed */
if (!of_property_read_u32(nc, "spi-max-frequency", &value))
@@ -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller *ctlr)
struct boardinfo *bi;
int first_dynamic;
int status;
+ int idx;
if (!dev)
return -ENODEV;
@@ -3164,7 +3271,8 @@ int spi_register_controller(struct spi_controller *ctlr)
}
/* Setting last_cs to -1 means no chip selected */
- ctlr->last_cs = -1;
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ ctlr->last_cs[idx] = -1;
status = device_add(&ctlr->dev);
if (status < 0)
@@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
* cs_change is set for each transfer.
*/
if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits & SPI_CS_WORD) ||
- spi_get_csgpiod(spi, 0))) {
+ spi_is_csgpiod(spi))) {
size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
int ret;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 7b4baff63c5c..871d3a6d879b 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -20,6 +20,9 @@
#include <uapi/linux/spi/spi.h>
+/* Max no. of CS supported per spi device */
+#define SPI_CS_CNT_MAX 4
+
struct dma_chan;
struct software_node;
struct ptp_system_timestamp;
@@ -132,7 +135,8 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
* @max_speed_hz: Maximum clock rate to be used with this chip
* (on this board); may be changed by the device's driver.
* The spi_transfer.speed_hz can override this for each transfer.
- * @chip_select: Chipselect, distinguishing chips handled by @controller.
+ * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
+ * the corresponding physical CS for logical CS i.
* @mode: The spi mode defines how data is clocked out and in.
* This may be changed by the device's driver.
* The "active low" default for chipselect mode can be overridden
@@ -157,8 +161,8 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
* the device will bind to the named driver and only the named driver.
* Do not set directly, because core frees it; use driver_set_override() to
* set or clear it.
- * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL when
- * not using a GPIO line)
+ * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines
+ * (optional, NULL when not using a GPIO line)
* @word_delay: delay to be inserted between consecutive
* words of a transfer
* @cs_setup: delay to be introduced by the controller after CS is asserted
@@ -167,6 +171,7 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
* deasserted. If @cs_change_delay is used from @spi_transfer, then the
* two delays will be added up.
* @pcpu_statistics: statistics for the spi_device
+ * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
*
* A @spi_device is used to interchange data between an SPI slave
* (usually a discrete chip) and CPU memory.
@@ -182,7 +187,7 @@ struct spi_device {
struct spi_controller *controller;
struct spi_controller *master; /* Compatibility layer */
u32 max_speed_hz;
- u8 chip_select;
+ u8 chip_select[SPI_CS_CNT_MAX];
u8 bits_per_word;
bool rt;
#define SPI_NO_TX BIT(31) /* No transmit wire */
@@ -213,7 +218,7 @@ struct spi_device {
void *controller_data;
char modalias[SPI_NAME_SIZE];
const char *driver_override;
- struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor */
+ struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */
struct spi_delay word_delay; /* Inter-word delay */
/* CS delays */
struct spi_delay cs_setup;
@@ -223,6 +228,13 @@ struct spi_device {
/* The statistics */
struct spi_statistics __percpu *pcpu_statistics;
+ /* Bit mask of the chipselect(s) that the driver need to use from
+ * the chipselect array.When the controller is capable to handle
+ * multiple chip selects & memories are connected in parallel
+ * then more than one bit need to be set in cs_index_mask.
+ */
+ u32 cs_index_mask : SPI_CS_CNT_MAX;
+
/*
* Likely need more hooks for more protocol options affecting how
* the controller talks to each chip, like:
@@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const struct spi_device *spi)
static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
{
- return spi->chip_select;
+ return spi->chip_select[idx];
}
static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect)
{
- spi->chip_select = chipselect;
+ spi->chip_select[idx] = chipselect;
}
static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx)
{
- return spi->cs_gpiod;
+ return spi->cs_gpiod[idx];
}
static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod)
{
- spi->cs_gpiod = csgpiod;
+ spi->cs_gpiod[idx] = csgpiod;
+}
+
+static inline bool spi_is_csgpiod(struct spi_device *spi)
+{
+ u8 idx;
+
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ if (spi_get_csgpiod(spi, idx))
+ return true;
+ }
+ return false;
}
/**
@@ -399,6 +422,8 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch
* @bus_lock_spinlock: spinlock for SPI bus locking
* @bus_lock_mutex: mutex for exclusion of multiple callers
* @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
+ * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
+ * more than one chip select at once.
* @setup: updates the device mode and clocking records used by a
* device's SPI controller; protocol code may call this. This
* must fail if an unrecognized or unsupported mode is requested.
@@ -567,6 +592,11 @@ struct spi_controller {
#define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
#define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */
#define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */
+ /*
+ * The spi-controller has multi chip select capability and can
+ * assert/de-assert more than one chip select at once.
+ */
+#define SPI_CONTROLLER_MULTI_CS BIT(7)
/* Flag indicating if the allocation of this struct is devres-managed */
bool devm_allocated;
@@ -677,7 +707,8 @@ struct spi_controller {
bool rt;
bool auto_runtime_pm;
bool cur_msg_mapped;
- char last_cs;
+ char last_cs[SPI_CS_CNT_MAX];
+ char last_cs_index_mask;
bool last_cs_mode_high;
bool fallback;
struct completion xfer_completion;
--
2.17.1
GQSPI supports two chip select CS0 & CS1. Update the driver to
assert/de-assert the appropriate chip select as per the bits set in
qspi->cs_index_mask.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/spi/spi-zynqmp-gqspi.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 9a46b2478f4e..c5d12ddd4ab3 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -154,6 +154,9 @@
#define GQSPI_FREQ_100MHZ 100000000
#define GQSPI_FREQ_150MHZ 150000000
+#define GQSPI_SELECT_LOWER_CS BIT(0)
+#define GQSPI_SELECT_UPPER_CS BIT(1)
+
#define SPI_AUTOSUSPEND_TIMEOUT 3000
enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
@@ -465,15 +468,17 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
+ if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_UPPER,
+ GQSPI_SELECT_FLASH_BUS_LOWER);
+ } else if (qspi->cs_index_mask & GQSPI_SELECT_LOWER_CS) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_LOWER,
+ GQSPI_SELECT_FLASH_BUS_LOWER);
+ }
+ genfifoentry |= xqspi->genfifobus;
if (!is_high) {
- if (!spi_get_chipselect(qspi, 0)) {
- xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
- xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
- } else {
- xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
- xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
- }
- genfifoentry |= xqspi->genfifobus;
genfifoentry |= xqspi->genfifocs;
genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
} else {
--
2.17.1
The current implementation assumes that a maximum of two flashes are
connected in parallel mode. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->spimem->spi->cs_index_mask. The QSPI driver will then assert/de-assert
CS0 & CS1.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where
addr is the address specified by the user.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/core.c | 409 +++++++++++++++++++++++++-------
drivers/mtd/spi-nor/core.h | 4 +
drivers/mtd/spi-nor/micron-st.c | 5 +
3 files changed, 333 insertions(+), 85 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index e990be7c7eb6..2e6cc45341ed 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -470,17 +470,29 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
op.data.nbytes = 2;
}
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ op.data.nbytes = 2;
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
- 1);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ ret = spi_nor_controller_ops_read_reg(nor,
+ SPINOR_OP_RDSR,
+ sr, 2);
+ else
+ ret = spi_nor_controller_ops_read_reg(nor,
+ SPINOR_OP_RDSR,
+ sr, 1);
}
if (ret)
dev_dbg(nor->dev, "error %d reading SR\n", ret);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ sr[0] |= sr[1];
+
return ret;
}
@@ -1824,6 +1836,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
struct spi_nor_flash_parameter *params;
u32 addr, len, offset, cur_cs_num = 0;
uint32_t rem;
+ u32 n_flash = 1;
int ret;
u64 sz;
@@ -1833,6 +1846,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
params = spi_nor_get_params(nor, 0);
sz = params->size;
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
if (spi_nor_has_uniform_erase(nor)) {
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
@@ -1854,53 +1870,82 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (ret)
goto erase_err;
- while (cur_cs_num < nor->num_flash) {
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
ret = spi_nor_erase_chip(nor);
spi_nor_unlock_device(nor);
if (ret)
goto erase_err;
/*
- * Scale the timeout linearly with the size of the flash, with
- * a minimum calibrated to an old 2MB flash. We could try to
- * pull these from CFI/SFDP, but these values should be good
- * enough for now.
- */
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
- CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
- (unsigned long)(params->size / SZ_2M));
+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+ (unsigned long)(mtd->size / SZ_2M));
ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
if (ret)
goto erase_err;
- cur_cs_num++;
- }
+ } else {
+ while (cur_cs_num < n_flash) {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ ret = spi_nor_erase_chip(nor);
+ spi_nor_unlock_device(nor);
+ if (ret)
+ goto erase_err;
+
+ /*
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+ (unsigned long)(params->size / SZ_2M));
+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
+ if (ret)
+ goto erase_err;
+
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ }
+ }
/* REVISIT in some cases we could speed up erasing large regions
* by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
* to use "small sector erase", but that's not always optimal.
*/
-
/* "sector"-at-a-time erase */
} else if (spi_nor_has_uniform_erase(nor)) {
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < nor->num_flash) && (addr > sz - 1)) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL)) {
+ while ((cur_cs_num < n_flash) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
-
while (len) {
ret = spi_nor_lock_device(nor);
if (ret)
goto erase_err;
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
offset = addr;
if (nor->flags & SNOR_F_HAS_STACKED) {
params = spi_nor_get_params(nor, cur_cs_num);
offset -= (sz - params->size);
}
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ u64 aux = offset;
+
+ ret = do_div(aux, n_flash);
+ offset = aux;
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ }
ret = spi_nor_erase_sector(nor, offset);
spi_nor_unlock_device(nor);
@@ -1923,34 +1968,42 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
sz += params->size;
}
}
-
/* erase multiple sectors */
} else {
- u64 erase_len = 0;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ u64 aux = offset;
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < nor->num_flash) && (addr > sz - 1)) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
- }
- /* perform multi sector erase onec per Flash*/
- while (len) {
- erase_len = (len > (sz - addr)) ? (sz - addr) : len;
- offset = addr;
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- if (nor->flags & SNOR_F_HAS_STACKED) {
- params = spi_nor_get_params(nor, cur_cs_num);
- offset -= (sz - params->size);
- }
- ret = spi_nor_erase_multi_sectors(nor, offset, erase_len);
+ ret = do_div(aux, n_flash);
+ offset = aux;
+ ret = spi_nor_erase_multi_sectors(nor, addr, len);
if (ret)
goto erase_err;
- len -= erase_len;
- addr += erase_len;
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
+ } else {
+ u64 erase_len = 0;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < n_flash) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ /* perform multi sector erase onec per Flash*/
+ while (len) {
+ erase_len = (len > (sz - addr)) ? (sz - addr) : len;
+ offset = addr;
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+ ret = spi_nor_erase_multi_sectors(nor, offset, erase_len);
+ if (ret)
+ goto erase_err;
+ len -= erase_len;
+ addr += erase_len;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
}
@@ -2144,9 +2197,12 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
struct spi_nor *nor = mtd_to_spi_nor(mtd);
struct spi_nor_flash_parameter *params;
ssize_t ret, read_len, len_lock = len;
+ bool is_ofst_odd = false;
loff_t from_lock = from;
u32 cur_cs_num = 0;
- u64 sz;
+ u_char *readbuf;
+ u32 n_flash = 1;
+ u64 sz = 0;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
@@ -2157,23 +2213,54 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
params = spi_nor_get_params(nor, 0);
sz = params->size;
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < nor->num_flash) && (from > sz - 1)) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
+ /*
+ * When even number of flashes are connected in parallel and the
+ * requested read length is odd then read (len + 1) from offset + 1
+ * and ignore offset[0] data.
+ */
+ if ((nor->flags & SNOR_F_HAS_PARALLEL) && (!(n_flash % 2)) && (from & 0x01)) {
+ from = (loff_t)(from - 1);
+ len = (size_t)(len + 1);
+ is_ofst_odd = true;
+ readbuf = kmalloc(len, GFP_KERNEL);
+ if (!readbuf)
+ return -ENOMEM;
+ } else {
+ readbuf = buf;
}
+
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL)) {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < n_flash) && (from > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ }
+
while (len) {
loff_t addr = from;
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- read_len = (len > (sz - addr)) ? (sz - addr) : len;
- params = spi_nor_get_params(nor, cur_cs_num);
- addr -= (sz - params->size);
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ u64 aux = addr;
+
+ ret = do_div(aux, n_flash);
+ addr = aux;
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ read_len = len;
+ } else {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ read_len = (len > (sz - addr)) ? (sz - addr) : len;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+ }
addr = spi_nor_convert_addr(nor, addr);
- ret = spi_nor_read_data(nor, addr, len, buf);
+ ret = spi_nor_read_data(nor, addr, read_len, readbuf);
if (ret == 0) {
/* We shouldn't see 0-length reads */
ret = -EIO;
@@ -2183,8 +2270,20 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
goto read_err;
WARN_ON(ret > read_len);
- *retlen += ret;
+ if (is_ofst_odd) {
+ /*
+ * Cannot read from odd offset in parallel mode.
+ * So read len + 1 from offset + 1 from the flash
+ * and copy len data from readbuf[1].
+ */
+ memcpy(buf, (readbuf + 1), (len - 1));
+ *retlen += (ret - 1);
+ } else {
+ *retlen += ret;
+ }
buf += ret;
+ if (!is_ofst_odd)
+ readbuf += ret;
from += ret;
len -= ret;
@@ -2202,8 +2301,10 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
ret = 0;
read_err:
- spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock);
+ if (is_ofst_odd)
+ kfree(readbuf);
+ spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock);
return ret;
}
@@ -2219,6 +2320,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
struct spi_nor_flash_parameter *params;
size_t page_offset, page_remain, i;
u32 page_size, cur_cs_num = 0;
+ u32 n_flash = 1;
ssize_t ret;
u64 sz;
@@ -2232,11 +2334,41 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
page_size = params->page_size;
sz = params->size;
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < nor->num_flash) && (to > sz - 1)) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ /*
+ * When even number of flashes are connected in parallel and the
+ * requested write length is odd then first write 2 bytes.
+ */
+ if ((!(n_flash % 2)) && (to & 0x01)) {
+ u8 two[2] = {0xff, buf[0]};
+ size_t written_len;
+
+ ret = spi_nor_write(mtd, to & ~1, 2, &written_len, two);
+ if (ret < 0)
+ return ret;
+ *retlen += 1; /* We've written only one actual byte */
+ ++buf;
+ --len;
+ ++to;
+ }
+ /*
+ * Write operation are performed in page size chunks and in
+ * parallel memories both the flashes are written simultaneously,
+ * hence increase the page_size in multiple of the number of flash
+ * connected in parallel.
+ */
+ page_size *= n_flash;
+
+ } else {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < n_flash) && (to > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
for (i = 0; i < len; ) {
@@ -2258,9 +2390,17 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
/* the size of data remaining on the first page */
page_remain = min_t(size_t, page_size - page_offset, len - i);
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- params = spi_nor_get_params(nor, cur_cs_num);
- addr -= (sz - params->size);
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ u64 aux = addr;
+
+ ret = do_div(aux, n_flash);
+ addr = aux;
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ } else {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+ }
addr = spi_nor_convert_addr(nor, addr);
@@ -2701,7 +2841,15 @@ static int spi_nor_select_erase(struct spi_nor *nor)
if (!erase)
return -EINVAL;
nor->erase_opcode = erase->opcode;
- mtd->erasesize = erase->size;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = erase->size * 2;
+ else
+ mtd->erasesize = erase->size;
return 0;
}
@@ -2719,7 +2867,15 @@ static int spi_nor_select_erase(struct spi_nor *nor)
if (!erase)
return -EINVAL;
- mtd->erasesize = erase->size;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = erase->size * 2;
+ else
+ mtd->erasesize = erase->size;
return 0;
}
@@ -3060,6 +3216,17 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
nor->num_flash++;
}
+ idx = 0;
+ while (idx < SNOR_FLASH_CNT_MAX) {
+ rc = of_property_read_u64_index(np, "parallel-memories", idx, &flash_size[idx]);
+ if (rc)
+ break;
+ idx++;
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL))
+ nor->flags |= SNOR_F_HAS_PARALLEL;
+
+ nor->num_flash++;
+ }
/*
* By default one flash device should be connected
@@ -3068,7 +3235,7 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
if (!nor->num_flash)
nor->num_flash = 1;
- if (nor->flags & SNOR_F_HAS_STACKED) {
+ if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) {
for (idx = 1; idx < nor->num_flash; idx++) {
params = spi_nor_get_params(nor, idx);
params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL);
@@ -3289,10 +3456,14 @@ static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
static int spi_nor_quad_enable(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params;
+ u32 n_flash = 1;
int err, idx;
- for (idx = 0; idx < nor->num_flash; idx++) {
- params = spi_nor_get_params(nor, idx);
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ params = spi_nor_get_params(nor, 0);
if (!params->quad_enable)
return 0;
@@ -3300,14 +3471,32 @@ static int spi_nor_quad_enable(struct spi_nor *nor)
spi_nor_get_protocol_width(nor->write_proto) == 4))
return 0;
/*
- * Set the appropriate CS index before
- * issuing the command.
+ * In parallel mode both chip selects i.e., CS0 &
+ * CS1 need to be asserted simulatneously.
*/
- nor->spimem->spi->cs_index_mask = 0x01 << idx;
-
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
err = params->quad_enable(nor);
if (err)
return err;
+ } else {
+ for (idx = 0; idx < n_flash; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (!params->quad_enable)
+ return 0;
+
+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4))
+ return 0;
+ /*
+ * Set the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 1 << idx;
+
+ err = params->quad_enable(nor);
+ if (err)
+ return err;
+ }
}
return err;
}
@@ -3341,8 +3530,12 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
static int spi_nor_init(struct spi_nor *nor)
{
+ u32 n_flash = 1;
int err, idx;
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
err = spi_nor_set_octal_dtr(nor, true);
if (err) {
dev_dbg(nor->dev, "octal mode not supported\n");
@@ -3382,15 +3575,26 @@ static int spi_nor_init(struct spi_nor *nor)
*/
WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
"enabling reset hack; may not recover from unexpected reboots\n");
- for (idx = 0; idx < nor->num_flash; idx++) {
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
/*
- * Select the appropriate CS index before
- * issuing the command.
+ * In parallel mode both chip selects i.e., CS0 &
+ * CS1 need to be asserted simulatneously.
*/
- nor->spimem->spi->cs_index_mask = 0x01 << idx;
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
err = spi_nor_set_4byte_addr_mode(nor, true);
if (err)
return err;
+ } else {
+ for (idx = 0; idx < n_flash; idx++) {
+ /*
+ * Select the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 1 << idx;
+ err = spi_nor_set_4byte_addr_mode(nor, true);
+ if (err)
+ return err;
+ }
}
}
@@ -3505,19 +3709,23 @@ static void spi_nor_put_device(struct mtd_info *mtd)
static void spi_nor_restore(struct spi_nor *nor)
{
+ u32 n_flash = 1;
int ret;
int idx;
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
/* restore the addressing mode */
if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
nor->flags & SNOR_F_BROKEN_RESET) {
- for (idx = 0; idx < nor->num_flash; idx++) {
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
/*
- * Select the appropriate CS index before
- * issuing the command.
+ * In parallel mode both chip selects i.e., CS0 &
+ * CS1 need to be asserted simulatneously.
*/
- nor->spimem->spi->cs_index_mask = 1 << idx;
- ret = spi_nor_set_4byte_addr_mode(nor, false);
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ spi_nor_set_4byte_addr_mode(nor, false);
if (ret)
/*
* Do not stop the execution in the hope that the flash
@@ -3527,6 +3735,24 @@ static void spi_nor_restore(struct spi_nor *nor)
dev_err(nor->dev,
"Failed to exit 4-byte address mode, err = %d\n",
ret);
+ } else {
+ for (idx = 0; idx < n_flash; idx++) {
+ /*
+ * Select the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 1 << idx;
+ ret = spi_nor_set_4byte_addr_mode(nor, false);
+ if (ret)
+ /*
+ * Do not stop the execution in the hope that the
+ * flash will default to the 3-byte address mode
+ * after the software reset.
+ */
+ dev_err(nor->dev,
+ "Failed to exit 4-byte address mode, err = %d\n",
+ ret);
+ }
}
}
@@ -3595,11 +3821,15 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
u64 total_sz = 0;
+ u32 n_flash = 1;
int idx;
spi_nor_set_mtd_locking_ops(nor);
spi_nor_set_mtd_otp_ops(nor);
+ if (nor->num_flash)
+ n_flash = nor->num_flash;
+
mtd->dev.parent = dev;
if (!mtd->name)
mtd->name = dev_name(dev);
@@ -3613,8 +3843,17 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
else
mtd->_erase = spi_nor_erase;
mtd->writesize = params->writesize;
- mtd->writebufsize = params->page_size;
- for (idx = 0; idx < nor->num_flash; idx++) {
+ /*
+ * In parallel-memories the write operation is
+ * performed on both the flashes simultaneously
+ * one page per flash, so double the writebufsize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->writebufsize = params->page_size << 1;
+ else
+ mtd->writebufsize = params->page_size;
+
+ for (idx = 0; idx < n_flash; idx++) {
params = spi_nor_get_params(nor, idx);
total_sz += params->size;
}
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index b2997eca7551..6c3009796013 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -21,6 +21,9 @@
/* In single configuration enable CS0 */
#define SPI_NOR_ENABLE_CS0 BIT(0)
+/* In parallel configuration enable multiple CS */
+#define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1))
+
/* Standard SPI NOR flash operations. */
#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \
@@ -144,6 +147,7 @@ enum spi_nor_option_flags {
SNOR_F_ECC = BIT(15),
SNOR_F_NO_WP = BIT(16),
SNOR_F_HAS_STACKED = BIT(17),
+ SNOR_F_HAS_PARALLEL = BIT(18),
};
struct spi_nor_read_command {
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 813a5b1a269b..577121ebd6e8 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -478,6 +478,9 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
op.data.nbytes = 2;
}
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ op.data.nbytes = 2;
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
@@ -489,6 +492,8 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
if (ret)
dev_dbg(nor->dev, "error %d reading FSR\n", ret);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ fsr[0] &= fsr[1];
return ret;
}
--
2.17.1
During probe GQSPI driver sets SPI_CONTROLLER_MULTI_CS bit in ctlr->flags
for notifying SPI core about multi CS capability of the controller.
In parallel mode the controller can either split the data between both the
flash or can send the same data to both the flashes, this is determined by
the STRIPE bit. While sending commands to the flashes the GQSPI driver
send the same command to both the flashes by resetting the STRIPE bit, but
while writing/reading data to & from the flash the GQSPI driver splits the
data evenly between both the flashes by setting the STRIPE bit.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/spi/spi-zynqmp-gqspi.c | 39 +++++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index c5d12ddd4ab3..61e91d59014b 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -21,6 +21,7 @@
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/spi/spi-mem.h>
+#include <linux/mtd/spi-nor.h>
/* Generic QSPI register offsets */
#define GQSPI_CONFIG_OFST 0x00000100
@@ -190,6 +191,7 @@ struct qspi_platform_data {
* @op_lock: Operational lock
* @speed_hz: Current SPI bus clock speed in hz
* @has_tapdelay: Used for tapdelay register available in qspi
+ * @is_parallel: Used for multi CS support
*/
struct zynqmp_qspi {
struct spi_controller *ctlr;
@@ -212,8 +214,33 @@ struct zynqmp_qspi {
struct mutex op_lock;
u32 speed_hz;
bool has_tapdelay;
+ bool is_parallel;
};
+/**
+ * zynqmp_gqspi_update_stripe - For GQSPI controller data stripe capabilities
+ * @op: Pointer to mem ops
+ * Return: Status of the data stripe
+ *
+ * Returns true if data stripe need to be enabled, else returns false
+ */
+bool zynqmp_gqspi_update_stripe(const struct spi_mem_op *op)
+{
+ if (op->cmd.opcode == SPINOR_OP_BE_4K ||
+ op->cmd.opcode == SPINOR_OP_BE_32K ||
+ op->cmd.opcode == SPINOR_OP_CHIP_ERASE ||
+ op->cmd.opcode == SPINOR_OP_SE ||
+ op->cmd.opcode == SPINOR_OP_BE_32K_4B ||
+ op->cmd.opcode == SPINOR_OP_SE_4B ||
+ op->cmd.opcode == SPINOR_OP_BE_4K_4B ||
+ op->cmd.opcode == SPINOR_OP_WRSR ||
+ op->cmd.opcode == SPINOR_OP_BRWR ||
+ (op->cmd.opcode == SPINOR_OP_WRSR2 && !op->addr.nbytes))
+ return false;
+
+ return true;
+}
+
/**
* zynqmp_gqspi_read - For GQSPI controller read operation
* @xqspi: Pointer to the zynqmp_qspi structure
@@ -468,7 +495,14 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
- if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
+ if ((qspi->cs_index_mask & GQSPI_SELECT_LOWER_CS) &&
+ (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS)) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_BOTH,
+ GQSPI_SELECT_FLASH_BUS_BOTH);
+ if (!xqspi->is_parallel)
+ xqspi->is_parallel = true;
+ } else if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
zynqmp_gqspi_selectslave(xqspi,
GQSPI_SELECT_FLASH_CS_UPPER,
GQSPI_SELECT_FLASH_BUS_LOWER);
@@ -1137,6 +1171,8 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem,
}
if (op->data.nbytes) {
+ if (xqspi->is_parallel && zynqmp_gqspi_update_stripe(op))
+ genfifoentry |= GQSPI_GENFIFO_STRIPE;
reinit_completion(&xqspi->data_completion);
if (op->data.dir == SPI_MEM_DATA_OUT) {
xqspi->txbuf = (u8 *)op->data.buf.out;
@@ -1332,6 +1368,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
ctlr->dev.of_node = np;
ctlr->auto_runtime_pm = true;
+ ctlr->flags |= SPI_CONTROLLER_MULTI_CS;
ret = devm_spi_register_controller(&pdev->dev, ctlr);
if (ret) {
--
2.17.1
Each flash that is connected in stacked mode should have a separate
parameter structure. So, the flash parameter member(*params) of the spi_nor
structure is changed to an array (*params[2]). The array is used to store
the parameters of each flash connected in stacked configuration.
The current implementation assumes that a maximum of two flashes are
connected in stacked mode and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical.
SPI-NOR is not aware of the chip_select values, for any incoming request
SPI-NOR will decide the flash index with the help of individual flash size
and the configuration type (single/stacked). SPI-NOR will pass on the flash
index information to the SPI core & SPI driver by setting the appropriate
bit in nor->spimem->spi->cs_index_mask. For example, if nth bit of
nor->spimem->spi->cs_index_mask is set then the driver would
assert/de-assert spi->chip_slect[n].
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/core.c | 272 +++++++++++++++++++++++++++++-------
drivers/mtd/spi-nor/core.h | 4 +
include/linux/mtd/spi-nor.h | 15 +-
3 files changed, 240 insertions(+), 51 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 93ae69b7ff83..e990be7c7eb6 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1821,13 +1821,18 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- u32 addr, len;
+ struct spi_nor_flash_parameter *params;
+ u32 addr, len, offset, cur_cs_num = 0;
uint32_t rem;
int ret;
+ u64 sz;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len);
+ params = spi_nor_get_params(nor, 0);
+ sz = params->size;
+
if (spi_nor_has_uniform_erase(nor)) {
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
@@ -1849,23 +1854,27 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (ret)
goto erase_err;
- ret = spi_nor_erase_chip(nor);
- spi_nor_unlock_device(nor);
- if (ret)
- goto erase_err;
+ while (cur_cs_num < nor->num_flash) {
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ ret = spi_nor_erase_chip(nor);
+ spi_nor_unlock_device(nor);
+ if (ret)
+ goto erase_err;
- /*
- * Scale the timeout linearly with the size of the flash, with
- * a minimum calibrated to an old 2MB flash. We could try to
- * pull these from CFI/SFDP, but these values should be good
- * enough for now.
- */
- timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
- CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
- (unsigned long)(mtd->size / SZ_2M));
- ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
- if (ret)
- goto erase_err;
+ /*
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+ (unsigned long)(params->size / SZ_2M));
+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
+ if (ret)
+ goto erase_err;
+ cur_cs_num++;
+ }
/* REVISIT in some cases we could speed up erasing large regions
* by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
@@ -1874,12 +1883,26 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
/* "sector"-at-a-time erase */
} else if (spi_nor_has_uniform_erase(nor)) {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < nor->num_flash) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+
while (len) {
ret = spi_nor_lock_device(nor);
if (ret)
goto erase_err;
- ret = spi_nor_erase_sector(nor, addr);
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ offset = addr;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+
+ ret = spi_nor_erase_sector(nor, offset);
spi_nor_unlock_device(nor);
if (ret)
goto erase_err;
@@ -1890,13 +1913,45 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
addr += mtd->erasesize;
len -= mtd->erasesize;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
/* erase multiple sectors */
} else {
- ret = spi_nor_erase_multi_sectors(nor, addr, len);
- if (ret)
- goto erase_err;
+ u64 erase_len = 0;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < nor->num_flash) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ /* perform multi sector erase onec per Flash*/
+ while (len) {
+ erase_len = (len > (sz - addr)) ? (sz - addr) : len;
+ offset = addr;
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+ ret = spi_nor_erase_multi_sectors(nor, offset, erase_len);
+ if (ret)
+ goto erase_err;
+ len -= erase_len;
+ addr += erase_len;
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
ret = spi_nor_write_disable(nor);
@@ -2087,9 +2142,11 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ struct spi_nor_flash_parameter *params;
+ ssize_t ret, read_len, len_lock = len;
loff_t from_lock = from;
- size_t len_lock = len;
- ssize_t ret;
+ u32 cur_cs_num = 0;
+ u64 sz;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
@@ -2097,9 +2154,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
if (ret)
return ret;
+ params = spi_nor_get_params(nor, 0);
+ sz = params->size;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < nor->num_flash) && (from > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
while (len) {
loff_t addr = from;
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ read_len = (len > (sz - addr)) ? (sz - addr) : len;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+
addr = spi_nor_convert_addr(nor, addr);
ret = spi_nor_read_data(nor, addr, len, buf);
@@ -2111,11 +2182,22 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
if (ret < 0)
goto read_err;
- WARN_ON(ret > len);
+ WARN_ON(ret > read_len);
*retlen += ret;
buf += ret;
from += ret;
len -= ret;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ *
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && (from > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+
}
ret = 0;
@@ -2136,8 +2218,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
struct spi_nor *nor = mtd_to_spi_nor(mtd);
struct spi_nor_flash_parameter *params;
size_t page_offset, page_remain, i;
+ u32 page_size, cur_cs_num = 0;
ssize_t ret;
- u32 page_size;
+ u64 sz;
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
@@ -2147,6 +2230,14 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
params = spi_nor_get_params(nor, 0);
page_size = params->page_size;
+ sz = params->size;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < nor->num_flash) && (to > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
for (i = 0; i < len; ) {
ssize_t written;
@@ -2167,6 +2258,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
/* the size of data remaining on the first page */
page_remain = min_t(size_t, page_size - page_offset, len - i);
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+
addr = spi_nor_convert_addr(nor, addr);
ret = spi_nor_lock_device(nor);
@@ -2184,6 +2279,15 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
goto write_err;
*retlen += written;
i += written;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && ((to + i) > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
write_err:
@@ -2297,8 +2401,6 @@ int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
static int spi_nor_spimem_check_op(struct spi_nor *nor,
struct spi_mem_op *op)
{
- struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
-
/*
* First test with 4 address bytes. The opcode itself might
* be a 3B addressing opcode but we don't care, because
@@ -2307,7 +2409,7 @@ static int spi_nor_spimem_check_op(struct spi_nor *nor,
*/
op->addr.nbytes = 4;
if (!spi_mem_supports_op(nor->spimem, op)) {
- if (params->size > SZ_16M)
+ if (nor->mtd.size > SZ_16M)
return -EOPNOTSUPP;
/* If flash size <= 16MB, 3 address bytes are sufficient */
@@ -2905,7 +3007,10 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
static int spi_nor_late_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
- int ret;
+ struct device_node *np = spi_nor_get_flash_node(nor);
+ u64 flash_size[SNOR_FLASH_CNT_MAX];
+ u32 idx = 0;
+ int rc, ret;
if (nor->manufacturer && nor->manufacturer->fixups &&
nor->manufacturer->fixups->late_init) {
@@ -2937,6 +3042,44 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
if (params->n_banks > 1)
params->bank_size = div64_u64(params->size, params->n_banks);
+ nor->num_flash = 0;
+
+ /*
+ * The flashes that are connected in stacked mode should be of same make.
+ * Except the flash size all other properties are identical for all the
+ * flashes connected in stacked mode.
+ * The flashes that are connected in parallel mode should be identical.
+ */
+ while (idx < SNOR_FLASH_CNT_MAX) {
+ rc = of_property_read_u64_index(np, "stacked-memories", idx, &flash_size[idx]);
+ if (rc)
+ break;
+ idx++;
+ if (!(nor->flags & SNOR_F_HAS_STACKED))
+ nor->flags |= SNOR_F_HAS_STACKED;
+
+ nor->num_flash++;
+ }
+
+ /*
+ * By default one flash device should be connected
+ * so, nor->num_flash is 1.
+ */
+ if (!nor->num_flash)
+ nor->num_flash = 1;
+
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ for (idx = 1; idx < nor->num_flash; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL);
+ if (params) {
+ memcpy(params, spi_nor_get_params(nor, 0), sizeof(*params));
+ params->size = flash_size[idx];
+ spi_nor_set_params(nor, idx, params);
+ }
+ }
+ }
+
return 0;
}
@@ -3145,16 +3288,28 @@ static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
*/
static int spi_nor_quad_enable(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ struct spi_nor_flash_parameter *params;
+ int err, idx;
- if (!params->quad_enable)
- return 0;
+ for (idx = 0; idx < nor->num_flash; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (!params->quad_enable)
+ return 0;
- if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
- spi_nor_get_protocol_width(nor->write_proto) == 4))
- return 0;
+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4))
+ return 0;
+ /*
+ * Set the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 0x01 << idx;
- return params->quad_enable(nor);
+ err = params->quad_enable(nor);
+ if (err)
+ return err;
+ }
+ return err;
}
/**
@@ -3186,7 +3341,7 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
static int spi_nor_init(struct spi_nor *nor)
{
- int err;
+ int err, idx;
err = spi_nor_set_octal_dtr(nor, true);
if (err) {
@@ -3227,9 +3382,16 @@ static int spi_nor_init(struct spi_nor *nor)
*/
WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
"enabling reset hack; may not recover from unexpected reboots\n");
- err = spi_nor_set_4byte_addr_mode(nor, true);
- if (err)
- return err;
+ for (idx = 0; idx < nor->num_flash; idx++) {
+ /*
+ * Select the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 0x01 << idx;
+ err = spi_nor_set_4byte_addr_mode(nor, true);
+ if (err)
+ return err;
+ }
}
return 0;
@@ -3344,18 +3506,28 @@ static void spi_nor_put_device(struct mtd_info *mtd)
static void spi_nor_restore(struct spi_nor *nor)
{
int ret;
+ int idx;
/* restore the addressing mode */
if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
nor->flags & SNOR_F_BROKEN_RESET) {
- ret = spi_nor_set_4byte_addr_mode(nor, false);
- if (ret)
+ for (idx = 0; idx < nor->num_flash; idx++) {
/*
- * Do not stop the execution in the hope that the flash
- * will default to the 3-byte address mode after the
- * software reset.
+ * Select the appropriate CS index before
+ * issuing the command.
*/
- dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret);
+ nor->spimem->spi->cs_index_mask = 1 << idx;
+ ret = spi_nor_set_4byte_addr_mode(nor, false);
+ if (ret)
+ /*
+ * Do not stop the execution in the hope that the flash
+ * will default to the 3-byte address mode after the
+ * software reset.
+ */
+ dev_err(nor->dev,
+ "Failed to exit 4-byte address mode, err = %d\n",
+ ret);
+ }
}
if (nor->flags & SNOR_F_SOFT_RESET)
@@ -3422,6 +3594,8 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
+ u64 total_sz = 0;
+ int idx;
spi_nor_set_mtd_locking_ops(nor);
spi_nor_set_mtd_otp_ops(nor);
@@ -3440,7 +3614,11 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
mtd->_erase = spi_nor_erase;
mtd->writesize = params->writesize;
mtd->writebufsize = params->page_size;
- mtd->size = params->size;
+ for (idx = 0; idx < nor->num_flash; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ total_sz += params->size;
+ }
+ mtd->size = total_sz;
mtd->_read = spi_nor_read;
/* Might be already set by some SST flashes. */
if (!mtd->_write)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 93cd2fc3606d..b2997eca7551 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -18,6 +18,9 @@
#define SPI_NOR_DEFAULT_N_BANKS 1
#define SPI_NOR_DEFAULT_SECTOR_SIZE SZ_64K
+/* In single configuration enable CS0 */
+#define SPI_NOR_ENABLE_CS0 BIT(0)
+
/* Standard SPI NOR flash operations. */
#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \
@@ -140,6 +143,7 @@ enum spi_nor_option_flags {
SNOR_F_RWW = BIT(14),
SNOR_F_ECC = BIT(15),
SNOR_F_NO_WP = BIT(16),
+ SNOR_F_HAS_STACKED = BIT(17),
};
struct spi_nor_read_command {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 59909e7d6f53..9d72b0bbab94 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -127,6 +127,12 @@
#define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
#define SR2_QUAD_EN_BIT7 BIT(7)
+/*
+ * Maximum number of flashes that can be connected
+ * in stacked/parallel configuration
+ */
+#define SNOR_FLASH_CNT_MAX 4
+
/* Supported SPI protocols */
#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
#define SNOR_PROTO_INST_SHIFT 16
@@ -378,6 +384,7 @@ struct spi_nor_flash_parameter;
* hooks, or dynamically when parsing the SFDP tables.
* @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
* @priv: pointer to the private data
+ * @num_flash number of flashes connected in parallel or stacked mode
*/
struct spi_nor {
struct mtd_info mtd;
@@ -412,13 +419,13 @@ struct spi_nor {
const struct spi_nor_controller_ops *controller_ops;
- struct spi_nor_flash_parameter *params;
+ struct spi_nor_flash_parameter *params[SNOR_FLASH_CNT_MAX];
struct {
struct spi_mem_dirmap_desc *rdesc;
struct spi_mem_dirmap_desc *wdesc;
} dirmap;
-
+ u32 num_flash;
void *priv;
};
@@ -435,13 +442,13 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
static inline struct spi_nor_flash_parameter *spi_nor_get_params(const struct spi_nor *nor, u8 idx)
{
- return nor->params;
+ return nor->params[idx];
}
static inline void spi_nor_set_params(struct spi_nor *nor, u8 idx,
struct spi_nor_flash_parameter *params)
{
- nor->params = params;
+ nor->params[idx] = params;
}
/**
* spi_nor_scan() - scan the SPI NOR
--
2.17.1
On Sat, Nov 18, 2023 at 07:24:39PM +0530, Amit Kumar Mahapatra wrote:
> AMD-Xilinx GQSPI controller has two advanced mode that allows the
> controller to consider two flashes as one single device.
This breaks an x86 allmodconfig build:
/build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c: In function ‘cs35l56_hda_spi
_probe’:
/build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:32:52: error: passing argumen
t 2 of ‘cs35l56_hda_common_probe’ makes integer from pointer without a cast [-We
rror=int-conversion]
32 | ret = cs35l56_hda_common_probe(cs35l56, spi->chip_select);
| ~~~^~~~~~~~~~~~~
| |
| u8 * {aka unsigned ch
ar *}
In file included from /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:12:
/build/stage/linux/sound/pci/hda/cs35l56_hda.h:45:63: note: expected ‘int’ but a
rgument is of type ‘u8 *’ {aka ‘unsigned char *’}
45 | int cs35l56_hda_common_probe(struct cs35l56_hda *cs35l56, int id);
| ~~~~^~
On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
> AMD-Xilinx GQSPI controller has two advanced mode that allows the
> controller to consider two flashes as one single device.
>
> One of these two mode is the parallel mode in which each byte of data is
> stored in both devices, the even bits in the lower flash & the odd bits in
> the upper flash. The byte split is automatically handled by the QSPI
> controller.
>
> The other mode is the stacked mode in which both the flashes share the
> same SPI bus but each of the device contain half of the data. In this mode,
> the controller does not follow CS requests but instead internally wires the
> two CS levels with the value of the most significant address bit.
>
> For supporting both these modes SPI core need to be updated for providing
> multiple CS for a single SPI device.
>
> For adding multi CS support the SPI device need to be aware of all the CS
> values. So, the "chip_select" member in the spi_device structure is now an
> array that holds all the CS values.
>
> spi_device structure now has a "cs_index_mask" member. This acts as an
> index to the chip_select array. If nth bit of spi->cs_index_mask is set
> then the driver would assert spi->chip_select[n].
>
> In parallel mode all the chip selects are asserted/de-asserted
> simultaneously and each byte of data is stored in both devices, the even
> bits in one, the odd bits in the other. The split is automatically handled
> by the GQSPI controller. The GQSPI controller supports a maximum of two
> flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is
> added in the spi controller flags, through ctlr->flags the spi core
> will make sure that the controller is capable of handling multiple chip
> selects at once.
>
> For supporting multiple CS via GPIO the cs_gpiod member of the spi_device
> structure is now an array that holds the gpio descriptor for each
> chipselect.
>
> CS GPIO is not tested due to unavailability of necessary hardware setup.
>
> Signed-off-by: Amit Kumar Mahapatra <[email protected]>
> ---
> Hello @Stefen,
> We restructured the SPI core implementation, for handling arbitrary number
> of devices connected in parallel(multi-cs) or stacked mode. We have tested
> this updated patch on native-cs setup but couldn't test cs-gpio due to
> unavailability of a proper setup. If possible, could you please retest
> the cs-gpio use case with this updated patch and provide your feedback.
Hi,
I tested this chain on 2 different systems using GPIOs as chip selects,
and see the
same error on both:
[Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
Let me know if you need any further testing.
Thanks,
Stefan Binding
> ---
> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---------
> include/linux/spi/spi.h | 51 ++++++++---
> 2 files changed, 191 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index 8ead7acb99f3..ff66147ba95f 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev, void *data)
> {
> struct spi_device *spi = to_spi_device(dev);
> struct spi_device *new_spi = data;
> -
> - if (spi->controller == new_spi->controller &&
> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
> - return -EBUSY;
> + int idx, nw_idx;
> + u8 cs, cs_nw;
> +
> + if (spi->controller == new_spi->controller) {
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + cs = spi_get_chipselect(spi, idx);
> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> + cs_nw = spi_get_chipselect(spi, nw_idx);
> + if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> + dev_err(dev, "chipselect %d already in use\n", cs_nw);
> + return -EBUSY;
> + }
> + }
> + }
> + }
> return 0;
> }
>
> @@ -629,13 +640,32 @@ static int __spi_add_device(struct spi_device *spi)
> {
> struct spi_controller *ctlr = spi->controller;
> struct device *dev = ctlr->dev.parent;
> - int status;
> + int status, idx, nw_idx;
> + u8 cs, nw_cs;
> +
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + /* Chipselects are numbered 0..max; validate. */
> + cs = spi_get_chipselect(spi, idx);
> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
> + dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx),
> + ctlr->num_chipselect);
> + return -EINVAL;
> + }
> + }
>
> - /* Chipselects are numbered 0..max; validate. */
> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
> - ctlr->num_chipselect);
> - return -EINVAL;
> + /*
> + * Make sure that multiple logical CS doesn't map to the same physical CS.
> + * For example, spi->chip_select[0] != spi->chip_select[1] and so on.
> + */
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + cs = spi_get_chipselect(spi, idx);
> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> + nw_cs = spi_get_chipselect(spi, nw_idx);
> + if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> + dev_err(dev, "chipselect %d already in use\n", nw_cs);
> + return -EBUSY;
> + }
> + }
> }
>
> /* Set the bus ID string */
> @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device *spi)
> * its configuration.
> */
> status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
> - if (status) {
> - dev_err(dev, "chipselect %d already in use\n",
> - spi_get_chipselect(spi, 0));
> + if (status)
> return status;
> - }
>
> /* Controller may unregister concurrently */
> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) &&
> @@ -659,8 +686,15 @@ static int __spi_add_device(struct spi_device *spi)
> return -ENODEV;
> }
>
> - if (ctlr->cs_gpiods)
> - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi, 0)]);
> + if (ctlr->cs_gpiods) {
> + u8 cs;
> +
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + cs = spi_get_chipselect(spi, idx);
> + if (cs != 0xFF)
> + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]);
> + }
> + }
>
> /*
> * Drivers may modify this initial i/o setup, but will
> @@ -701,6 +735,9 @@ int spi_add_device(struct spi_device *spi)
> struct spi_controller *ctlr = spi->controller;
> int status;
>
> + /* Set the bus ID string */
> + spi_dev_set_name(spi);
> +
> mutex_lock(&ctlr->add_lock);
> status = __spi_add_device(spi);
> mutex_unlock(&ctlr->add_lock);
> @@ -942,32 +979,51 @@ static void spi_res_release(struct spi_controller *ctlr, struct spi_message *mes
> }
>
> /*-------------------------------------------------------------------------*/
> +static inline bool spi_is_last_cs(struct spi_device *spi)
> +{
> + u8 idx;
> + bool last = false;
> +
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + if ((spi->cs_index_mask >> idx) & 0x01) {
> + if (spi->controller->last_cs[idx] == spi_get_chipselect(spi, idx))
> + last = true;
> + }
> + }
> + return last;
> +}
> +
>
> static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
> {
> bool activate = enable;
> + u8 idx;
>
> /*
> * Avoid calling into the driver (or doing delays) if the chip select
> * isn't actually changing from the last time this was called.
> */
> - if (!force && ((enable && spi->controller->last_cs == spi_get_chipselect(spi, 0)) ||
> - (!enable && spi->controller->last_cs != spi_get_chipselect(spi, 0))) &&
> + if (!force && ((enable && spi->controller->last_cs_index_mask == spi->cs_index_mask &&
> + spi_is_last_cs(spi)) ||
> + (!enable && spi->controller->last_cs_index_mask == spi->cs_index_mask &&
> + !spi_is_last_cs(spi))) &&
> (spi->controller->last_cs_mode_high == (spi->mode & SPI_CS_HIGH)))
> return;
>
> trace_spi_set_cs(spi, activate);
>
> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi, 0) : -1;
> spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
>
> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) && !activate)
> - spi_delay_exec(&spi->cs_hold, NULL);
> -
> if (spi->mode & SPI_CS_HIGH)
> enable = !enable;
>
> - if (spi_get_csgpiod(spi, 0)) {
> + if (spi_is_csgpiod(spi)) {
> + if (!spi->controller->set_cs_timing && !activate)
> + spi_delay_exec(&spi->cs_hold, NULL);
> +
> if (!(spi->mode & SPI_NO_CS)) {
> /*
> * Historically ACPI has no means of the GPIO polarity and
> @@ -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
> * ambiguity. That's why we use enable, that takes SPI_CS_HIGH
> * into account.
> */
> - if (has_acpi_companion(&spi->dev))
> - gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> - else
> - /* Polarity handled by GPIO library */
> - gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + if (((spi->cs_index_mask >> idx) & 0x01) &&
> + spi_get_csgpiod(spi, idx)) {
> + if (has_acpi_companion(&spi->dev))
> + gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> + !enable);
> + else
> + /* Polarity handled by GPIO library */
> + gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> + activate);
> +
> + if (activate)
> + spi_delay_exec(&spi->cs_setup, NULL);
> + else
> + spi_delay_exec(&spi->cs_inactive, NULL);
> + }
> + }
> }
> /* Some SPI masters need both GPIO CS & slave_select */
> if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
> spi->controller->set_cs)
> spi->controller->set_cs(spi, !enable);
> +
> + if (!spi->controller->set_cs_timing) {
> + if (activate)
> + spi_delay_exec(&spi->cs_setup, NULL);
> + else
> + spi_delay_exec(&spi->cs_inactive, NULL);
> + }
> } else if (spi->controller->set_cs) {
> spi->controller->set_cs(spi, !enable);
> }
> -
> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
> - if (activate)
> - spi_delay_exec(&spi->cs_setup, NULL);
> - else
> - spi_delay_exec(&spi->cs_inactive, NULL);
> - }
> }
>
> #ifdef CONFIG_HAS_DMA
> @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct device_node *nc,
> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> struct device_node *nc)
> {
> - u32 value;
> - int rc;
> + u32 value, cs[SPI_CS_CNT_MAX];
> + int rc, idx;
>
> /* Mode (clock phase/polarity/etc.) */
> if (of_property_read_bool(nc, "spi-cpha"))
> @@ -2295,14 +2363,52 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> return 0;
> }
>
> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
> + dev_err(&ctlr->dev, "No. of CS is more than max. no. of supported CS\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * Zero(0) is a valid physical CS value and can be located at any
> + * logical CS in the spi->chip_select[]. If all the physical CS
> + * are initialized to 0 then It would be difficult to differentiate
> + * between a valid physical CS 0 & an unused logical CS whose physical
> + * CS can be 0. As a solution to this issue initialize all the CS to 0xFF.
> + * Now all the unused logical CS will have 0xFF physical CS value & can be
> + * ignore while performing physical CS validity checks.
> + */
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(spi, idx, 0xFF);
> +
> /* Device address */
> - rc = of_property_read_u32(nc, "reg", &value);
> - if (rc) {
> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> + SPI_CS_CNT_MAX);
> + if (rc < 0) {
> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n",
> nc, rc);
> return rc;
> }
> - spi_set_chipselect(spi, 0, value);
> + if (rc > ctlr->num_chipselect) {
> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr->num_chipselect (%d)\n",
> + nc, rc);
> + return rc;
> + }
> + if ((of_property_read_bool(nc, "parallel-memories")) &&
> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> + dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n");
> + return -EINVAL;
> + }
> + for (idx = 0; idx < rc; idx++)
> + spi_set_chipselect(spi, idx, cs[idx]);
> +
> + /* spi->chip_select[i] gives the corresponding physical CS for logical CS i
> + * logical CS number is represented by setting the ith bit in spi->cs_index_mask
> + * So, for example, if spi->cs_index_mask = 0x01 then logical CS number is 0 and
> + * spi->chip_select[0] will give the physical CS.
> + * By default spi->chip_select[0] will hold the physical CS number so, set
> + * spi->cs_index_mask as 0x01.
> + */
> + spi->cs_index_mask = 0x01;
>
> /* Device speed */
> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
> @@ -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller *ctlr)
> struct boardinfo *bi;
> int first_dynamic;
> int status;
> + int idx;
>
> if (!dev)
> return -ENODEV;
> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct spi_controller *ctlr)
> }
>
> /* Setting last_cs to -1 means no chip selected */
> - ctlr->last_cs = -1;
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + ctlr->last_cs[idx] = -1;
>
> status = device_add(&ctlr->dev);
> if (status < 0)
> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
> * cs_change is set for each transfer.
> */
> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits & SPI_CS_WORD) ||
> - spi_get_csgpiod(spi, 0))) {
> + spi_is_csgpiod(spi))) {
> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
> int ret;
>
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 7b4baff63c5c..871d3a6d879b 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -20,6 +20,9 @@
>
> #include <uapi/linux/spi/spi.h>
>
> +/* Max no. of CS supported per spi device */
> +#define SPI_CS_CNT_MAX 4
> +
> struct dma_chan;
> struct software_node;
> struct ptp_system_timestamp;
> @@ -132,7 +135,8 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> * @max_speed_hz: Maximum clock rate to be used with this chip
> * (on this board); may be changed by the device's driver.
> * The spi_transfer.speed_hz can override this for each transfer.
> - * @chip_select: Chipselect, distinguishing chips handled by @controller.
> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
> + * the corresponding physical CS for logical CS i.
> * @mode: The spi mode defines how data is clocked out and in.
> * This may be changed by the device's driver.
> * The "active low" default for chipselect mode can be overridden
> @@ -157,8 +161,8 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> * the device will bind to the named driver and only the named driver.
> * Do not set directly, because core frees it; use driver_set_override() to
> * set or clear it.
> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL when
> - * not using a GPIO line)
> + * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines
> + * (optional, NULL when not using a GPIO line)
> * @word_delay: delay to be inserted between consecutive
> * words of a transfer
> * @cs_setup: delay to be introduced by the controller after CS is asserted
> @@ -167,6 +171,7 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> * deasserted. If @cs_change_delay is used from @spi_transfer, then the
> * two delays will be added up.
> * @pcpu_statistics: statistics for the spi_device
> + * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
> *
> * A @spi_device is used to interchange data between an SPI slave
> * (usually a discrete chip) and CPU memory.
> @@ -182,7 +187,7 @@ struct spi_device {
> struct spi_controller *controller;
> struct spi_controller *master; /* Compatibility layer */
> u32 max_speed_hz;
> - u8 chip_select;
> + u8 chip_select[SPI_CS_CNT_MAX];
> u8 bits_per_word;
> bool rt;
> #define SPI_NO_TX BIT(31) /* No transmit wire */
> @@ -213,7 +218,7 @@ struct spi_device {
> void *controller_data;
> char modalias[SPI_NAME_SIZE];
> const char *driver_override;
> - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor */
> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */
> struct spi_delay word_delay; /* Inter-word delay */
> /* CS delays */
> struct spi_delay cs_setup;
> @@ -223,6 +228,13 @@ struct spi_device {
> /* The statistics */
> struct spi_statistics __percpu *pcpu_statistics;
>
> + /* Bit mask of the chipselect(s) that the driver need to use from
> + * the chipselect array.When the controller is capable to handle
> + * multiple chip selects & memories are connected in parallel
> + * then more than one bit need to be set in cs_index_mask.
> + */
> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> +
> /*
> * Likely need more hooks for more protocol options affecting how
> * the controller talks to each chip, like:
> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const struct spi_device *spi)
>
> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
> {
> - return spi->chip_select;
> + return spi->chip_select[idx];
> }
>
> static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect)
> {
> - spi->chip_select = chipselect;
> + spi->chip_select[idx] = chipselect;
> }
>
> static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx)
> {
> - return spi->cs_gpiod;
> + return spi->cs_gpiod[idx];
> }
>
> static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod)
> {
> - spi->cs_gpiod = csgpiod;
> + spi->cs_gpiod[idx] = csgpiod;
> +}
> +
> +static inline bool spi_is_csgpiod(struct spi_device *spi)
> +{
> + u8 idx;
> +
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + if (spi_get_csgpiod(spi, idx))
> + return true;
> + }
> + return false;
> }
>
> /**
> @@ -399,6 +422,8 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> * @bus_lock_spinlock: spinlock for SPI bus locking
> * @bus_lock_mutex: mutex for exclusion of multiple callers
> * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
> + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
> + * more than one chip select at once.
> * @setup: updates the device mode and clocking records used by a
> * device's SPI controller; protocol code may call this. This
> * must fail if an unrecognized or unsupported mode is requested.
> @@ -567,6 +592,11 @@ struct spi_controller {
> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */
> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */
> + /*
> + * The spi-controller has multi chip select capability and can
> + * assert/de-assert more than one chip select at once.
> + */
> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
>
> /* Flag indicating if the allocation of this struct is devres-managed */
> bool devm_allocated;
> @@ -677,7 +707,8 @@ struct spi_controller {
> bool rt;
> bool auto_runtime_pm;
> bool cur_msg_mapped;
> - char last_cs;
> + char last_cs[SPI_CS_CNT_MAX];
> + char last_cs_index_mask;
> bool last_cs_mode_high;
> bool fallback;
> struct completion xfer_completion;
Hello Mark,
> -----Original Message-----
> From: Mark Brown <[email protected]>
> Sent: Monday, November 20, 2023 7:33 PM
> To: Mahapatra, Amit Kumar <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>; linux-
> [email protected]; git (AMD-Xilinx) <[email protected]>;
> [email protected]
> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>
> On Sat, Nov 18, 2023 at 07:24:39PM +0530, Amit Kumar Mahapatra wrote:
> > AMD-Xilinx GQSPI controller has two advanced mode that allows the
> > controller to consider two flashes as one single device.
>
> This breaks an x86 allmodconfig build:
The cause of this failure are the following patches, which neglects to
utilize spi_get_chipselect() for retrieving the CS value. Instead,
it directly accesses spi->chip_select.
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
In my upcoming series, I will address these issues.
Regards,
Amit
>
> /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c: In function
> ‘cs35l56_hda_spi
> _probe’:
> /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:32:52: error: passing
> argumen t 2 of ‘cs35l56_hda_common_probe’ makes integer from pointer
> without a cast [-We rror=int-conversion]
> 32 | ret = cs35l56_hda_common_probe(cs35l56, spi->chip_select);
> | ~~~^~~~~~~~~~~~~
> | |
> | u8 * {aka unsigned ch
> ar *}
> In file included from /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:12:
> /build/stage/linux/sound/pci/hda/cs35l56_hda.h:45:63: note: expected ‘int’
> but a rgument is of type ‘u8 *’ {aka ‘unsigned char *’}
> 45 | int cs35l56_hda_common_probe(struct cs35l56_hda *cs35l56, int id);
> | ~~~~^~
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Monday, November 20, 2023 8:00 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>; linux-
> [email protected]; git (AMD-Xilinx) <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>
>
> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
> > AMD-Xilinx GQSPI controller has two advanced mode that allows the
> > controller to consider two flashes as one single device.
> >
> > One of these two mode is the parallel mode in which each byte of data
> > is stored in both devices, the even bits in the lower flash & the odd
> > bits in the upper flash. The byte split is automatically handled by
> > the QSPI controller.
> >
> > The other mode is the stacked mode in which both the flashes share the
> > same SPI bus but each of the device contain half of the data. In this
> > mode, the controller does not follow CS requests but instead
> > internally wires the two CS levels with the value of the most significant
> address bit.
> >
> > For supporting both these modes SPI core need to be updated for
> > providing multiple CS for a single SPI device.
> >
> > For adding multi CS support the SPI device need to be aware of all the
> > CS values. So, the "chip_select" member in the spi_device structure is
> > now an array that holds all the CS values.
> >
> > spi_device structure now has a "cs_index_mask" member. This acts as an
> > index to the chip_select array. If nth bit of spi->cs_index_mask is
> > set then the driver would assert spi->chip_select[n].
> >
> > In parallel mode all the chip selects are asserted/de-asserted
> > simultaneously and each byte of data is stored in both devices, the
> > even bits in one, the odd bits in the other. The split is
> > automatically handled by the GQSPI controller. The GQSPI controller
> > supports a maximum of two flashes connected in parallel mode. A
> > SPI_CONTROLLER_MULTI_CS flag bit is added in the spi controller flags,
> > through ctlr->flags the spi core will make sure that the controller is
> > capable of handling multiple chip selects at once.
> >
> > For supporting multiple CS via GPIO the cs_gpiod member of the
> > spi_device structure is now an array that holds the gpio descriptor
> > for each chipselect.
> >
> > CS GPIO is not tested due to unavailability of necessary hardware setup.
> >
> > Signed-off-by: Amit Kumar Mahapatra <[email protected]>
> > ---
> > Hello @Stefen,
> > We restructured the SPI core implementation, for handling arbitrary
> > number of devices connected in parallel(multi-cs) or stacked mode. We
> > have tested this updated patch on native-cs setup but couldn't test
> > cs-gpio due to unavailability of a proper setup. If possible, could
> > you please retest the cs-gpio use case with this updated patch and provide
> your feedback.
>
> Hi,
>
> I tested this chain on 2 different systems using GPIOs as chip selects, and see
> the same error on both:
> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
>
> Let me know if you need any further testing.
>
> Thanks,
>
> Stefan Binding
>
> > ---
> > drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---------
> > include/linux/spi/spi.h | 51 ++++++++---
> > 2 files changed, 191 insertions(+), 52 deletions(-)
> >
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > 8ead7acb99f3..ff66147ba95f 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev, void
> *data)
> > {
> > struct spi_device *spi = to_spi_device(dev);
> > struct spi_device *new_spi = data;
> > -
> > - if (spi->controller == new_spi->controller &&
> > - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
> > - return -EBUSY;
> > + int idx, nw_idx;
> > + u8 cs, cs_nw;
> > +
> > + if (spi->controller == new_spi->controller) {
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + cs = spi_get_chipselect(spi, idx);
> > + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> nw_idx++) {
> > + cs_nw = spi_get_chipselect(spi, nw_idx);
Thank you for dedicating your time to test my patch.
As per my analysis the error is reported from here as we are
supplying the former SPI device structure to retrieve the CS
value for the new SPI devices.
To fix this, could you kindly substitute the above line with
cs_nw = spi_get_chipselect(new_spi, nw_idx);
and rerun your tests?
If it works correctly, I will incorporate this fix into my
upcoming series.
Regards,
Amit
> > + if (cs != 0xFF && cs_nw != 0xFF && cs ==
> cs_nw) {
> > + dev_err(dev, "chipselect %d already in
> use\n", cs_nw);
> > + return -EBUSY;
> > + }
> > + }
> > + }
> > + }
> > return 0;
> > }
> >
> > @@ -629,13 +640,32 @@ static int __spi_add_device(struct spi_device *spi)
> > {
> > struct spi_controller *ctlr = spi->controller;
> > struct device *dev = ctlr->dev.parent;
> > - int status;
> > + int status, idx, nw_idx;
> > + u8 cs, nw_cs;
> > +
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + /* Chipselects are numbered 0..max; validate. */
> > + cs = spi_get_chipselect(spi, idx);
> > + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
> > + dev_err(dev, "cs%d >= max %d\n",
> spi_get_chipselect(spi, idx),
> > + ctlr->num_chipselect);
> > + return -EINVAL;
> > + }
> > + }
> >
> > - /* Chipselects are numbered 0..max; validate. */
> > - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> > - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
> > - ctlr->num_chipselect);
> > - return -EINVAL;
> > + /*
> > + * Make sure that multiple logical CS doesn't map to the same
> physical CS.
> > + * For example, spi->chip_select[0] != spi->chip_select[1] and so on.
> > + */
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + cs = spi_get_chipselect(spi, idx);
> > + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> > + nw_cs = spi_get_chipselect(spi, nw_idx);
> > + if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> > + dev_err(dev, "chipselect %d already in use\n",
> nw_cs);
> > + return -EBUSY;
> > + }
> > + }
> > }
> >
> > /* Set the bus ID string */
> > @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device *spi)
> > * its configuration.
> > */
> > status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
> > - if (status) {
> > - dev_err(dev, "chipselect %d already in use\n",
> > - spi_get_chipselect(spi, 0));
> > + if (status)
> > return status;
> > - }
> >
> > /* Controller may unregister concurrently */
> > if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8 +686,15 @@
> static
> > int __spi_add_device(struct spi_device *spi)
> > return -ENODEV;
> > }
> >
> > - if (ctlr->cs_gpiods)
> > - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi,
> 0)]);
> > + if (ctlr->cs_gpiods) {
> > + u8 cs;
> > +
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + cs = spi_get_chipselect(spi, idx);
> > + if (cs != 0xFF)
> > + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]);
> > + }
> > + }
> >
> > /*
> > * Drivers may modify this initial i/o setup, but will @@ -701,6
> > +735,9 @@ int spi_add_device(struct spi_device *spi)
> > struct spi_controller *ctlr = spi->controller;
> > int status;
> >
> > + /* Set the bus ID string */
> > + spi_dev_set_name(spi);
> > +
> > mutex_lock(&ctlr->add_lock);
> > status = __spi_add_device(spi);
> > mutex_unlock(&ctlr->add_lock);
> > @@ -942,32 +979,51 @@ static void spi_res_release(struct spi_controller
> *ctlr, struct spi_message *mes
> > }
> >
> >
> > /*--------------------------------------------------------------------
> > -----*/
> > +static inline bool spi_is_last_cs(struct spi_device *spi) {
> > + u8 idx;
> > + bool last = false;
> > +
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + if ((spi->cs_index_mask >> idx) & 0x01) {
> > + if (spi->controller->last_cs[idx] ==
> spi_get_chipselect(spi, idx))
> > + last = true;
> > + }
> > + }
> > + return last;
> > +}
> > +
> >
> > static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
> > {
> > bool activate = enable;
> > + u8 idx;
> >
> > /*
> > * Avoid calling into the driver (or doing delays) if the chip select
> > * isn't actually changing from the last time this was called.
> > */
> > - if (!force && ((enable && spi->controller->last_cs ==
> spi_get_chipselect(spi, 0)) ||
> > - (!enable && spi->controller->last_cs !=
> spi_get_chipselect(spi, 0))) &&
> > + if (!force && ((enable && spi->controller->last_cs_index_mask == spi-
> >cs_index_mask &&
> > + spi_is_last_cs(spi)) ||
> > + (!enable && spi->controller->last_cs_index_mask == spi-
> >cs_index_mask &&
> > + !spi_is_last_cs(spi))) &&
> > (spi->controller->last_cs_mode_high == (spi->mode &
> SPI_CS_HIGH)))
> > return;
> >
> > trace_spi_set_cs(spi, activate);
> >
> > - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
> > + spi->controller->last_cs_index_mask = spi->cs_index_mask;
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi,
> 0)
> > +: -1;
> > spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
> >
> > - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) &&
> !activate)
> > - spi_delay_exec(&spi->cs_hold, NULL);
> > -
> > if (spi->mode & SPI_CS_HIGH)
> > enable = !enable;
> >
> > - if (spi_get_csgpiod(spi, 0)) {
> > + if (spi_is_csgpiod(spi)) {
> > + if (!spi->controller->set_cs_timing && !activate)
> > + spi_delay_exec(&spi->cs_hold, NULL);
> > +
> > if (!(spi->mode & SPI_NO_CS)) {
> > /*
> > * Historically ACPI has no means of the GPIO polarity
> and @@
> > -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi, bool
> enable, bool force)
> > * ambiguity. That's why we use enable, that takes
> SPI_CS_HIGH
> > * into account.
> > */
> > - if (has_acpi_companion(&spi->dev))
> > -
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> > - else
> > - /* Polarity handled by GPIO library */
> > -
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + if (((spi->cs_index_mask >> idx) & 0x01) &&
> > + spi_get_csgpiod(spi, idx)) {
> > + if (has_acpi_companion(&spi->dev))
> > +
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> > +
> !enable);
> > + else
> > + /* Polarity handled by GPIO
> library */
> > +
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> > +
> activate);
> > +
> > + if (activate)
> > + spi_delay_exec(&spi-
> >cs_setup, NULL);
> > + else
> > + spi_delay_exec(&spi-
> >cs_inactive, NULL);
> > + }
> > + }
> > }
> > /* Some SPI masters need both GPIO CS & slave_select */
> > if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
> > spi->controller->set_cs)
> > spi->controller->set_cs(spi, !enable);
> > +
> > + if (!spi->controller->set_cs_timing) {
> > + if (activate)
> > + spi_delay_exec(&spi->cs_setup, NULL);
> > + else
> > + spi_delay_exec(&spi->cs_inactive, NULL);
> > + }
> > } else if (spi->controller->set_cs) {
> > spi->controller->set_cs(spi, !enable);
> > }
> > -
> > - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
> > - if (activate)
> > - spi_delay_exec(&spi->cs_setup, NULL);
> > - else
> > - spi_delay_exec(&spi->cs_inactive, NULL);
> > - }
> > }
> >
> > #ifdef CONFIG_HAS_DMA
> > @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct
> device_node *nc,
> > static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> > struct device_node *nc)
> > {
> > - u32 value;
> > - int rc;
> > + u32 value, cs[SPI_CS_CNT_MAX];
> > + int rc, idx;
> >
> > /* Mode (clock phase/polarity/etc.) */
> > if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14 +2363,52
> @@
> > static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> > return 0;
> > }
> >
> > + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
> > + dev_err(&ctlr->dev, "No. of CS is more than max. no. of
> supported CS\n");
> > + return -EINVAL;
> > + }
> > +
> > + /*
> > + * Zero(0) is a valid physical CS value and can be located at any
> > + * logical CS in the spi->chip_select[]. If all the physical CS
> > + * are initialized to 0 then It would be difficult to differentiate
> > + * between a valid physical CS 0 & an unused logical CS whose
> physical
> > + * CS can be 0. As a solution to this issue initialize all the CS to 0xFF.
> > + * Now all the unused logical CS will have 0xFF physical CS value & can
> be
> > + * ignore while performing physical CS validity checks.
> > + */
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + spi_set_chipselect(spi, idx, 0xFF);
> > +
> > /* Device address */
> > - rc = of_property_read_u32(nc, "reg", &value);
> > - if (rc) {
> > + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> > + SPI_CS_CNT_MAX);
> > + if (rc < 0) {
> > dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> (%d)\n",
> > nc, rc);
> > return rc;
> > }
> > - spi_set_chipselect(spi, 0, value);
> > + if (rc > ctlr->num_chipselect) {
> > + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
> >num_chipselect (%d)\n",
> > + nc, rc);
> > + return rc;
> > + }
> > + if ((of_property_read_bool(nc, "parallel-memories")) &&
> > + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> > + dev_err(&ctlr->dev, "SPI controller doesn't support multi
> CS\n");
> > + return -EINVAL;
> > + }
> > + for (idx = 0; idx < rc; idx++)
> > + spi_set_chipselect(spi, idx, cs[idx]);
> > +
> > + /* spi->chip_select[i] gives the corresponding physical CS for logical CS
> i
> > + * logical CS number is represented by setting the ith bit in spi-
> >cs_index_mask
> > + * So, for example, if spi->cs_index_mask = 0x01 then logical CS
> number is 0 and
> > + * spi->chip_select[0] will give the physical CS.
> > + * By default spi->chip_select[0] will hold the physical CS number so,
> set
> > + * spi->cs_index_mask as 0x01.
> > + */
> > + spi->cs_index_mask = 0x01;
> >
> > /* Device speed */
> > if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
> > -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller *ctlr)
> > struct boardinfo *bi;
> > int first_dynamic;
> > int status;
> > + int idx;
> >
> > if (!dev)
> > return -ENODEV;
> > @@ -3164,7 +3271,8 @@ int spi_register_controller(struct spi_controller
> *ctlr)
> > }
> >
> > /* Setting last_cs to -1 means no chip selected */
> > - ctlr->last_cs = -1;
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + ctlr->last_cs[idx] = -1;
> >
> > status = device_add(&ctlr->dev);
> > if (status < 0)
> > @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device *spi,
> struct spi_message *message)
> > * cs_change is set for each transfer.
> > */
> > if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> SPI_CS_WORD) ||
> > - spi_get_csgpiod(spi, 0))) {
> > + spi_is_csgpiod(spi))) {
> > size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
> > int ret;
> >
> > diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> > 7b4baff63c5c..871d3a6d879b 100644
> > --- a/include/linux/spi/spi.h
> > +++ b/include/linux/spi/spi.h
> > @@ -20,6 +20,9 @@
> >
> > #include <uapi/linux/spi/spi.h>
> >
> > +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 4
> > +
> > struct dma_chan;
> > struct software_node;
> > struct ptp_system_timestamp;
> > @@ -132,7 +135,8 @@ extern void
> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > * @max_speed_hz: Maximum clock rate to be used with this chip
> > * (on this board); may be changed by the device's driver.
> > * The spi_transfer.speed_hz can override this for each transfer.
> > - * @chip_select: Chipselect, distinguishing chips handled by @controller.
> > + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
> > + * the corresponding physical CS for logical CS i.
> > * @mode: The spi mode defines how data is clocked out and in.
> > * This may be changed by the device's driver.
> > * The "active low" default for chipselect mode can be overridden
> > @@ -157,8 +161,8 @@ extern void
> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > * the device will bind to the named driver and only the named driver.
> > * Do not set directly, because core frees it; use driver_set_override() to
> > * set or clear it.
> > - * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL when
> > - * not using a GPIO line)
> > + * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect
> lines
> > + * (optional, NULL when not using a GPIO line)
> > * @word_delay: delay to be inserted between consecutive
> > * words of a transfer
> > * @cs_setup: delay to be introduced by the controller after CS is
> > asserted @@ -167,6 +171,7 @@ extern void
> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > * deasserted. If @cs_change_delay is used from @spi_transfer, then
> the
> > * two delays will be added up.
> > * @pcpu_statistics: statistics for the spi_device
> > + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> > + chipselect array
> > *
> > * A @spi_device is used to interchange data between an SPI slave
> > * (usually a discrete chip) and CPU memory.
> > @@ -182,7 +187,7 @@ struct spi_device {
> > struct spi_controller *controller;
> > struct spi_controller *master; /* Compatibility layer */
> > u32 max_speed_hz;
> > - u8 chip_select;
> > + u8 chip_select[SPI_CS_CNT_MAX];
> > u8 bits_per_word;
> > bool rt;
> > #define SPI_NO_TX BIT(31) /* No transmit wire */
> > @@ -213,7 +218,7 @@ struct spi_device {
> > void *controller_data;
> > char modalias[SPI_NAME_SIZE];
> > const char *driver_override;
> > - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor
> */
> > + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select
> gpio desc */
> > struct spi_delay word_delay; /* Inter-word delay */
> > /* CS delays */
> > struct spi_delay cs_setup;
> > @@ -223,6 +228,13 @@ struct spi_device {
> > /* The statistics */
> > struct spi_statistics __percpu *pcpu_statistics;
> >
> > + /* Bit mask of the chipselect(s) that the driver need to use from
> > + * the chipselect array.When the controller is capable to handle
> > + * multiple chip selects & memories are connected in parallel
> > + * then more than one bit need to be set in cs_index_mask.
> > + */
> > + u32 cs_index_mask : SPI_CS_CNT_MAX;
> > +
> > /*
> > * Likely need more hooks for more protocol options affecting how
> > * the controller talks to each chip, like:
> > @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const struct
> > spi_device *spi)
> >
> > static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
> > {
> > - return spi->chip_select;
> > + return spi->chip_select[idx];
> > }
> >
> > static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8
> chipselect)
> > {
> > - spi->chip_select = chipselect;
> > + spi->chip_select[idx] = chipselect;
> > }
> >
> > static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi,
> u8 idx)
> > {
> > - return spi->cs_gpiod;
> > + return spi->cs_gpiod[idx];
> > }
> >
> > static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct
> gpio_desc *csgpiod)
> > {
> > - spi->cs_gpiod = csgpiod;
> > + spi->cs_gpiod[idx] = csgpiod;
> > +}
> > +
> > +static inline bool spi_is_csgpiod(struct spi_device *spi) {
> > + u8 idx;
> > +
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + if (spi_get_csgpiod(spi, idx))
> > + return true;
> > + }
> > + return false;
> > }
> >
> > /**
> > @@ -399,6 +422,8 @@ extern struct spi_device
> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> > * @bus_lock_spinlock: spinlock for SPI bus locking
> > * @bus_lock_mutex: mutex for exclusion of multiple callers
> > * @bus_lock_flag: indicates that the SPI bus is locked for
> > exclusive use
> > + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
> > + * more than one chip select at once.
> > * @setup: updates the device mode and clocking records used by a
> > * device's SPI controller; protocol code may call this. This
> > * must fail if an unrecognized or unsupported mode is requested.
> > @@ -567,6 +592,11 @@ struct spi_controller {
> > #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
> > #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must
> select slave */
> > #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
> suspended */
> > + /*
> > + * The spi-controller has multi chip select capability and can
> > + * assert/de-assert more than one chip select at once.
> > + */
> > +#define SPI_CONTROLLER_MULTI_CS BIT(7)
> >
> > /* Flag indicating if the allocation of this struct is devres-managed */
> > bool devm_allocated;
> > @@ -677,7 +707,8 @@ struct spi_controller {
> > bool rt;
> > bool auto_runtime_pm;
> > bool cur_msg_mapped;
> > - char last_cs;
> > + char last_cs[SPI_CS_CNT_MAX];
> > + char last_cs_index_mask;
> > bool last_cs_mode_high;
> > bool fallback;
> > struct completion xfer_completion;
On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Monday, November 20, 2023 8:00 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>; linux-
>> [email protected]; git (AMD-Xilinx) <[email protected]>;
>> [email protected]; [email protected]
>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>>
>>
>> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
>>> AMD-Xilinx GQSPI controller has two advanced mode that allows the
>>> controller to consider two flashes as one single device.
>>>
>>> One of these two mode is the parallel mode in which each byte of data
>>> is stored in both devices, the even bits in the lower flash & the odd
>>> bits in the upper flash. The byte split is automatically handled by
>>> the QSPI controller.
>>>
>>> The other mode is the stacked mode in which both the flashes share the
>>> same SPI bus but each of the device contain half of the data. In this
>>> mode, the controller does not follow CS requests but instead
>>> internally wires the two CS levels with the value of the most significant
>> address bit.
>>> For supporting both these modes SPI core need to be updated for
>>> providing multiple CS for a single SPI device.
>>>
>>> For adding multi CS support the SPI device need to be aware of all the
>>> CS values. So, the "chip_select" member in the spi_device structure is
>>> now an array that holds all the CS values.
>>>
>>> spi_device structure now has a "cs_index_mask" member. This acts as an
>>> index to the chip_select array. If nth bit of spi->cs_index_mask is
>>> set then the driver would assert spi->chip_select[n].
>>>
>>> In parallel mode all the chip selects are asserted/de-asserted
>>> simultaneously and each byte of data is stored in both devices, the
>>> even bits in one, the odd bits in the other. The split is
>>> automatically handled by the GQSPI controller. The GQSPI controller
>>> supports a maximum of two flashes connected in parallel mode. A
>>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi controller flags,
>>> through ctlr->flags the spi core will make sure that the controller is
>>> capable of handling multiple chip selects at once.
>>>
>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>> spi_device structure is now an array that holds the gpio descriptor
>>> for each chipselect.
>>>
>>> CS GPIO is not tested due to unavailability of necessary hardware setup.
>>>
>>> Signed-off-by: Amit Kumar Mahapatra <[email protected]>
>>> ---
>>> Hello @Stefen,
>>> We restructured the SPI core implementation, for handling arbitrary
>>> number of devices connected in parallel(multi-cs) or stacked mode. We
>>> have tested this updated patch on native-cs setup but couldn't test
>>> cs-gpio due to unavailability of a proper setup. If possible, could
>>> you please retest the cs-gpio use case with this updated patch and provide
>> your feedback.
>>
>> Hi,
>>
>> I tested this chain on 2 different systems using GPIOs as chip selects, and see
>> the same error on both:
>> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
>>
>> Let me know if you need any further testing.
>>
>> Thanks,
>>
>> Stefan Binding
>>
>>> ---
>>> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---------
>>> include/linux/spi/spi.h | 51 ++++++++---
>>> 2 files changed, 191 insertions(+), 52 deletions(-)
>>>
>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>> 8ead7acb99f3..ff66147ba95f 100644
>>> --- a/drivers/spi/spi.c
>>> +++ b/drivers/spi/spi.c
>>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev, void
>> *data)
>>> {
>>> struct spi_device *spi = to_spi_device(dev);
>>> struct spi_device *new_spi = data;
>>> -
>>> - if (spi->controller == new_spi->controller &&
>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
>>> - return -EBUSY;
>>> + int idx, nw_idx;
>>> + u8 cs, cs_nw;
>>> +
>>> + if (spi->controller == new_spi->controller) {
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + cs = spi_get_chipselect(spi, idx);
>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>> nw_idx++) {
>>> + cs_nw = spi_get_chipselect(spi, nw_idx);
> Thank you for dedicating your time to test my patch.
> As per my analysis the error is reported from here as we are
> supplying the former SPI device structure to retrieve the CS
> value for the new SPI devices.
> To fix this, could you kindly substitute the above line with
>
> cs_nw = spi_get_chipselect(new_spi, nw_idx);
>
> and rerun your tests?
> If it works correctly, I will incorporate this fix into my
> upcoming series.
>
> Regards,
> Amit
Hi,
I still see the same error:
[Â Â Â 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
Thanks,
Stefan
>
>>> + if (cs != 0xFF && cs_nw != 0xFF && cs ==
>> cs_nw) {
>>> + dev_err(dev, "chipselect %d already in
>> use\n", cs_nw);
>>> + return -EBUSY;
>>> + }
>>> + }
>>> + }
>>> + }
>>> return 0;
>>> }
>>>
>>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct spi_device *spi)
>>> {
>>> struct spi_controller *ctlr = spi->controller;
>>> struct device *dev = ctlr->dev.parent;
>>> - int status;
>>> + int status, idx, nw_idx;
>>> + u8 cs, nw_cs;
>>> +
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + /* Chipselects are numbered 0..max; validate. */
>>> + cs = spi_get_chipselect(spi, idx);
>>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
>>> + dev_err(dev, "cs%d >= max %d\n",
>> spi_get_chipselect(spi, idx),
>>> + ctlr->num_chipselect);
>>> + return -EINVAL;
>>> + }
>>> + }
>>>
>>> - /* Chipselects are numbered 0..max; validate. */
>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>> - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
>>> - ctlr->num_chipselect);
>>> - return -EINVAL;
>>> + /*
>>> + * Make sure that multiple logical CS doesn't map to the same
>> physical CS.
>>> + * For example, spi->chip_select[0] != spi->chip_select[1] and so on.
>>> + */
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + cs = spi_get_chipselect(spi, idx);
>>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
>>> + nw_cs = spi_get_chipselect(spi, nw_idx);
>>> + if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
>>> + dev_err(dev, "chipselect %d already in use\n",
>> nw_cs);
>>> + return -EBUSY;
>>> + }
>>> + }
>>> }
>>>
>>> /* Set the bus ID string */
>>> @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device *spi)
>>> * its configuration.
>>> */
>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
>>> - if (status) {
>>> - dev_err(dev, "chipselect %d already in use\n",
>>> - spi_get_chipselect(spi, 0));
>>> + if (status)
>>> return status;
>>> - }
>>>
>>> /* Controller may unregister concurrently */
>>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8 +686,15 @@
>> static
>>> int __spi_add_device(struct spi_device *spi)
>>> return -ENODEV;
>>> }
>>>
>>> - if (ctlr->cs_gpiods)
>>> - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi,
>> 0)]);
>>> + if (ctlr->cs_gpiods) {
>>> + u8 cs;
>>> +
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + cs = spi_get_chipselect(spi, idx);
>>> + if (cs != 0xFF)
>>> + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]);
>>> + }
>>> + }
>>>
>>> /*
>>> * Drivers may modify this initial i/o setup, but will @@ -701,6
>>> +735,9 @@ int spi_add_device(struct spi_device *spi)
>>> struct spi_controller *ctlr = spi->controller;
>>> int status;
>>>
>>> + /* Set the bus ID string */
>>> + spi_dev_set_name(spi);
>>> +
>>> mutex_lock(&ctlr->add_lock);
>>> status = __spi_add_device(spi);
>>> mutex_unlock(&ctlr->add_lock);
>>> @@ -942,32 +979,51 @@ static void spi_res_release(struct spi_controller
>> *ctlr, struct spi_message *mes
>>> }
>>>
>>>
>>> /*--------------------------------------------------------------------
>>> -----*/
>>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
>>> + u8 idx;
>>> + bool last = false;
>>> +
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + if ((spi->cs_index_mask >> idx) & 0x01) {
>>> + if (spi->controller->last_cs[idx] ==
>> spi_get_chipselect(spi, idx))
>>> + last = true;
>>> + }
>>> + }
>>> + return last;
>>> +}
>>> +
>>>
>>> static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
>>> {
>>> bool activate = enable;
>>> + u8 idx;
>>>
>>> /*
>>> * Avoid calling into the driver (or doing delays) if the chip select
>>> * isn't actually changing from the last time this was called.
>>> */
>>> - if (!force && ((enable && spi->controller->last_cs ==
>> spi_get_chipselect(spi, 0)) ||
>>> - (!enable && spi->controller->last_cs !=
>> spi_get_chipselect(spi, 0))) &&
>>> + if (!force && ((enable && spi->controller->last_cs_index_mask == spi-
>>> cs_index_mask &&
>>> + spi_is_last_cs(spi)) ||
>>> + (!enable && spi->controller->last_cs_index_mask == spi-
>>> cs_index_mask &&
>>> + !spi_is_last_cs(spi))) &&
>>> (spi->controller->last_cs_mode_high == (spi->mode &
>> SPI_CS_HIGH)))
>>> return;
>>>
>>> trace_spi_set_cs(spi, activate);
>>>
>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
>>> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> + spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi,
>> 0)
>>> +: -1;
>>> spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
>>>
>>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) &&
>> !activate)
>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>> -
>>> if (spi->mode & SPI_CS_HIGH)
>>> enable = !enable;
>>>
>>> - if (spi_get_csgpiod(spi, 0)) {
>>> + if (spi_is_csgpiod(spi)) {
>>> + if (!spi->controller->set_cs_timing && !activate)
>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>> +
>>> if (!(spi->mode & SPI_NO_CS)) {
>>> /*
>>> * Historically ACPI has no means of the GPIO polarity
>> and @@
>>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi, bool
>> enable, bool force)
>>> * ambiguity. That's why we use enable, that takes
>> SPI_CS_HIGH
>>> * into account.
>>> */
>>> - if (has_acpi_companion(&spi->dev))
>>> -
>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>> - else
>>> - /* Polarity handled by GPIO library */
>>> -
>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + if (((spi->cs_index_mask >> idx) & 0x01) &&
>>> + spi_get_csgpiod(spi, idx)) {
>>> + if (has_acpi_companion(&spi->dev))
>>> +
>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>> +
>> !enable);
>>> + else
>>> + /* Polarity handled by GPIO
>> library */
>>> +
>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>> +
>> activate);
>>> +
>>> + if (activate)
>>> + spi_delay_exec(&spi-
>>> cs_setup, NULL);
>>> + else
>>> + spi_delay_exec(&spi-
>>> cs_inactive, NULL);
>>> + }
>>> + }
>>> }
>>> /* Some SPI masters need both GPIO CS & slave_select */
>>> if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
>>> spi->controller->set_cs)
>>> spi->controller->set_cs(spi, !enable);
>>> +
>>> + if (!spi->controller->set_cs_timing) {
>>> + if (activate)
>>> + spi_delay_exec(&spi->cs_setup, NULL);
>>> + else
>>> + spi_delay_exec(&spi->cs_inactive, NULL);
>>> + }
>>> } else if (spi->controller->set_cs) {
>>> spi->controller->set_cs(spi, !enable);
>>> }
>>> -
>>> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
>>> - if (activate)
>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>> - else
>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>> - }
>>> }
>>>
>>> #ifdef CONFIG_HAS_DMA
>>> @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct
>> device_node *nc,
>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>>> struct device_node *nc)
>>> {
>>> - u32 value;
>>> - int rc;
>>> + u32 value, cs[SPI_CS_CNT_MAX];
>>> + int rc, idx;
>>>
>>> /* Mode (clock phase/polarity/etc.) */
>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14 +2363,52
>> @@
>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>>> return 0;
>>> }
>>>
>>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
>>> + dev_err(&ctlr->dev, "No. of CS is more than max. no. of
>> supported CS\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + /*
>>> + * Zero(0) is a valid physical CS value and can be located at any
>>> + * logical CS in the spi->chip_select[]. If all the physical CS
>>> + * are initialized to 0 then It would be difficult to differentiate
>>> + * between a valid physical CS 0 & an unused logical CS whose
>> physical
>>> + * CS can be 0. As a solution to this issue initialize all the CS to 0xFF.
>>> + * Now all the unused logical CS will have 0xFF physical CS value & can
>> be
>>> + * ignore while performing physical CS validity checks.
>>> + */
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> + spi_set_chipselect(spi, idx, 0xFF);
>>> +
>>> /* Device address */
>>> - rc = of_property_read_u32(nc, "reg", &value);
>>> - if (rc) {
>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
>>> + SPI_CS_CNT_MAX);
>>> + if (rc < 0) {
>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>> (%d)\n",
>>> nc, rc);
>>> return rc;
>>> }
>>> - spi_set_chipselect(spi, 0, value);
>>> + if (rc > ctlr->num_chipselect) {
>>> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
>>> num_chipselect (%d)\n",
>>> + nc, rc);
>>> + return rc;
>>> + }
>>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>> + dev_err(&ctlr->dev, "SPI controller doesn't support multi
>> CS\n");
>>> + return -EINVAL;
>>> + }
>>> + for (idx = 0; idx < rc; idx++)
>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>> +
>>> + /* spi->chip_select[i] gives the corresponding physical CS for logical CS
>> i
>>> + * logical CS number is represented by setting the ith bit in spi-
>>> cs_index_mask
>>> + * So, for example, if spi->cs_index_mask = 0x01 then logical CS
>> number is 0 and
>>> + * spi->chip_select[0] will give the physical CS.
>>> + * By default spi->chip_select[0] will hold the physical CS number so,
>> set
>>> + * spi->cs_index_mask as 0x01.
>>> + */
>>> + spi->cs_index_mask = 0x01;
>>>
>>> /* Device speed */
>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
>>> -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller *ctlr)
>>> struct boardinfo *bi;
>>> int first_dynamic;
>>> int status;
>>> + int idx;
>>>
>>> if (!dev)
>>> return -ENODEV;
>>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct spi_controller
>> *ctlr)
>>> }
>>>
>>> /* Setting last_cs to -1 means no chip selected */
>>> - ctlr->last_cs = -1;
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> + ctlr->last_cs[idx] = -1;
>>>
>>> status = device_add(&ctlr->dev);
>>> if (status < 0)
>>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device *spi,
>> struct spi_message *message)
>>> * cs_change is set for each transfer.
>>> */
>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>> SPI_CS_WORD) ||
>>> - spi_get_csgpiod(spi, 0))) {
>>> + spi_is_csgpiod(spi))) {
>>> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
>>> int ret;
>>>
>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
>>> 7b4baff63c5c..871d3a6d879b 100644
>>> --- a/include/linux/spi/spi.h
>>> +++ b/include/linux/spi/spi.h
>>> @@ -20,6 +20,9 @@
>>>
>>> #include <uapi/linux/spi/spi.h>
>>>
>>> +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 4
>>> +
>>> struct dma_chan;
>>> struct software_node;
>>> struct ptp_system_timestamp;
>>> @@ -132,7 +135,8 @@ extern void
>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>> * @max_speed_hz: Maximum clock rate to be used with this chip
>>> * (on this board); may be changed by the device's driver.
>>> * The spi_transfer.speed_hz can override this for each transfer.
>>> - * @chip_select: Chipselect, distinguishing chips handled by @controller.
>>> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
>>> + * the corresponding physical CS for logical CS i.
>>> * @mode: The spi mode defines how data is clocked out and in.
>>> * This may be changed by the device's driver.
>>> * The "active low" default for chipselect mode can be overridden
>>> @@ -157,8 +161,8 @@ extern void
>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>> * the device will bind to the named driver and only the named driver.
>>> * Do not set directly, because core frees it; use driver_set_override() to
>>> * set or clear it.
>>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL when
>>> - * not using a GPIO line)
>>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect
>> lines
>>> + * (optional, NULL when not using a GPIO line)
>>> * @word_delay: delay to be inserted between consecutive
>>> * words of a transfer
>>> * @cs_setup: delay to be introduced by the controller after CS is
>>> asserted @@ -167,6 +171,7 @@ extern void
>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>> * deasserted. If @cs_change_delay is used from @spi_transfer, then
>> the
>>> * two delays will be added up.
>>> * @pcpu_statistics: statistics for the spi_device
>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>> + chipselect array
>>> *
>>> * A @spi_device is used to interchange data between an SPI slave
>>> * (usually a discrete chip) and CPU memory.
>>> @@ -182,7 +187,7 @@ struct spi_device {
>>> struct spi_controller *controller;
>>> struct spi_controller *master; /* Compatibility layer */
>>> u32 max_speed_hz;
>>> - u8 chip_select;
>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>> u8 bits_per_word;
>>> bool rt;
>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>> @@ -213,7 +218,7 @@ struct spi_device {
>>> void *controller_data;
>>> char modalias[SPI_NAME_SIZE];
>>> const char *driver_override;
>>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor
>> */
>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select
>> gpio desc */
>>> struct spi_delay word_delay; /* Inter-word delay */
>>> /* CS delays */
>>> struct spi_delay cs_setup;
>>> @@ -223,6 +228,13 @@ struct spi_device {
>>> /* The statistics */
>>> struct spi_statistics __percpu *pcpu_statistics;
>>>
>>> + /* Bit mask of the chipselect(s) that the driver need to use from
>>> + * the chipselect array.When the controller is capable to handle
>>> + * multiple chip selects & memories are connected in parallel
>>> + * then more than one bit need to be set in cs_index_mask.
>>> + */
>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>> +
>>> /*
>>> * Likely need more hooks for more protocol options affecting how
>>> * the controller talks to each chip, like:
>>> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const struct
>>> spi_device *spi)
>>>
>>> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
>>> {
>>> - return spi->chip_select;
>>> + return spi->chip_select[idx];
>>> }
>>>
>>> static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8
>> chipselect)
>>> {
>>> - spi->chip_select = chipselect;
>>> + spi->chip_select[idx] = chipselect;
>>> }
>>>
>>> static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi,
>> u8 idx)
>>> {
>>> - return spi->cs_gpiod;
>>> + return spi->cs_gpiod[idx];
>>> }
>>>
>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct
>> gpio_desc *csgpiod)
>>> {
>>> - spi->cs_gpiod = csgpiod;
>>> + spi->cs_gpiod[idx] = csgpiod;
>>> +}
>>> +
>>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
>>> + u8 idx;
>>> +
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + if (spi_get_csgpiod(spi, idx))
>>> + return true;
>>> + }
>>> + return false;
>>> }
>>>
>>> /**
>>> @@ -399,6 +422,8 @@ extern struct spi_device
>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>>> exclusive use
>>> + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
>>> + * more than one chip select at once.
>>> * @setup: updates the device mode and clocking records used by a
>>> * device's SPI controller; protocol code may call this. This
>>> * must fail if an unrecognized or unsupported mode is requested.
>>> @@ -567,6 +592,11 @@ struct spi_controller {
>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
>>> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must
>> select slave */
>>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
>> suspended */
>>> + /*
>>> + * The spi-controller has multi chip select capability and can
>>> + * assert/de-assert more than one chip select at once.
>>> + */
>>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
>>>
>>> /* Flag indicating if the allocation of this struct is devres-managed */
>>> bool devm_allocated;
>>> @@ -677,7 +707,8 @@ struct spi_controller {
>>> bool rt;
>>> bool auto_runtime_pm;
>>> bool cur_msg_mapped;
>>> - char last_cs;
>>> + char last_cs[SPI_CS_CNT_MAX];
>>> + char last_cs_index_mask;
>>> bool last_cs_mode_high;
>>> bool fallback;
>>> struct completion xfer_completion;
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Tuesday, November 21, 2023 7:28 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>; linux-
> [email protected]; git (AMD-Xilinx) <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>
>
> On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
> > Hello Stefan,
> >
> >> -----Original Message-----
> >> From: Stefan Binding <[email protected]>
> >> Sent: Monday, November 20, 2023 8:00 PM
> >> To: Mahapatra, Amit Kumar <[email protected]>;
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected]
> >> Cc: [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Simek, Michal <[email protected]>;
> >> linux- [email protected]; git (AMD-Xilinx)
> >> <[email protected]>; [email protected];
> >> [email protected]
> >> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> >> SPI core
> >>
> >>
> >> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
> >>> AMD-Xilinx GQSPI controller has two advanced mode that allows the
> >>> controller to consider two flashes as one single device.
> >>>
> >>> One of these two mode is the parallel mode in which each byte of
> >>> data is stored in both devices, the even bits in the lower flash &
> >>> the odd bits in the upper flash. The byte split is automatically
> >>> handled by the QSPI controller.
> >>>
> >>> The other mode is the stacked mode in which both the flashes share
> >>> the same SPI bus but each of the device contain half of the data. In
> >>> this mode, the controller does not follow CS requests but instead
> >>> internally wires the two CS levels with the value of the most
> >>> significant
> >> address bit.
> >>> For supporting both these modes SPI core need to be updated for
> >>> providing multiple CS for a single SPI device.
> >>>
> >>> For adding multi CS support the SPI device need to be aware of all
> >>> the CS values. So, the "chip_select" member in the spi_device
> >>> structure is now an array that holds all the CS values.
> >>>
> >>> spi_device structure now has a "cs_index_mask" member. This acts as
> >>> an index to the chip_select array. If nth bit of spi->cs_index_mask
> >>> is set then the driver would assert spi->chip_select[n].
> >>>
> >>> In parallel mode all the chip selects are asserted/de-asserted
> >>> simultaneously and each byte of data is stored in both devices, the
> >>> even bits in one, the odd bits in the other. The split is
> >>> automatically handled by the GQSPI controller. The GQSPI controller
> >>> supports a maximum of two flashes connected in parallel mode. A
> >>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi controller
> >>> flags, through ctlr->flags the spi core will make sure that the
> >>> controller is capable of handling multiple chip selects at once.
> >>>
> >>> For supporting multiple CS via GPIO the cs_gpiod member of the
> >>> spi_device structure is now an array that holds the gpio descriptor
> >>> for each chipselect.
> >>>
> >>> CS GPIO is not tested due to unavailability of necessary hardware setup.
> >>>
> >>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> [email protected]>
> >>> ---
> >>> Hello @Stefen,
> >>> We restructured the SPI core implementation, for handling arbitrary
> >>> number of devices connected in parallel(multi-cs) or stacked mode.
> >>> We have tested this updated patch on native-cs setup but couldn't
> >>> test cs-gpio due to unavailability of a proper setup. If possible,
> >>> could you please retest the cs-gpio use case with this updated patch
> >>> and provide
> >> your feedback.
> >>
> >> Hi,
> >>
> >> I tested this chain on 2 different systems using GPIOs as chip
> >> selects, and see the same error on both:
> >> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
> >>
> >> Let me know if you need any further testing.
> >>
> >> Thanks,
> >>
> >> Stefan Binding
> >>
> >>> ---
> >>> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---------
> >>> include/linux/spi/spi.h | 51 ++++++++---
> >>> 2 files changed, 191 insertions(+), 52 deletions(-)
> >>>
> >>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>> 8ead7acb99f3..ff66147ba95f 100644
> >>> --- a/drivers/spi/spi.c
> >>> +++ b/drivers/spi/spi.c
> >>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev,
> >>> void
> >> *data)
> >>> {
> >>> struct spi_device *spi = to_spi_device(dev);
> >>> struct spi_device *new_spi = data;
> >>> -
> >>> - if (spi->controller == new_spi->controller &&
> >>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
> >>> - return -EBUSY;
> >>> + int idx, nw_idx;
> >>> + u8 cs, cs_nw;
> >>> +
> >>> + if (spi->controller == new_spi->controller) {
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + cs = spi_get_chipselect(spi, idx);
> >>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> >> nw_idx++) {
> >>> + cs_nw = spi_get_chipselect(spi, nw_idx);
> > Thank you for dedicating your time to test my patch.
> > As per my analysis the error is reported from here as we are supplying
> > the former SPI device structure to retrieve the CS value for the new
> > SPI devices.
> > To fix this, could you kindly substitute the above line with
> >
> > cs_nw = spi_get_chipselect(new_spi, nw_idx);
> >
> > and rerun your tests?
> > If it works correctly, I will incorporate this fix into my upcoming
> > series.
> >
> > Regards,
> > Amit
>
> Hi,
>
> I still see the same error:
>
> [Â Â Â 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
Thank you for the quick testing. For further analysis I have incorporated
additional debug prints on top of 1/8 patch. The corresponding diff is
shared below. Kindly implement the specified changes, rerun your test and
share the kernel logs.
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ff66147ba95f..7f59ea81593d 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -618,8 +618,10 @@ static int spi_dev_check(struct device *dev, void *data)
if (spi->controller == new_spi->controller) {
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
cs = spi_get_chipselect(spi, idx);
+ printk("%s() [%d] CS[%d] = [%d]\n", __func__, __LINE__, idx, cs);
for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
- cs_nw = spi_get_chipselect(spi, nw_idx);
+ cs_nw = spi_get_chipselect(new_spi, nw_idx);
+ printk("%s() [%d] CS_NEW[%d] = [%d]\n", __func__, __LINE__, nw_idx, cs_nw);
if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
dev_err(dev, "chipselect %d already in use\n", cs_nw);
return -EBUSY;
@@ -659,8 +661,10 @@ static int __spi_add_device(struct spi_device *spi)
*/
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
cs = spi_get_chipselect(spi, idx);
+ printk("%s() [%d] CS[%d] = [%d]\n", __func__, __LINE__, idx, cs);
for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
nw_cs = spi_get_chipselect(spi, nw_idx);
+ printk("%s() [%d] CS_NEW[%d] = [%d]\n", __func__, __LINE__, nw_idx, nw_cs);
if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
dev_err(dev, "chipselect %d already in use\n", nw_cs);
return -EBUSY;
@@ -2401,6 +2405,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
for (idx = 0; idx < rc; idx++)
spi_set_chipselect(spi, idx, cs[idx]);
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ printk("%s() [%d] CS[%d] = [%d]\n", __func__, __LINE__, idx, spi_get_chipselect(spi, idx));
+
/* spi->chip_select[i] gives the corresponding physical CS for logical CS i
* logical CS number is represented by setting the ith bit in spi->cs_index_mask
* So, for example, if spi->cs_index_mask = 0x01 then logical CS number is 0 and
Regards,
Amit
>
> Thanks,
>
> Stefan
>
> >
> >>> + if (cs != 0xFF && cs_nw != 0xFF && cs ==
> >> cs_nw) {
> >>> + dev_err(dev, "chipselect %d already in
> >> use\n", cs_nw);
> >>> + return -EBUSY;
> >>> + }
> >>> + }
> >>> + }
> >>> + }
> >>> return 0;
> >>> }
> >>>
> >>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct spi_device
> *spi)
> >>> {
> >>> struct spi_controller *ctlr = spi->controller;
> >>> struct device *dev = ctlr->dev.parent;
> >>> - int status;
> >>> + int status, idx, nw_idx;
> >>> + u8 cs, nw_cs;
> >>> +
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + /* Chipselects are numbered 0..max; validate. */
> >>> + cs = spi_get_chipselect(spi, idx);
> >>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
> >>> + dev_err(dev, "cs%d >= max %d\n",
> >> spi_get_chipselect(spi, idx),
> >>> + ctlr->num_chipselect);
> >>> + return -EINVAL;
> >>> + }
> >>> + }
> >>>
> >>> - /* Chipselects are numbered 0..max; validate. */
> >>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>> - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
> >>> - ctlr->num_chipselect);
> >>> - return -EINVAL;
> >>> + /*
> >>> + * Make sure that multiple logical CS doesn't map to the same
> >> physical CS.
> >>> + * For example, spi->chip_select[0] != spi->chip_select[1] and so on.
> >>> + */
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + cs = spi_get_chipselect(spi, idx);
> >>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> >>> + nw_cs = spi_get_chipselect(spi, nw_idx);
> >>> + if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> >>> + dev_err(dev, "chipselect %d already in use\n",
> >> nw_cs);
> >>> + return -EBUSY;
> >>> + }
> >>> + }
> >>> }
> >>>
> >>> /* Set the bus ID string */
> >>> @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device
> *spi)
> >>> * its configuration.
> >>> */
> >>> status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
> >>> - if (status) {
> >>> - dev_err(dev, "chipselect %d already in use\n",
> >>> - spi_get_chipselect(spi, 0));
> >>> + if (status)
> >>> return status;
> >>> - }
> >>>
> >>> /* Controller may unregister concurrently */
> >>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8 +686,15 @@
> >> static
> >>> int __spi_add_device(struct spi_device *spi)
> >>> return -ENODEV;
> >>> }
> >>>
> >>> - if (ctlr->cs_gpiods)
> >>> - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi,
> >> 0)]);
> >>> + if (ctlr->cs_gpiods) {
> >>> + u8 cs;
> >>> +
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + cs = spi_get_chipselect(spi, idx);
> >>> + if (cs != 0xFF)
> >>> + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]);
> >>> + }
> >>> + }
> >>>
> >>> /*
> >>> * Drivers may modify this initial i/o setup, but will @@ -701,6
> >>> +735,9 @@ int spi_add_device(struct spi_device *spi)
> >>> struct spi_controller *ctlr = spi->controller;
> >>> int status;
> >>>
> >>> + /* Set the bus ID string */
> >>> + spi_dev_set_name(spi);
> >>> +
> >>> mutex_lock(&ctlr->add_lock);
> >>> status = __spi_add_device(spi);
> >>> mutex_unlock(&ctlr->add_lock);
> >>> @@ -942,32 +979,51 @@ static void spi_res_release(struct
> >>> spi_controller
> >> *ctlr, struct spi_message *mes
> >>> }
> >>>
> >>>
> >>> /*------------------------------------------------------------------
> >>> --
> >>> -----*/
> >>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
> >>> + u8 idx;
> >>> + bool last = false;
> >>> +
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + if ((spi->cs_index_mask >> idx) & 0x01) {
> >>> + if (spi->controller->last_cs[idx] ==
> >> spi_get_chipselect(spi, idx))
> >>> + last = true;
> >>> + }
> >>> + }
> >>> + return last;
> >>> +}
> >>> +
> >>>
> >>> static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
> >>> {
> >>> bool activate = enable;
> >>> + u8 idx;
> >>>
> >>> /*
> >>> * Avoid calling into the driver (or doing delays) if the chip select
> >>> * isn't actually changing from the last time this was called.
> >>> */
> >>> - if (!force && ((enable && spi->controller->last_cs ==
> >> spi_get_chipselect(spi, 0)) ||
> >>> - (!enable && spi->controller->last_cs !=
> >> spi_get_chipselect(spi, 0))) &&
> >>> + if (!force && ((enable && spi->controller->last_cs_index_mask ==
> >>> +spi-
> >>> cs_index_mask &&
> >>> + spi_is_last_cs(spi)) ||
> >>> + (!enable && spi->controller->last_cs_index_mask == spi-
> >>> cs_index_mask &&
> >>> + !spi_is_last_cs(spi))) &&
> >>> (spi->controller->last_cs_mode_high == (spi->mode &
> >> SPI_CS_HIGH)))
> >>> return;
> >>>
> >>> trace_spi_set_cs(spi, activate);
> >>>
> >>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
> >>> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>> + spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi,
> >> 0)
> >>> +: -1;
> >>> spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
> >>>
> >>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) &&
> >> !activate)
> >>> - spi_delay_exec(&spi->cs_hold, NULL);
> >>> -
> >>> if (spi->mode & SPI_CS_HIGH)
> >>> enable = !enable;
> >>>
> >>> - if (spi_get_csgpiod(spi, 0)) {
> >>> + if (spi_is_csgpiod(spi)) {
> >>> + if (!spi->controller->set_cs_timing && !activate)
> >>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>> +
> >>> if (!(spi->mode & SPI_NO_CS)) {
> >>> /*
> >>> * Historically ACPI has no means of the GPIO polarity
> >> and @@
> >>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi,
> >>> bool
> >> enable, bool force)
> >>> * ambiguity. That's why we use enable, that takes
> >> SPI_CS_HIGH
> >>> * into account.
> >>> */
> >>> - if (has_acpi_companion(&spi->dev))
> >>> -
> >> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> >>> - else
> >>> - /* Polarity handled by GPIO library */
> >>> -
> >> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + if (((spi->cs_index_mask >> idx) & 0x01) &&
> >>> + spi_get_csgpiod(spi, idx)) {
> >>> + if (has_acpi_companion(&spi->dev))
> >>> +
> >> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>> +
> >> !enable);
> >>> + else
> >>> + /* Polarity handled by GPIO
> >> library */
> >>> +
> >> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>> +
> >> activate);
> >>> +
> >>> + if (activate)
> >>> + spi_delay_exec(&spi-
> >>> cs_setup, NULL);
> >>> + else
> >>> + spi_delay_exec(&spi-
> >>> cs_inactive, NULL);
> >>> + }
> >>> + }
> >>> }
> >>> /* Some SPI masters need both GPIO CS & slave_select */
> >>> if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
> >>> spi->controller->set_cs)
> >>> spi->controller->set_cs(spi, !enable);
> >>> +
> >>> + if (!spi->controller->set_cs_timing) {
> >>> + if (activate)
> >>> + spi_delay_exec(&spi->cs_setup, NULL);
> >>> + else
> >>> + spi_delay_exec(&spi->cs_inactive, NULL);
> >>> + }
> >>> } else if (spi->controller->set_cs) {
> >>> spi->controller->set_cs(spi, !enable);
> >>> }
> >>> -
> >>> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
> >>> - if (activate)
> >>> - spi_delay_exec(&spi->cs_setup, NULL);
> >>> - else
> >>> - spi_delay_exec(&spi->cs_inactive, NULL);
> >>> - }
> >>> }
> >>>
> >>> #ifdef CONFIG_HAS_DMA
> >>> @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct
> >> device_node *nc,
> >>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device
> *spi,
> >>> struct device_node *nc)
> >>> {
> >>> - u32 value;
> >>> - int rc;
> >>> + u32 value, cs[SPI_CS_CNT_MAX];
> >>> + int rc, idx;
> >>>
> >>> /* Mode (clock phase/polarity/etc.) */
> >>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14 +2363,52
> >> @@
> >>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> >>> return 0;
> >>> }
> >>>
> >>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
> >>> + dev_err(&ctlr->dev, "No. of CS is more than max. no. of
> >> supported CS\n");
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> + /*
> >>> + * Zero(0) is a valid physical CS value and can be located at any
> >>> + * logical CS in the spi->chip_select[]. If all the physical CS
> >>> + * are initialized to 0 then It would be difficult to differentiate
> >>> + * between a valid physical CS 0 & an unused logical CS whose
> >> physical
> >>> + * CS can be 0. As a solution to this issue initialize all the CS to 0xFF.
> >>> + * Now all the unused logical CS will have 0xFF physical CS value
> >>> +& can
> >> be
> >>> + * ignore while performing physical CS validity checks.
> >>> + */
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>> + spi_set_chipselect(spi, idx, 0xFF);
> >>> +
> >>> /* Device address */
> >>> - rc = of_property_read_u32(nc, "reg", &value);
> >>> - if (rc) {
> >>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> >>> + SPI_CS_CNT_MAX);
> >>> + if (rc < 0) {
> >>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> >> (%d)\n",
> >>> nc, rc);
> >>> return rc;
> >>> }
> >>> - spi_set_chipselect(spi, 0, value);
> >>> + if (rc > ctlr->num_chipselect) {
> >>> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
> >>> num_chipselect (%d)\n",
> >>> + nc, rc);
> >>> + return rc;
> >>> + }
> >>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
> >>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> >>> + dev_err(&ctlr->dev, "SPI controller doesn't support multi
> >> CS\n");
> >>> + return -EINVAL;
> >>> + }
> >>> + for (idx = 0; idx < rc; idx++)
> >>> + spi_set_chipselect(spi, idx, cs[idx]);
> >>> +
> >>> + /* spi->chip_select[i] gives the corresponding physical CS for
> >>> +logical CS
> >> i
> >>> + * logical CS number is represented by setting the ith bit in spi-
> >>> cs_index_mask
> >>> + * So, for example, if spi->cs_index_mask = 0x01 then logical CS
> >> number is 0 and
> >>> + * spi->chip_select[0] will give the physical CS.
> >>> + * By default spi->chip_select[0] will hold the physical CS number
> >>> +so,
> >> set
> >>> + * spi->cs_index_mask as 0x01.
> >>> + */
> >>> + spi->cs_index_mask = 0x01;
> >>>
> >>> /* Device speed */
> >>> if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
> >>> -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller *ctlr)
> >>> struct boardinfo *bi;
> >>> int first_dynamic;
> >>> int status;
> >>> + int idx;
> >>>
> >>> if (!dev)
> >>> return -ENODEV;
> >>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct
> >>> spi_controller
> >> *ctlr)
> >>> }
> >>>
> >>> /* Setting last_cs to -1 means no chip selected */
> >>> - ctlr->last_cs = -1;
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>> + ctlr->last_cs[idx] = -1;
> >>>
> >>> status = device_add(&ctlr->dev);
> >>> if (status < 0)
> >>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device
> >>> *spi,
> >> struct spi_message *message)
> >>> * cs_change is set for each transfer.
> >>> */
> >>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> >> SPI_CS_WORD) ||
> >>> - spi_get_csgpiod(spi, 0))) {
> >>> + spi_is_csgpiod(spi))) {
> >>> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
> >>> int ret;
> >>>
> >>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> >>> 7b4baff63c5c..871d3a6d879b 100644
> >>> --- a/include/linux/spi/spi.h
> >>> +++ b/include/linux/spi/spi.h
> >>> @@ -20,6 +20,9 @@
> >>>
> >>> #include <uapi/linux/spi/spi.h>
> >>>
> >>> +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX
> >>> +4
> >>> +
> >>> struct dma_chan;
> >>> struct software_node;
> >>> struct ptp_system_timestamp;
> >>> @@ -132,7 +135,8 @@ extern void
> >> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>> * @max_speed_hz: Maximum clock rate to be used with this chip
> >>> * (on this board); may be changed by the device's driver.
> >>> * The spi_transfer.speed_hz can override this for each transfer.
> >>> - * @chip_select: Chipselect, distinguishing chips handled by @controller.
> >>> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
> >>> + * the corresponding physical CS for logical CS i.
> >>> * @mode: The spi mode defines how data is clocked out and in.
> >>> * This may be changed by the device's driver.
> >>> * The "active low" default for chipselect mode can be overridden
> >>> @@ -157,8 +161,8 @@ extern void
> >> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>> * the device will bind to the named driver and only the named driver.
> >>> * Do not set directly, because core frees it; use driver_set_override() to
> >>> * set or clear it.
> >>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL
> when
> >>> - * not using a GPIO line)
> >>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding
> >>> + chipselect
> >> lines
> >>> + * (optional, NULL when not using a GPIO line)
> >>> * @word_delay: delay to be inserted between consecutive
> >>> * words of a transfer
> >>> * @cs_setup: delay to be introduced by the controller after CS
> >>> is asserted @@ -167,6 +171,7 @@ extern void
> >> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>> * deasserted. If @cs_change_delay is used from @spi_transfer, then
> >> the
> >>> * two delays will be added up.
> >>> * @pcpu_statistics: statistics for the spi_device
> >>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> >>> + chipselect array
> >>> *
> >>> * A @spi_device is used to interchange data between an SPI slave
> >>> * (usually a discrete chip) and CPU memory.
> >>> @@ -182,7 +187,7 @@ struct spi_device {
> >>> struct spi_controller *controller;
> >>> struct spi_controller *master; /* Compatibility layer */
> >>> u32 max_speed_hz;
> >>> - u8 chip_select;
> >>> + u8 chip_select[SPI_CS_CNT_MAX];
> >>> u8 bits_per_word;
> >>> bool rt;
> >>> #define SPI_NO_TX BIT(31) /* No transmit wire */
> >>> @@ -213,7 +218,7 @@ struct spi_device {
> >>> void *controller_data;
> >>> char modalias[SPI_NAME_SIZE];
> >>> const char *driver_override;
> >>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor
> >> */
> >>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select
> >> gpio desc */
> >>> struct spi_delay word_delay; /* Inter-word delay */
> >>> /* CS delays */
> >>> struct spi_delay cs_setup;
> >>> @@ -223,6 +228,13 @@ struct spi_device {
> >>> /* The statistics */
> >>> struct spi_statistics __percpu *pcpu_statistics;
> >>>
> >>> + /* Bit mask of the chipselect(s) that the driver need to use from
> >>> + * the chipselect array.When the controller is capable to handle
> >>> + * multiple chip selects & memories are connected in parallel
> >>> + * then more than one bit need to be set in cs_index_mask.
> >>> + */
> >>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> >>> +
> >>> /*
> >>> * Likely need more hooks for more protocol options affecting how
> >>> * the controller talks to each chip, like:
> >>> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const
> >>> struct spi_device *spi)
> >>>
> >>> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
> >>> {
> >>> - return spi->chip_select;
> >>> + return spi->chip_select[idx];
> >>> }
> >>>
> >>> static inline void spi_set_chipselect(struct spi_device *spi, u8
> >>> idx, u8
> >> chipselect)
> >>> {
> >>> - spi->chip_select = chipselect;
> >>> + spi->chip_select[idx] = chipselect;
> >>> }
> >>>
> >>> static inline struct gpio_desc *spi_get_csgpiod(const struct
> >>> spi_device *spi,
> >> u8 idx)
> >>> {
> >>> - return spi->cs_gpiod;
> >>> + return spi->cs_gpiod[idx];
> >>> }
> >>>
> >>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
> >>> idx, struct
> >> gpio_desc *csgpiod)
> >>> {
> >>> - spi->cs_gpiod = csgpiod;
> >>> + spi->cs_gpiod[idx] = csgpiod;
> >>> +}
> >>> +
> >>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
> >>> + u8 idx;
> >>> +
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + if (spi_get_csgpiod(spi, idx))
> >>> + return true;
> >>> + }
> >>> + return false;
> >>> }
> >>>
> >>> /**
> >>> @@ -399,6 +422,8 @@ extern struct spi_device
> >> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> >>> * @bus_lock_spinlock: spinlock for SPI bus locking
> >>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> >>> * @bus_lock_flag: indicates that the SPI bus is locked for
> >>> exclusive use
> >>> + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
> >>> + * more than one chip select at once.
> >>> * @setup: updates the device mode and clocking records used by a
> >>> * device's SPI controller; protocol code may call this. This
> >>> * must fail if an unrecognized or unsupported mode is requested.
> >>> @@ -567,6 +592,11 @@ struct spi_controller {
> >>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
> */
> >>> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS
> must
> >> select slave */
> >>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
> >> suspended */
> >>> + /*
> >>> + * The spi-controller has multi chip select capability and can
> >>> + * assert/de-assert more than one chip select at once.
> >>> + */
> >>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
> >>>
> >>> /* Flag indicating if the allocation of this struct is devres-managed */
> >>> bool devm_allocated;
> >>> @@ -677,7 +707,8 @@ struct spi_controller {
> >>> bool rt;
> >>> bool auto_runtime_pm;
> >>> bool cur_msg_mapped;
> >>> - char last_cs;
> >>> + char last_cs[SPI_CS_CNT_MAX];
> >>> + char last_cs_index_mask;
> >>> bool last_cs_mode_high;
> >>> bool fallback;
> >>> struct completion xfer_completion;
On 21/11/2023 16:35, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Tuesday, November 21, 2023 7:28 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>; linux-
>> [email protected]; git (AMD-Xilinx) <[email protected]>;
>> [email protected]; [email protected]
>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>>
>>
>> On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
>>> Hello Stefan,
>>>
>>>> -----Original Message-----
>>>> From: Stefan Binding <[email protected]>
>>>> Sent: Monday, November 20, 2023 8:00 PM
>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]; [email protected]
>>>> Cc: [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; Simek, Michal <[email protected]>;
>>>> linux- [email protected]; git (AMD-Xilinx)
>>>> <[email protected]>; [email protected];
>>>> [email protected]
>>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
>>>> SPI core
>>>>
>>>>
>>>> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
>>>>> AMD-Xilinx GQSPI controller has two advanced mode that allows the
>>>>> controller to consider two flashes as one single device.
>>>>>
>>>>> One of these two mode is the parallel mode in which each byte of
>>>>> data is stored in both devices, the even bits in the lower flash &
>>>>> the odd bits in the upper flash. The byte split is automatically
>>>>> handled by the QSPI controller.
>>>>>
>>>>> The other mode is the stacked mode in which both the flashes share
>>>>> the same SPI bus but each of the device contain half of the data. In
>>>>> this mode, the controller does not follow CS requests but instead
>>>>> internally wires the two CS levels with the value of the most
>>>>> significant
>>>> address bit.
>>>>> For supporting both these modes SPI core need to be updated for
>>>>> providing multiple CS for a single SPI device.
>>>>>
>>>>> For adding multi CS support the SPI device need to be aware of all
>>>>> the CS values. So, the "chip_select" member in the spi_device
>>>>> structure is now an array that holds all the CS values.
>>>>>
>>>>> spi_device structure now has a "cs_index_mask" member. This acts as
>>>>> an index to the chip_select array. If nth bit of spi->cs_index_mask
>>>>> is set then the driver would assert spi->chip_select[n].
>>>>>
>>>>> In parallel mode all the chip selects are asserted/de-asserted
>>>>> simultaneously and each byte of data is stored in both devices, the
>>>>> even bits in one, the odd bits in the other. The split is
>>>>> automatically handled by the GQSPI controller. The GQSPI controller
>>>>> supports a maximum of two flashes connected in parallel mode. A
>>>>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi controller
>>>>> flags, through ctlr->flags the spi core will make sure that the
>>>>> controller is capable of handling multiple chip selects at once.
>>>>>
>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>>>> spi_device structure is now an array that holds the gpio descriptor
>>>>> for each chipselect.
>>>>>
>>>>> CS GPIO is not tested due to unavailability of necessary hardware setup.
>>>>>
>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
>> [email protected]>
>>>>> ---
>>>>> Hello @Stefen,
>>>>> We restructured the SPI core implementation, for handling arbitrary
>>>>> number of devices connected in parallel(multi-cs) or stacked mode.
>>>>> We have tested this updated patch on native-cs setup but couldn't
>>>>> test cs-gpio due to unavailability of a proper setup. If possible,
>>>>> could you please retest the cs-gpio use case with this updated patch
>>>>> and provide
>>>> your feedback.
>>>>
>>>> Hi,
>>>>
>>>> I tested this chain on 2 different systems using GPIOs as chip
>>>> selects, and see the same error on both:
>>>> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
>>>>
>>>> Let me know if you need any further testing.
>>>>
>>>> Thanks,
>>>>
>>>> Stefan Binding
>>>>
>>>>> ---
>>>>> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---------
>>>>> include/linux/spi/spi.h | 51 ++++++++---
>>>>> 2 files changed, 191 insertions(+), 52 deletions(-)
>>>>>
>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>>>> 8ead7acb99f3..ff66147ba95f 100644
>>>>> --- a/drivers/spi/spi.c
>>>>> +++ b/drivers/spi/spi.c
>>>>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev,
>>>>> void
>>>> *data)
>>>>> {
>>>>> struct spi_device *spi = to_spi_device(dev);
>>>>> struct spi_device *new_spi = data;
>>>>> -
>>>>> - if (spi->controller == new_spi->controller &&
>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
>>>>> - return -EBUSY;
>>>>> + int idx, nw_idx;
>>>>> + u8 cs, cs_nw;
>>>>> +
>>>>> + if (spi->controller == new_spi->controller) {
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>>>> nw_idx++) {
>>>>> + cs_nw = spi_get_chipselect(spi, nw_idx);
>>> Thank you for dedicating your time to test my patch.
>>> As per my analysis the error is reported from here as we are supplying
>>> the former SPI device structure to retrieve the CS value for the new
>>> SPI devices.
>>> To fix this, could you kindly substitute the above line with
>>>
>>> cs_nw = spi_get_chipselect(new_spi, nw_idx);
>>>
>>> and rerun your tests?
>>> If it works correctly, I will incorporate this fix into my upcoming
>>> series.
>>>
>>> Regards,
>>> Amit
Hi,
I've attached my log.
I notice that you add a print to of_spi_parse_dt, however since the
laptop I am using is an x86 laptop, it uses ACPI rather than OF, and I
don't think this function isnt even compiled in.
Thanks,
Stefan
>> Hi,
>>
>> I still see the same error:
>>
>> [Â Â Â 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
> Thank you for the quick testing. For further analysis I have incorporated
> additional debug prints on top of 1/8 patch. The corresponding diff is
> shared below. Kindly implement the specified changes, rerun your test and
> share the kernel logs.
>
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index ff66147ba95f..7f59ea81593d 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -618,8 +618,10 @@ static int spi_dev_check(struct device *dev, void *data)
> if (spi->controller == new_spi->controller) {
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> cs = spi_get_chipselect(spi, idx);
> + printk("%s() [%d] CS[%d] = [%d]\n", __func__, __LINE__, idx, cs);
> for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> - cs_nw = spi_get_chipselect(spi, nw_idx);
> + cs_nw = spi_get_chipselect(new_spi, nw_idx);
> + printk("%s() [%d] CS_NEW[%d] = [%d]\n", __func__, __LINE__, nw_idx, cs_nw);
> if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> dev_err(dev, "chipselect %d already in use\n", cs_nw);
> return -EBUSY;
> @@ -659,8 +661,10 @@ static int __spi_add_device(struct spi_device *spi)
> */
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> cs = spi_get_chipselect(spi, idx);
> + printk("%s() [%d] CS[%d] = [%d]\n", __func__, __LINE__, idx, cs);
> for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> nw_cs = spi_get_chipselect(spi, nw_idx);
> + printk("%s() [%d] CS_NEW[%d] = [%d]\n", __func__, __LINE__, nw_idx, nw_cs);
> if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> dev_err(dev, "chipselect %d already in use\n", nw_cs);
> return -EBUSY;
> @@ -2401,6 +2405,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> for (idx = 0; idx < rc; idx++)
> spi_set_chipselect(spi, idx, cs[idx]);
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + printk("%s() [%d] CS[%d] = [%d]\n", __func__, __LINE__, idx, spi_get_chipselect(spi, idx));
> +
> /* spi->chip_select[i] gives the corresponding physical CS for logical CS i
> * logical CS number is represented by setting the ith bit in spi->cs_index_mask
> * So, for example, if spi->cs_index_mask = 0x01 then logical CS number is 0 and
>
> Regards,
> Amit
>
>> Thanks,
>>
>> Stefan
>>
>>>>> + if (cs != 0xFF && cs_nw != 0xFF && cs ==
>>>> cs_nw) {
>>>>> + dev_err(dev, "chipselect %d already in
>>>> use\n", cs_nw);
>>>>> + return -EBUSY;
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> return 0;
>>>>> }
>>>>>
>>>>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct spi_device
>> *spi)
>>>>> {
>>>>> struct spi_controller *ctlr = spi->controller;
>>>>> struct device *dev = ctlr->dev.parent;
>>>>> - int status;
>>>>> + int status, idx, nw_idx;
>>>>> + u8 cs, nw_cs;
>>>>> +
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>> spi_get_chipselect(spi, idx),
>>>>> + ctlr->num_chipselect);
>>>>> + return -EINVAL;
>>>>> + }
>>>>> + }
>>>>>
>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>> - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
>>>>> - ctlr->num_chipselect);
>>>>> - return -EINVAL;
>>>>> + /*
>>>>> + * Make sure that multiple logical CS doesn't map to the same
>>>> physical CS.
>>>>> + * For example, spi->chip_select[0] != spi->chip_select[1] and so on.
>>>>> + */
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
>>>>> + nw_cs = spi_get_chipselect(spi, nw_idx);
>>>>> + if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
>>>>> + dev_err(dev, "chipselect %d already in use\n",
>>>> nw_cs);
>>>>> + return -EBUSY;
>>>>> + }
>>>>> + }
>>>>> }
>>>>>
>>>>> /* Set the bus ID string */
>>>>> @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device
>> *spi)
>>>>> * its configuration.
>>>>> */
>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
>>>>> - if (status) {
>>>>> - dev_err(dev, "chipselect %d already in use\n",
>>>>> - spi_get_chipselect(spi, 0));
>>>>> + if (status)
>>>>> return status;
>>>>> - }
>>>>>
>>>>> /* Controller may unregister concurrently */
>>>>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8 +686,15 @@
>>>> static
>>>>> int __spi_add_device(struct spi_device *spi)
>>>>> return -ENODEV;
>>>>> }
>>>>>
>>>>> - if (ctlr->cs_gpiods)
>>>>> - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi,
>>>> 0)]);
>>>>> + if (ctlr->cs_gpiods) {
>>>>> + u8 cs;
>>>>> +
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>> + if (cs != 0xFF)
>>>>> + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]);
>>>>> + }
>>>>> + }
>>>>>
>>>>> /*
>>>>> * Drivers may modify this initial i/o setup, but will @@ -701,6
>>>>> +735,9 @@ int spi_add_device(struct spi_device *spi)
>>>>> struct spi_controller *ctlr = spi->controller;
>>>>> int status;
>>>>>
>>>>> + /* Set the bus ID string */
>>>>> + spi_dev_set_name(spi);
>>>>> +
>>>>> mutex_lock(&ctlr->add_lock);
>>>>> status = __spi_add_device(spi);
>>>>> mutex_unlock(&ctlr->add_lock);
>>>>> @@ -942,32 +979,51 @@ static void spi_res_release(struct
>>>>> spi_controller
>>>> *ctlr, struct spi_message *mes
>>>>> }
>>>>>
>>>>>
>>>>> /*------------------------------------------------------------------
>>>>> --
>>>>> -----*/
>>>>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
>>>>> + u8 idx;
>>>>> + bool last = false;
>>>>> +
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + if ((spi->cs_index_mask >> idx) & 0x01) {
>>>>> + if (spi->controller->last_cs[idx] ==
>>>> spi_get_chipselect(spi, idx))
>>>>> + last = true;
>>>>> + }
>>>>> + }
>>>>> + return last;
>>>>> +}
>>>>> +
>>>>>
>>>>> static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
>>>>> {
>>>>> bool activate = enable;
>>>>> + u8 idx;
>>>>>
>>>>> /*
>>>>> * Avoid calling into the driver (or doing delays) if the chip select
>>>>> * isn't actually changing from the last time this was called.
>>>>> */
>>>>> - if (!force && ((enable && spi->controller->last_cs ==
>>>> spi_get_chipselect(spi, 0)) ||
>>>>> - (!enable && spi->controller->last_cs !=
>>>> spi_get_chipselect(spi, 0))) &&
>>>>> + if (!force && ((enable && spi->controller->last_cs_index_mask ==
>>>>> +spi-
>>>>> cs_index_mask &&
>>>>> + spi_is_last_cs(spi)) ||
>>>>> + (!enable && spi->controller->last_cs_index_mask == spi-
>>>>> cs_index_mask &&
>>>>> + !spi_is_last_cs(spi))) &&
>>>>> (spi->controller->last_cs_mode_high == (spi->mode &
>>>> SPI_CS_HIGH)))
>>>>> return;
>>>>>
>>>>> trace_spi_set_cs(spi, activate);
>>>>>
>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
>>>>> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>> + spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi,
>>>> 0)
>>>>> +: -1;
>>>>> spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
>>>>>
>>>>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) &&
>>>> !activate)
>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>>>> -
>>>>> if (spi->mode & SPI_CS_HIGH)
>>>>> enable = !enable;
>>>>>
>>>>> - if (spi_get_csgpiod(spi, 0)) {
>>>>> + if (spi_is_csgpiod(spi)) {
>>>>> + if (!spi->controller->set_cs_timing && !activate)
>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>> +
>>>>> if (!(spi->mode & SPI_NO_CS)) {
>>>>> /*
>>>>> * Historically ACPI has no means of the GPIO polarity
>>>> and @@
>>>>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi,
>>>>> bool
>>>> enable, bool force)
>>>>> * ambiguity. That's why we use enable, that takes
>>>> SPI_CS_HIGH
>>>>> * into account.
>>>>> */
>>>>> - if (has_acpi_companion(&spi->dev))
>>>>> -
>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>>>> - else
>>>>> - /* Polarity handled by GPIO library */
>>>>> -
>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + if (((spi->cs_index_mask >> idx) & 0x01) &&
>>>>> + spi_get_csgpiod(spi, idx)) {
>>>>> + if (has_acpi_companion(&spi->dev))
>>>>> +
>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>> +
>>>> !enable);
>>>>> + else
>>>>> + /* Polarity handled by GPIO
>>>> library */
>>>>> +
>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>> +
>>>> activate);
>>>>> +
>>>>> + if (activate)
>>>>> + spi_delay_exec(&spi-
>>>>> cs_setup, NULL);
>>>>> + else
>>>>> + spi_delay_exec(&spi-
>>>>> cs_inactive, NULL);
>>>>> + }
>>>>> + }
>>>>> }
>>>>> /* Some SPI masters need both GPIO CS & slave_select */
>>>>> if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
>>>>> spi->controller->set_cs)
>>>>> spi->controller->set_cs(spi, !enable);
>>>>> +
>>>>> + if (!spi->controller->set_cs_timing) {
>>>>> + if (activate)
>>>>> + spi_delay_exec(&spi->cs_setup, NULL);
>>>>> + else
>>>>> + spi_delay_exec(&spi->cs_inactive, NULL);
>>>>> + }
>>>>> } else if (spi->controller->set_cs) {
>>>>> spi->controller->set_cs(spi, !enable);
>>>>> }
>>>>> -
>>>>> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
>>>>> - if (activate)
>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>>>> - else
>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>>>> - }
>>>>> }
>>>>>
>>>>> #ifdef CONFIG_HAS_DMA
>>>>> @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct
>>>> device_node *nc,
>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device
>> *spi,
>>>>> struct device_node *nc)
>>>>> {
>>>>> - u32 value;
>>>>> - int rc;
>>>>> + u32 value, cs[SPI_CS_CNT_MAX];
>>>>> + int rc, idx;
>>>>>
>>>>> /* Mode (clock phase/polarity/etc.) */
>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14 +2363,52
>>>> @@
>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>>>>> return 0;
>>>>> }
>>>>>
>>>>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
>>>>> + dev_err(&ctlr->dev, "No. of CS is more than max. no. of
>>>> supported CS\n");
>>>>> + return -EINVAL;
>>>>> + }
>>>>> +
>>>>> + /*
>>>>> + * Zero(0) is a valid physical CS value and can be located at any
>>>>> + * logical CS in the spi->chip_select[]. If all the physical CS
>>>>> + * are initialized to 0 then It would be difficult to differentiate
>>>>> + * between a valid physical CS 0 & an unused logical CS whose
>>>> physical
>>>>> + * CS can be 0. As a solution to this issue initialize all the CS to 0xFF.
>>>>> + * Now all the unused logical CS will have 0xFF physical CS value
>>>>> +& can
>>>> be
>>>>> + * ignore while performing physical CS validity checks.
>>>>> + */
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>> + spi_set_chipselect(spi, idx, 0xFF);
>>>>> +
>>>>> /* Device address */
>>>>> - rc = of_property_read_u32(nc, "reg", &value);
>>>>> - if (rc) {
>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
>>>>> + SPI_CS_CNT_MAX);
>>>>> + if (rc < 0) {
>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>>>> (%d)\n",
>>>>> nc, rc);
>>>>> return rc;
>>>>> }
>>>>> - spi_set_chipselect(spi, 0, value);
>>>>> + if (rc > ctlr->num_chipselect) {
>>>>> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
>>>>> num_chipselect (%d)\n",
>>>>> + nc, rc);
>>>>> + return rc;
>>>>> + }
>>>>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support multi
>>>> CS\n");
>>>>> + return -EINVAL;
>>>>> + }
>>>>> + for (idx = 0; idx < rc; idx++)
>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>>>> +
>>>>> + /* spi->chip_select[i] gives the corresponding physical CS for
>>>>> +logical CS
>>>> i
>>>>> + * logical CS number is represented by setting the ith bit in spi-
>>>>> cs_index_mask
>>>>> + * So, for example, if spi->cs_index_mask = 0x01 then logical CS
>>>> number is 0 and
>>>>> + * spi->chip_select[0] will give the physical CS.
>>>>> + * By default spi->chip_select[0] will hold the physical CS number
>>>>> +so,
>>>> set
>>>>> + * spi->cs_index_mask as 0x01.
>>>>> + */
>>>>> + spi->cs_index_mask = 0x01;
>>>>>
>>>>> /* Device speed */
>>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
>>>>> -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller *ctlr)
>>>>> struct boardinfo *bi;
>>>>> int first_dynamic;
>>>>> int status;
>>>>> + int idx;
>>>>>
>>>>> if (!dev)
>>>>> return -ENODEV;
>>>>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct
>>>>> spi_controller
>>>> *ctlr)
>>>>> }
>>>>>
>>>>> /* Setting last_cs to -1 means no chip selected */
>>>>> - ctlr->last_cs = -1;
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>> + ctlr->last_cs[idx] = -1;
>>>>>
>>>>> status = device_add(&ctlr->dev);
>>>>> if (status < 0)
>>>>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device
>>>>> *spi,
>>>> struct spi_message *message)
>>>>> * cs_change is set for each transfer.
>>>>> */
>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>>>> SPI_CS_WORD) ||
>>>>> - spi_get_csgpiod(spi, 0))) {
>>>>> + spi_is_csgpiod(spi))) {
>>>>> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
>>>>> int ret;
>>>>>
>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
>>>>> 7b4baff63c5c..871d3a6d879b 100644
>>>>> --- a/include/linux/spi/spi.h
>>>>> +++ b/include/linux/spi/spi.h
>>>>> @@ -20,6 +20,9 @@
>>>>>
>>>>> #include <uapi/linux/spi/spi.h>
>>>>>
>>>>> +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX
>>>>> +4
>>>>> +
>>>>> struct dma_chan;
>>>>> struct software_node;
>>>>> struct ptp_system_timestamp;
>>>>> @@ -132,7 +135,8 @@ extern void
>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>> * @max_speed_hz: Maximum clock rate to be used with this chip
>>>>> * (on this board); may be changed by the device's driver.
>>>>> * The spi_transfer.speed_hz can override this for each transfer.
>>>>> - * @chip_select: Chipselect, distinguishing chips handled by @controller.
>>>>> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
>>>>> + * the corresponding physical CS for logical CS i.
>>>>> * @mode: The spi mode defines how data is clocked out and in.
>>>>> * This may be changed by the device's driver.
>>>>> * The "active low" default for chipselect mode can be overridden
>>>>> @@ -157,8 +161,8 @@ extern void
>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>> * the device will bind to the named driver and only the named driver.
>>>>> * Do not set directly, because core frees it; use driver_set_override() to
>>>>> * set or clear it.
>>>>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL
>> when
>>>>> - * not using a GPIO line)
>>>>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding
>>>>> + chipselect
>>>> lines
>>>>> + * (optional, NULL when not using a GPIO line)
>>>>> * @word_delay: delay to be inserted between consecutive
>>>>> * words of a transfer
>>>>> * @cs_setup: delay to be introduced by the controller after CS
>>>>> is asserted @@ -167,6 +171,7 @@ extern void
>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>> * deasserted. If @cs_change_delay is used from @spi_transfer, then
>>>> the
>>>>> * two delays will be added up.
>>>>> * @pcpu_statistics: statistics for the spi_device
>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>>>> + chipselect array
>>>>> *
>>>>> * A @spi_device is used to interchange data between an SPI slave
>>>>> * (usually a discrete chip) and CPU memory.
>>>>> @@ -182,7 +187,7 @@ struct spi_device {
>>>>> struct spi_controller *controller;
>>>>> struct spi_controller *master; /* Compatibility layer */
>>>>> u32 max_speed_hz;
>>>>> - u8 chip_select;
>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>>>> u8 bits_per_word;
>>>>> bool rt;
>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>>>> @@ -213,7 +218,7 @@ struct spi_device {
>>>>> void *controller_data;
>>>>> char modalias[SPI_NAME_SIZE];
>>>>> const char *driver_override;
>>>>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor
>>>> */
>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select
>>>> gpio desc */
>>>>> struct spi_delay word_delay; /* Inter-word delay */
>>>>> /* CS delays */
>>>>> struct spi_delay cs_setup;
>>>>> @@ -223,6 +228,13 @@ struct spi_device {
>>>>> /* The statistics */
>>>>> struct spi_statistics __percpu *pcpu_statistics;
>>>>>
>>>>> + /* Bit mask of the chipselect(s) that the driver need to use from
>>>>> + * the chipselect array.When the controller is capable to handle
>>>>> + * multiple chip selects & memories are connected in parallel
>>>>> + * then more than one bit need to be set in cs_index_mask.
>>>>> + */
>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>>>> +
>>>>> /*
>>>>> * Likely need more hooks for more protocol options affecting how
>>>>> * the controller talks to each chip, like:
>>>>> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const
>>>>> struct spi_device *spi)
>>>>>
>>>>> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
>>>>> {
>>>>> - return spi->chip_select;
>>>>> + return spi->chip_select[idx];
>>>>> }
>>>>>
>>>>> static inline void spi_set_chipselect(struct spi_device *spi, u8
>>>>> idx, u8
>>>> chipselect)
>>>>> {
>>>>> - spi->chip_select = chipselect;
>>>>> + spi->chip_select[idx] = chipselect;
>>>>> }
>>>>>
>>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
>>>>> spi_device *spi,
>>>> u8 idx)
>>>>> {
>>>>> - return spi->cs_gpiod;
>>>>> + return spi->cs_gpiod[idx];
>>>>> }
>>>>>
>>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
>>>>> idx, struct
>>>> gpio_desc *csgpiod)
>>>>> {
>>>>> - spi->cs_gpiod = csgpiod;
>>>>> + spi->cs_gpiod[idx] = csgpiod;
>>>>> +}
>>>>> +
>>>>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
>>>>> + u8 idx;
>>>>> +
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + if (spi_get_csgpiod(spi, idx))
>>>>> + return true;
>>>>> + }
>>>>> + return false;
>>>>> }
>>>>>
>>>>> /**
>>>>> @@ -399,6 +422,8 @@ extern struct spi_device
>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>>>>> exclusive use
>>>>> + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
>>>>> + * more than one chip select at once.
>>>>> * @setup: updates the device mode and clocking records used by a
>>>>> * device's SPI controller; protocol code may call this. This
>>>>> * must fail if an unrecognized or unsupported mode is requested.
>>>>> @@ -567,6 +592,11 @@ struct spi_controller {
>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
>> */
>>>>> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS
>> must
>>>> select slave */
>>>>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
>>>> suspended */
>>>>> + /*
>>>>> + * The spi-controller has multi chip select capability and can
>>>>> + * assert/de-assert more than one chip select at once.
>>>>> + */
>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
>>>>>
>>>>> /* Flag indicating if the allocation of this struct is devres-managed */
>>>>> bool devm_allocated;
>>>>> @@ -677,7 +707,8 @@ struct spi_controller {
>>>>> bool rt;
>>>>> bool auto_runtime_pm;
>>>>> bool cur_msg_mapped;
>>>>> - char last_cs;
>>>>> + char last_cs[SPI_CS_CNT_MAX];
>>>>> + char last_cs_index_mask;
>>>>> bool last_cs_mode_high;
>>>>> bool fallback;
>>>>> struct completion xfer_completion;
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Tuesday, November 21, 2023 11:07 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>; linux-
> [email protected]; git (AMD-Xilinx) <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>
>
> On 21/11/2023 16:35, Mahapatra, Amit Kumar wrote:
> > Hello Stefan,
> >
> >> -----Original Message-----
> >> From: Stefan Binding <[email protected]>
> >> Sent: Tuesday, November 21, 2023 7:28 PM
> >> To: Mahapatra, Amit Kumar <[email protected]>;
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected]
> >> Cc: [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Simek, Michal <[email protected]>;
> >> linux- [email protected]; git (AMD-Xilinx)
> >> <[email protected]>; [email protected];
> >> [email protected]
> >> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> >> SPI core
> >>
> >>
> >> On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
> >>> Hello Stefan,
> >>>
> >>>> -----Original Message-----
> >>>> From: Stefan Binding <[email protected]>
> >>>> Sent: Monday, November 20, 2023 8:00 PM
> >>>> To: Mahapatra, Amit Kumar <[email protected]>;
> >>>> [email protected]; [email protected]; [email protected];
> >>>> [email protected]; [email protected]; [email protected]
> >>>> Cc: [email protected]; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected]; Simek, Michal <[email protected]>;
> >>>> linux- [email protected]; git (AMD-Xilinx)
> >>>> <[email protected]>; [email protected];
> >>>> [email protected]
> >>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> >>>> SPI core
> >>>>
> >>>>
> >>>> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
> >>>>> AMD-Xilinx GQSPI controller has two advanced mode that allows the
> >>>>> controller to consider two flashes as one single device.
> >>>>>
> >>>>> One of these two mode is the parallel mode in which each byte of
> >>>>> data is stored in both devices, the even bits in the lower flash &
> >>>>> the odd bits in the upper flash. The byte split is automatically
> >>>>> handled by the QSPI controller.
> >>>>>
> >>>>> The other mode is the stacked mode in which both the flashes share
> >>>>> the same SPI bus but each of the device contain half of the data.
> >>>>> In this mode, the controller does not follow CS requests but
> >>>>> instead internally wires the two CS levels with the value of the
> >>>>> most significant
> >>>> address bit.
> >>>>> For supporting both these modes SPI core need to be updated for
> >>>>> providing multiple CS for a single SPI device.
> >>>>>
> >>>>> For adding multi CS support the SPI device need to be aware of all
> >>>>> the CS values. So, the "chip_select" member in the spi_device
> >>>>> structure is now an array that holds all the CS values.
> >>>>>
> >>>>> spi_device structure now has a "cs_index_mask" member. This acts
> >>>>> as an index to the chip_select array. If nth bit of
> >>>>> spi->cs_index_mask is set then the driver would assert spi-
> >chip_select[n].
> >>>>>
> >>>>> In parallel mode all the chip selects are asserted/de-asserted
> >>>>> simultaneously and each byte of data is stored in both devices,
> >>>>> the even bits in one, the odd bits in the other. The split is
> >>>>> automatically handled by the GQSPI controller. The GQSPI
> >>>>> controller supports a maximum of two flashes connected in parallel
> >>>>> mode. A SPI_CONTROLLER_MULTI_CS flag bit is added in the spi
> >>>>> controller flags, through ctlr->flags the spi core will make sure
> >>>>> that the controller is capable of handling multiple chip selects at once.
> >>>>>
> >>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
> >>>>> spi_device structure is now an array that holds the gpio
> >>>>> descriptor for each chipselect.
> >>>>>
> >>>>> CS GPIO is not tested due to unavailability of necessary hardware
> setup.
> >>>>>
> >>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> >> [email protected]>
> >>>>> ---
> >>>>> Hello @Stefen,
> >>>>> We restructured the SPI core implementation, for handling
> >>>>> arbitrary number of devices connected in parallel(multi-cs) or stacked
> mode.
> >>>>> We have tested this updated patch on native-cs setup but couldn't
> >>>>> test cs-gpio due to unavailability of a proper setup. If possible,
> >>>>> could you please retest the cs-gpio use case with this updated
> >>>>> patch and provide
> >>>> your feedback.
> >>>>
> >>>> Hi,
> >>>>
> >>>> I tested this chain on 2 different systems using GPIOs as chip
> >>>> selects, and see the same error on both:
> >>>> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
> >>>>
> >>>> Let me know if you need any further testing.
> >>>>
> >>>> Thanks,
> >>>>
> >>>> Stefan Binding
> >>>>
> >>>>> ---
> >>>>> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++-------
> --
> >>>>> include/linux/spi/spi.h | 51 ++++++++---
> >>>>> 2 files changed, 191 insertions(+), 52 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>>>> 8ead7acb99f3..ff66147ba95f 100644
> >>>>> --- a/drivers/spi/spi.c
> >>>>> +++ b/drivers/spi/spi.c
> >>>>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev,
> >>>>> void
> >>>> *data)
> >>>>> {
> >>>>> struct spi_device *spi = to_spi_device(dev);
> >>>>> struct spi_device *new_spi = data;
> >>>>> -
> >>>>> - if (spi->controller == new_spi->controller &&
> >>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
> >>>>> - return -EBUSY;
> >>>>> + int idx, nw_idx;
> >>>>> + u8 cs, cs_nw;
> >>>>> +
> >>>>> + if (spi->controller == new_spi->controller) {
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> >>>> nw_idx++) {
> >>>>> + cs_nw = spi_get_chipselect(spi,
> nw_idx);
> >>> Thank you for dedicating your time to test my patch.
> >>> As per my analysis the error is reported from here as we are
> >>> supplying the former SPI device structure to retrieve the CS value
> >>> for the new SPI devices.
> >>> To fix this, could you kindly substitute the above line with
> >>>
> >>> cs_nw = spi_get_chipselect(new_spi, nw_idx);
> >>>
> >>> and rerun your tests?
> >>> If it works correctly, I will incorporate this fix into my upcoming
> >>> series.
> >>>
> >>> Regards,
> >>> Amit
>
> Hi,
>
> I've attached my log.
> I notice that you add a print to of_spi_parse_dt, however since the laptop I
> am using is an x86 laptop, it uses ACPI rather than OF, and I don't think this
> function isnt even compiled in.
That’s correct, I missed it.
Upon reviewing the logs, I discovered that in the ACPI flow, I am not
initializing the unused CS[] to FF, as I am doing in the OF flow.
Consequently, in the ACPI flow, all the unused CS[] are automatically
initialized to 0. During the __spi_add_device process, the SPI core faces
difficulty distinguishing between a valid CS value of 0 and an unused CS
value of 0, leading to a failure in the driver probe.
Incorporating the following modifications should resolve this issue.
Kindly apply these changes on top of 1/8 and re-run the test.
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ff66147ba95f..d0301c17d4f8 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -619,7 +619,7 @@ static int spi_dev_check(struct device *dev, void *data)
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
cs = spi_get_chipselect(spi, idx);
for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
- cs_nw = spi_get_chipselect(spi, nw_idx);
+ cs_nw = spi_get_chipselect(new_spi, nw_idx);
if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
dev_err(dev, "chipselect %d already in use\n", cs_nw);
return -EBUSY;
@@ -764,6 +764,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
{
struct spi_device *proxy;
int status;
+ u8 idx;
/*
* NOTE: caller did any chip->bus_num checks necessary.
@@ -779,6 +780,9 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(proxy, idx, 0xFF);
+
spi_set_chipselect(proxy, 0, chip->chip_select);
proxy->max_speed_hz = chip->max_speed_hz;
proxy->mode = chip->mode;
@@ -2514,6 +2518,7 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
struct spi_controller *ctlr = spi->controller;
struct spi_device *ancillary;
int rc = 0;
+ u8 idx;
/* Alloc an spi_device */
ancillary = spi_alloc_device(ctlr);
@@ -2524,6 +2529,9 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
strscpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias));
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(ancillary, idx, 0xFF);
+
/* Use provided chip-select for ancillary device */
spi_set_chipselect(ancillary, 0, chip_select);
@@ -2732,6 +2740,7 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
struct acpi_spi_lookup lookup = {};
struct spi_device *spi;
int ret;
+ u8 idx;
if (!ctlr && index == -1)
return ERR_PTR(-EINVAL);
@@ -2767,6 +2776,9 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
return ERR_PTR(-ENOMEM);
}
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(spi, idx, 0xFF);
+
ACPI_COMPANION_SET(&spi->dev, adev);
spi->max_speed_hz = lookup.max_speed_hz;
spi->mode |= lookup.mode;
Regards,
Amit
> Thanks,
>
> Stefan
>
> >> Hi,
> >>
> >> I still see the same error:
> >>
> >> [Â Â Â 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
> > Thank you for the quick testing. For further analysis I have
> > incorporated additional debug prints on top of 1/8 patch. The
> > corresponding diff is shared below. Kindly implement the specified
> > changes, rerun your test and share the kernel logs.
> >
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > ff66147ba95f..7f59ea81593d 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -618,8 +618,10 @@ static int spi_dev_check(struct device *dev, void
> *data)
> > if (spi->controller == new_spi->controller) {
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > cs = spi_get_chipselect(spi, idx);
> > + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> > + __LINE__, idx, cs);
> > for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> > - cs_nw = spi_get_chipselect(spi, nw_idx);
> > + cs_nw = spi_get_chipselect(new_spi, nw_idx);
> > + printk("%s() [%d] CS_NEW[%d] =
> > + [%d]\n", __func__, __LINE__, nw_idx, cs_nw);
> > if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> > dev_err(dev, "chipselect %d already in use\n",
> cs_nw);
> > return -EBUSY; @@ -659,8
> > +661,10 @@ static int __spi_add_device(struct spi_device *spi)
> > */
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > cs = spi_get_chipselect(spi, idx);
> > + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> > + __LINE__, idx, cs);
> > for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> > nw_cs = spi_get_chipselect(spi, nw_idx);
> > + printk("%s() [%d] CS_NEW[%d] = [%d]\n",
> > + __func__, __LINE__, nw_idx, nw_cs);
> > if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> > dev_err(dev, "chipselect %d already in use\n", nw_cs);
> > return -EBUSY; @@ -2401,6 +2405,9 @@
> > static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> > for (idx = 0; idx < rc; idx++)
> > spi_set_chipselect(spi, idx, cs[idx]);
> >
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> > + __LINE__, idx, spi_get_chipselect(spi, idx));
> > +
> > /* spi->chip_select[i] gives the corresponding physical CS for logical CS i
> > * logical CS number is represented by setting the ith bit in spi-
> >cs_index_mask
> > * So, for example, if spi->cs_index_mask = 0x01 then logical
> > CS number is 0 and
> >
> > Regards,
> > Amit
> >
> >> Thanks,
> >>
> >> Stefan
> >>
> >>>>> + if (cs != 0xFF && cs_nw != 0xFF && cs
> ==
> >>>> cs_nw) {
> >>>>> + dev_err(dev, "chipselect %d
> already in
> >>>> use\n", cs_nw);
> >>>>> + return -EBUSY;
> >>>>> + }
> >>>>> + }
> >>>>> + }
> >>>>> + }
> >>>>> return 0;
> >>>>> }
> >>>>>
> >>>>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct
> >>>>> spi_device
> >> *spi)
> >>>>> {
> >>>>> struct spi_controller *ctlr = spi->controller;
> >>>>> struct device *dev = ctlr->dev.parent;
> >>>>> - int status;
> >>>>> + int status, idx, nw_idx;
> >>>>> + u8 cs, nw_cs;
> >>>>> +
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + /* Chipselects are numbered 0..max; validate. */
> >>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
> >>>>> + dev_err(dev, "cs%d >= max %d\n",
> >>>> spi_get_chipselect(spi, idx),
> >>>>> + ctlr->num_chipselect);
> >>>>> + return -EINVAL;
> >>>>> + }
> >>>>> + }
> >>>>>
> >>>>> - /* Chipselects are numbered 0..max; validate. */
> >>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>>>> - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
> >>>>> - ctlr->num_chipselect);
> >>>>> - return -EINVAL;
> >>>>> + /*
> >>>>> + * Make sure that multiple logical CS doesn't map to the same
> >>>> physical CS.
> >>>>> + * For example, spi->chip_select[0] != spi->chip_select[1] and
> so on.
> >>>>> + */
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX;
> nw_idx++) {
> >>>>> + nw_cs = spi_get_chipselect(spi, nw_idx);
> >>>>> + if (cs != 0xFF && nw_cs != 0xFF && cs ==
> nw_cs) {
> >>>>> + dev_err(dev, "chipselect %d already in
> use\n",
> >>>> nw_cs);
> >>>>> + return -EBUSY;
> >>>>> + }
> >>>>> + }
> >>>>> }
> >>>>>
> >>>>> /* Set the bus ID string */
> >>>>> @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device
> >> *spi)
> >>>>> * its configuration.
> >>>>> */
> >>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> spi_dev_check);
> >>>>> - if (status) {
> >>>>> - dev_err(dev, "chipselect %d already in use\n",
> >>>>> - spi_get_chipselect(spi, 0));
> >>>>> + if (status)
> >>>>> return status;
> >>>>> - }
> >>>>>
> >>>>> /* Controller may unregister concurrently */
> >>>>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8
> +686,15 @@
> >>>> static
> >>>>> int __spi_add_device(struct spi_device *spi)
> >>>>> return -ENODEV;
> >>>>> }
> >>>>>
> >>>>> - if (ctlr->cs_gpiods)
> >>>>> - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi,
> >>>> 0)]);
> >>>>> + if (ctlr->cs_gpiods) {
> >>>>> + u8 cs;
> >>>>> +
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>> + if (cs != 0xFF)
> >>>>> + spi_set_csgpiod(spi, idx, ctlr-
> >cs_gpiods[cs]);
> >>>>> + }
> >>>>> + }
> >>>>>
> >>>>> /*
> >>>>> * Drivers may modify this initial i/o setup, but will @@
> >>>>> -701,6
> >>>>> +735,9 @@ int spi_add_device(struct spi_device *spi)
> >>>>> struct spi_controller *ctlr = spi->controller;
> >>>>> int status;
> >>>>>
> >>>>> + /* Set the bus ID string */
> >>>>> + spi_dev_set_name(spi);
> >>>>> +
> >>>>> mutex_lock(&ctlr->add_lock);
> >>>>> status = __spi_add_device(spi);
> >>>>> mutex_unlock(&ctlr->add_lock); @@ -942,32 +979,51 @@
> static
> >>>>> void spi_res_release(struct spi_controller
> >>>> *ctlr, struct spi_message *mes
> >>>>> }
> >>>>>
> >>>>>
> >>>>> /*----------------------------------------------------------------
> >>>>> --
> >>>>> --
> >>>>> -----*/
> >>>>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
> >>>>> + u8 idx;
> >>>>> + bool last = false;
> >>>>> +
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + if ((spi->cs_index_mask >> idx) & 0x01) {
> >>>>> + if (spi->controller->last_cs[idx] ==
> >>>> spi_get_chipselect(spi, idx))
> >>>>> + last = true;
> >>>>> + }
> >>>>> + }
> >>>>> + return last;
> >>>>> +}
> >>>>> +
> >>>>>
> >>>>> static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
> >>>>> {
> >>>>> bool activate = enable;
> >>>>> + u8 idx;
> >>>>>
> >>>>> /*
> >>>>> * Avoid calling into the driver (or doing delays) if the chip
> select
> >>>>> * isn't actually changing from the last time this was called.
> >>>>> */
> >>>>> - if (!force && ((enable && spi->controller->last_cs ==
> >>>> spi_get_chipselect(spi, 0)) ||
> >>>>> - (!enable && spi->controller->last_cs !=
> >>>> spi_get_chipselect(spi, 0))) &&
> >>>>> + if (!force && ((enable && spi->controller->last_cs_index_mask
> ==
> >>>>> +spi-
> >>>>> cs_index_mask &&
> >>>>> + spi_is_last_cs(spi)) ||
> >>>>> + (!enable && spi->controller->last_cs_index_mask
> == spi-
> >>>>> cs_index_mask &&
> >>>>> + !spi_is_last_cs(spi))) &&
> >>>>> (spi->controller->last_cs_mode_high == (spi->mode &
> >>>> SPI_CS_HIGH)))
> >>>>> return;
> >>>>>
> >>>>> trace_spi_set_cs(spi, activate);
> >>>>>
> >>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
> >>>>> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>> + spi->controller->last_cs[idx] = enable ?
> >>>>> +spi_get_chipselect(spi,
> >>>> 0)
> >>>>> +: -1;
> >>>>> spi->controller->last_cs_mode_high = spi->mode &
> SPI_CS_HIGH;
> >>>>>
> >>>>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) &&
> >>>> !activate)
> >>>>> - spi_delay_exec(&spi->cs_hold, NULL);
> >>>>> -
> >>>>> if (spi->mode & SPI_CS_HIGH)
> >>>>> enable = !enable;
> >>>>>
> >>>>> - if (spi_get_csgpiod(spi, 0)) {
> >>>>> + if (spi_is_csgpiod(spi)) {
> >>>>> + if (!spi->controller->set_cs_timing && !activate)
> >>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>>>> +
> >>>>> if (!(spi->mode & SPI_NO_CS)) {
> >>>>> /*
> >>>>> * Historically ACPI has no means of the GPIO
> polarity
> >>>> and @@
> >>>>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi,
> >>>>> bool
> >>>> enable, bool force)
> >>>>> * ambiguity. That's why we use enable, that
> takes
> >>>> SPI_CS_HIGH
> >>>>> * into account.
> >>>>> */
> >>>>> - if (has_acpi_companion(&spi->dev))
> >>>>> -
> >>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> >>>>> - else
> >>>>> - /* Polarity handled by GPIO library */
> >>>>> -
> >>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + if (((spi->cs_index_mask >> idx) &
> 0x01) &&
> >>>>> + spi_get_csgpiod(spi, idx)) {
> >>>>> + if (has_acpi_companion(&spi-
> >dev))
> >>>>> +
> >>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>> +
> >>>> !enable);
> >>>>> + else
> >>>>> + /* Polarity handled by
> GPIO
> >>>> library */
> >>>>> +
> >>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>> +
> >>>> activate);
> >>>>> +
> >>>>> + if (activate)
> >>>>> + spi_delay_exec(&spi-
> >>>>> cs_setup, NULL);
> >>>>> + else
> >>>>> + spi_delay_exec(&spi-
> >>>>> cs_inactive, NULL);
> >>>>> + }
> >>>>> + }
> >>>>> }
> >>>>> /* Some SPI masters need both GPIO CS &
> slave_select */
> >>>>> if ((spi->controller->flags &
> SPI_CONTROLLER_GPIO_SS) &&
> >>>>> spi->controller->set_cs)
> >>>>> spi->controller->set_cs(spi, !enable);
> >>>>> +
> >>>>> + if (!spi->controller->set_cs_timing) {
> >>>>> + if (activate)
> >>>>> + spi_delay_exec(&spi->cs_setup,
> NULL);
> >>>>> + else
> >>>>> + spi_delay_exec(&spi->cs_inactive,
> NULL);
> >>>>> + }
> >>>>> } else if (spi->controller->set_cs) {
> >>>>> spi->controller->set_cs(spi, !enable);
> >>>>> }
> >>>>> -
> >>>>> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
> >>>>> - if (activate)
> >>>>> - spi_delay_exec(&spi->cs_setup, NULL);
> >>>>> - else
> >>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
> >>>>> - }
> >>>>> }
> >>>>>
> >>>>> #ifdef CONFIG_HAS_DMA
> >>>>> @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct
> >>>> device_node *nc,
> >>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> >>>>> spi_device
> >> *spi,
> >>>>> struct device_node *nc)
> >>>>> {
> >>>>> - u32 value;
> >>>>> - int rc;
> >>>>> + u32 value, cs[SPI_CS_CNT_MAX];
> >>>>> + int rc, idx;
> >>>>>
> >>>>> /* Mode (clock phase/polarity/etc.) */
> >>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14
> >>>>> +2363,52
> >>>> @@
> >>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device
> *spi,
> >>>>> return 0;
> >>>>> }
> >>>>>
> >>>>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
> >>>>> + dev_err(&ctlr->dev, "No. of CS is more than max. no.
> of
> >>>> supported CS\n");
> >>>>> + return -EINVAL;
> >>>>> + }
> >>>>> +
> >>>>> + /*
> >>>>> + * Zero(0) is a valid physical CS value and can be located at
> any
> >>>>> + * logical CS in the spi->chip_select[]. If all the physical CS
> >>>>> + * are initialized to 0 then It would be difficult to differentiate
> >>>>> + * between a valid physical CS 0 & an unused logical CS whose
> >>>> physical
> >>>>> + * CS can be 0. As a solution to this issue initialize all the CS to
> 0xFF.
> >>>>> + * Now all the unused logical CS will have 0xFF physical CS
> >>>>> +value & can
> >>>> be
> >>>>> + * ignore while performing physical CS validity checks.
> >>>>> + */
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>> + spi_set_chipselect(spi, idx, 0xFF);
> >>>>> +
> >>>>> /* Device address */
> >>>>> - rc = of_property_read_u32(nc, "reg", &value);
> >>>>> - if (rc) {
> >>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
> 1,
> >>>>> + SPI_CS_CNT_MAX);
> >>>>> + if (rc < 0) {
> >>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> >>>> (%d)\n",
> >>>>> nc, rc);
> >>>>> return rc;
> >>>>> }
> >>>>> - spi_set_chipselect(spi, 0, value);
> >>>>> + if (rc > ctlr->num_chipselect) {
> >>>>> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
> >>>>> num_chipselect (%d)\n",
> >>>>> + nc, rc);
> >>>>> + return rc;
> >>>>> + }
> >>>>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
> >>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> >>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
> multi
> >>>> CS\n");
> >>>>> + return -EINVAL;
> >>>>> + }
> >>>>> + for (idx = 0; idx < rc; idx++)
> >>>>> + spi_set_chipselect(spi, idx, cs[idx]);
> >>>>> +
> >>>>> + /* spi->chip_select[i] gives the corresponding physical CS for
> >>>>> +logical CS
> >>>> i
> >>>>> + * logical CS number is represented by setting the ith bit in
> >>>>> +spi-
> >>>>> cs_index_mask
> >>>>> + * So, for example, if spi->cs_index_mask = 0x01 then logical
> CS
> >>>> number is 0 and
> >>>>> + * spi->chip_select[0] will give the physical CS.
> >>>>> + * By default spi->chip_select[0] will hold the physical CS
> >>>>> +number so,
> >>>> set
> >>>>> + * spi->cs_index_mask as 0x01.
> >>>>> + */
> >>>>> + spi->cs_index_mask = 0x01;
> >>>>>
> >>>>> /* Device speed */
> >>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
> >>>>> @@
> >>>>> -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller
> *ctlr)
> >>>>> struct boardinfo *bi;
> >>>>> int first_dynamic;
> >>>>> int status;
> >>>>> + int idx;
> >>>>>
> >>>>> if (!dev)
> >>>>> return -ENODEV;
> >>>>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct
> >>>>> spi_controller
> >>>> *ctlr)
> >>>>> }
> >>>>>
> >>>>> /* Setting last_cs to -1 means no chip selected */
> >>>>> - ctlr->last_cs = -1;
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>> + ctlr->last_cs[idx] = -1;
> >>>>>
> >>>>> status = device_add(&ctlr->dev);
> >>>>> if (status < 0)
> >>>>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device
> >>>>> *spi,
> >>>> struct spi_message *message)
> >>>>> * cs_change is set for each transfer.
> >>>>> */
> >>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> >>>> SPI_CS_WORD) ||
> >>>>> - spi_get_csgpiod(spi, 0))) {
> >>>>> + spi_is_csgpiod(spi))) {
> >>>>> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
> >>>>> int ret;
> >>>>>
> >>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> >>>>> index 7b4baff63c5c..871d3a6d879b 100644
> >>>>> --- a/include/linux/spi/spi.h
> >>>>> +++ b/include/linux/spi/spi.h
> >>>>> @@ -20,6 +20,9 @@
> >>>>>
> >>>>> #include <uapi/linux/spi/spi.h>
> >>>>>
> >>>>> +/* Max no. of CS supported per spi device */ #define
> >>>>> +SPI_CS_CNT_MAX
> >>>>> +4
> >>>>> +
> >>>>> struct dma_chan;
> >>>>> struct software_node;
> >>>>> struct ptp_system_timestamp;
> >>>>> @@ -132,7 +135,8 @@ extern void
> >>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>> * @max_speed_hz: Maximum clock rate to be used with this chip
> >>>>> * (on this board); may be changed by the device's driver.
> >>>>> * The spi_transfer.speed_hz can override this for each transfer.
> >>>>> - * @chip_select: Chipselect, distinguishing chips handled by
> @controller.
> >>>>> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
> >>>>> + * the corresponding physical CS for logical CS i.
> >>>>> * @mode: The spi mode defines how data is clocked out and in.
> >>>>> * This may be changed by the device's driver.
> >>>>> * The "active low" default for chipselect mode can be
> overridden
> >>>>> @@ -157,8 +161,8 @@ extern void
> >>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>> * the device will bind to the named driver and only the named
> driver.
> >>>>> * Do not set directly, because core frees it; use
> driver_set_override() to
> >>>>> * set or clear it.
> >>>>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional,
> >>>>> NULL
> >> when
> >>>>> - * not using a GPIO line)
> >>>>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding
> >>>>> + chipselect
> >>>> lines
> >>>>> + * (optional, NULL when not using a GPIO line)
> >>>>> * @word_delay: delay to be inserted between consecutive
> >>>>> * words of a transfer
> >>>>> * @cs_setup: delay to be introduced by the controller after
> >>>>> CS is asserted @@ -167,6 +171,7 @@ extern void
> >>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>> * deasserted. If @cs_change_delay is used from @spi_transfer,
> then
> >>>> the
> >>>>> * two delays will be added up.
> >>>>> * @pcpu_statistics: statistics for the spi_device
> >>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> >>>>> + chipselect array
> >>>>> *
> >>>>> * A @spi_device is used to interchange data between an SPI slave
> >>>>> * (usually a discrete chip) and CPU memory.
> >>>>> @@ -182,7 +187,7 @@ struct spi_device {
> >>>>> struct spi_controller *controller;
> >>>>> struct spi_controller *master; /* Compatibility layer
> */
> >>>>> u32 max_speed_hz;
> >>>>> - u8 chip_select;
> >>>>> + u8 chip_select[SPI_CS_CNT_MAX];
> >>>>> u8 bits_per_word;
> >>>>> bool rt;
> >>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
> >>>>> @@ -213,7 +218,7 @@ struct spi_device {
> >>>>> void *controller_data;
> >>>>> char modalias[SPI_NAME_SIZE];
> >>>>> const char *driver_override;
> >>>>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor
> >>>> */
> >>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> Chip select
> >>>> gpio desc */
> >>>>> struct spi_delay word_delay; /* Inter-word delay */
> >>>>> /* CS delays */
> >>>>> struct spi_delay cs_setup;
> >>>>> @@ -223,6 +228,13 @@ struct spi_device {
> >>>>> /* The statistics */
> >>>>> struct spi_statistics __percpu *pcpu_statistics;
> >>>>>
> >>>>> + /* Bit mask of the chipselect(s) that the driver need to use
> from
> >>>>> + * the chipselect array.When the controller is capable to
> handle
> >>>>> + * multiple chip selects & memories are connected in parallel
> >>>>> + * then more than one bit need to be set in cs_index_mask.
> >>>>> + */
> >>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> >>>>> +
> >>>>> /*
> >>>>> * Likely need more hooks for more protocol options affecting
> how
> >>>>> * the controller talks to each chip, like:
> >>>>> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const
> >>>>> struct spi_device *spi)
> >>>>>
> >>>>> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
> >>>>> {
> >>>>> - return spi->chip_select;
> >>>>> + return spi->chip_select[idx];
> >>>>> }
> >>>>>
> >>>>> static inline void spi_set_chipselect(struct spi_device *spi,
> >>>>> u8 idx, u8
> >>>> chipselect)
> >>>>> {
> >>>>> - spi->chip_select = chipselect;
> >>>>> + spi->chip_select[idx] = chipselect;
> >>>>> }
> >>>>>
> >>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
> >>>>> spi_device *spi,
> >>>> u8 idx)
> >>>>> {
> >>>>> - return spi->cs_gpiod;
> >>>>> + return spi->cs_gpiod[idx];
> >>>>> }
> >>>>>
> >>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
> >>>>> idx, struct
> >>>> gpio_desc *csgpiod)
> >>>>> {
> >>>>> - spi->cs_gpiod = csgpiod;
> >>>>> + spi->cs_gpiod[idx] = csgpiod;
> >>>>> +}
> >>>>> +
> >>>>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
> >>>>> + u8 idx;
> >>>>> +
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + if (spi_get_csgpiod(spi, idx))
> >>>>> + return true;
> >>>>> + }
> >>>>> + return false;
> >>>>> }
> >>>>>
> >>>>> /**
> >>>>> @@ -399,6 +422,8 @@ extern struct spi_device
> >>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> >>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
> >>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> >>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
> >>>>> exclusive use
> >>>>> + * @multi_cs_cap: indicates that the SPI Controller can assert/de-
> assert
> >>>>> + * more than one chip select at once.
> >>>>> * @setup: updates the device mode and clocking records used by a
> >>>>> * device's SPI controller; protocol code may call this. This
> >>>>> * must fail if an unrecognized or unsupported mode is
> requested.
> >>>>> @@ -567,6 +592,11 @@ struct spi_controller {
> >>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
> >> */
> >>>>> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS
> >> must
> >>>> select slave */
> >>>>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
> >>>> suspended */
> >>>>> + /*
> >>>>> + * The spi-controller has multi chip select capability and can
> >>>>> + * assert/de-assert more than one chip select at once.
> >>>>> + */
> >>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
> >>>>>
> >>>>> /* Flag indicating if the allocation of this struct is devres-
> managed */
> >>>>> bool devm_allocated;
> >>>>> @@ -677,7 +707,8 @@ struct spi_controller {
> >>>>> bool rt;
> >>>>> bool auto_runtime_pm;
> >>>>> bool cur_msg_mapped;
> >>>>> - char last_cs;
> >>>>> + char last_cs[SPI_CS_CNT_MAX];
> >>>>> + char last_cs_index_mask;
> >>>>> bool last_cs_mode_high;
> >>>>> bool fallback;
> >>>>> struct completion xfer_completion;
On 21/11/2023 19:18, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Tuesday, November 21, 2023 11:07 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>; linux-
>> [email protected]; git (AMD-Xilinx) <[email protected]>;
>> [email protected]; [email protected]
>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>>
>>
>> On 21/11/2023 16:35, Mahapatra, Amit Kumar wrote:
>>> Hello Stefan,
>>>
>>>> -----Original Message-----
>>>> From: Stefan Binding <[email protected]>
>>>> Sent: Tuesday, November 21, 2023 7:28 PM
>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]; [email protected]
>>>> Cc: [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; Simek, Michal <[email protected]>;
>>>> linux- [email protected]; git (AMD-Xilinx)
>>>> <[email protected]>; [email protected];
>>>> [email protected]
>>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
>>>> SPI core
>>>>
>>>>
>>>> On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
>>>>> Hello Stefan,
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Stefan Binding <[email protected]>
>>>>>> Sent: Monday, November 20, 2023 8:00 PM
>>>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>>>> [email protected]; [email protected]; [email protected];
>>>>>> [email protected]; [email protected]; [email protected]
>>>>>> Cc: [email protected]; [email protected];
>>>>>> [email protected]; [email protected];
>>>>>> [email protected]; [email protected];
>>>>>> [email protected]; Simek, Michal <[email protected]>;
>>>>>> linux- [email protected]; git (AMD-Xilinx)
>>>>>> <[email protected]>; [email protected];
>>>>>> [email protected]
>>>>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
>>>>>> SPI core
>>>>>>
>>>>>>
>>>>>> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
>>>>>>> AMD-Xilinx GQSPI controller has two advanced mode that allows the
>>>>>>> controller to consider two flashes as one single device.
>>>>>>>
>>>>>>> One of these two mode is the parallel mode in which each byte of
>>>>>>> data is stored in both devices, the even bits in the lower flash &
>>>>>>> the odd bits in the upper flash. The byte split is automatically
>>>>>>> handled by the QSPI controller.
>>>>>>>
>>>>>>> The other mode is the stacked mode in which both the flashes share
>>>>>>> the same SPI bus but each of the device contain half of the data.
>>>>>>> In this mode, the controller does not follow CS requests but
>>>>>>> instead internally wires the two CS levels with the value of the
>>>>>>> most significant
>>>>>> address bit.
>>>>>>> For supporting both these modes SPI core need to be updated for
>>>>>>> providing multiple CS for a single SPI device.
>>>>>>>
>>>>>>> For adding multi CS support the SPI device need to be aware of all
>>>>>>> the CS values. So, the "chip_select" member in the spi_device
>>>>>>> structure is now an array that holds all the CS values.
>>>>>>>
>>>>>>> spi_device structure now has a "cs_index_mask" member. This acts
>>>>>>> as an index to the chip_select array. If nth bit of
>>>>>>> spi->cs_index_mask is set then the driver would assert spi-
>>> chip_select[n].
>>>>>>> In parallel mode all the chip selects are asserted/de-asserted
>>>>>>> simultaneously and each byte of data is stored in both devices,
>>>>>>> the even bits in one, the odd bits in the other. The split is
>>>>>>> automatically handled by the GQSPI controller. The GQSPI
>>>>>>> controller supports a maximum of two flashes connected in parallel
>>>>>>> mode. A SPI_CONTROLLER_MULTI_CS flag bit is added in the spi
>>>>>>> controller flags, through ctlr->flags the spi core will make sure
>>>>>>> that the controller is capable of handling multiple chip selects at once.
>>>>>>>
>>>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>>>>>> spi_device structure is now an array that holds the gpio
>>>>>>> descriptor for each chipselect.
>>>>>>>
>>>>>>> CS GPIO is not tested due to unavailability of necessary hardware
>> setup.
>>>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
>>>> [email protected]>
>>>>>>> ---
>>>>>>> Hello @Stefen,
>>>>>>> We restructured the SPI core implementation, for handling
>>>>>>> arbitrary number of devices connected in parallel(multi-cs) or stacked
>> mode.
>>>>>>> We have tested this updated patch on native-cs setup but couldn't
>>>>>>> test cs-gpio due to unavailability of a proper setup. If possible,
>>>>>>> could you please retest the cs-gpio use case with this updated
>>>>>>> patch and provide
>>>>>> your feedback.
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> I tested this chain on 2 different systems using GPIOs as chip
>>>>>> selects, and see the same error on both:
>>>>>> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
>>>>>>
>>>>>> Let me know if you need any further testing.
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> Stefan Binding
>>>>>>
>>>>>>> ---
>>>>>>> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++-------
>> --
>>>>>>> include/linux/spi/spi.h | 51 ++++++++---
>>>>>>> 2 files changed, 191 insertions(+), 52 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>>>>>> 8ead7acb99f3..ff66147ba95f 100644
>>>>>>> --- a/drivers/spi/spi.c
>>>>>>> +++ b/drivers/spi/spi.c
>>>>>>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device *dev,
>>>>>>> void
>>>>>> *data)
>>>>>>> {
>>>>>>> struct spi_device *spi = to_spi_device(dev);
>>>>>>> struct spi_device *new_spi = data;
>>>>>>> -
>>>>>>> - if (spi->controller == new_spi->controller &&
>>>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
>>>>>>> - return -EBUSY;
>>>>>>> + int idx, nw_idx;
>>>>>>> + u8 cs, cs_nw;
>>>>>>> +
>>>>>>> + if (spi->controller == new_spi->controller) {
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>>>>>> nw_idx++) {
>>>>>>> + cs_nw = spi_get_chipselect(spi,
>> nw_idx);
>>>>> Thank you for dedicating your time to test my patch.
>>>>> As per my analysis the error is reported from here as we are
>>>>> supplying the former SPI device structure to retrieve the CS value
>>>>> for the new SPI devices.
>>>>> To fix this, could you kindly substitute the above line with
>>>>>
>>>>> cs_nw = spi_get_chipselect(new_spi, nw_idx);
>>>>>
>>>>> and rerun your tests?
>>>>> If it works correctly, I will incorporate this fix into my upcoming
>>>>> series.
>>>>>
>>>>> Regards,
>>>>> Amit
>> Hi,
>>
>> I've attached my log.
>> I notice that you add a print to of_spi_parse_dt, however since the laptop I
>> am using is an x86 laptop, it uses ACPI rather than OF, and I don't think this
>> function isnt even compiled in.
> That’s correct, I missed it.
> Upon reviewing the logs, I discovered that in the ACPI flow, I am not
> initializing the unused CS[] to FF, as I am doing in the OF flow.
> Consequently, in the ACPI flow, all the unused CS[] are automatically
> initialized to 0. During the __spi_add_device process, the SPI core faces
> difficulty distinguishing between a valid CS value of 0 and an unused CS
> value of 0, leading to a failure in the driver probe.
>
> Incorporating the following modifications should resolve this issue.
> Kindly apply these changes on top of 1/8 and re-run the test.
>
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index ff66147ba95f..d0301c17d4f8 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -619,7 +619,7 @@ static int spi_dev_check(struct device *dev, void *data)
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> cs = spi_get_chipselect(spi, idx);
> for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> - cs_nw = spi_get_chipselect(spi, nw_idx);
> + cs_nw = spi_get_chipselect(new_spi, nw_idx);
> if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> dev_err(dev, "chipselect %d already in use\n", cs_nw);
> return -EBUSY;
> @@ -764,6 +764,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
> {
> struct spi_device *proxy;
> int status;
> + u8 idx;
>
> /*
> * NOTE: caller did any chip->bus_num checks necessary.
> @@ -779,6 +780,9 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
>
> WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(proxy, idx, 0xFF);
> +
> spi_set_chipselect(proxy, 0, chip->chip_select);
> proxy->max_speed_hz = chip->max_speed_hz;
> proxy->mode = chip->mode;
> @@ -2514,6 +2518,7 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
> struct spi_controller *ctlr = spi->controller;
> struct spi_device *ancillary;
> int rc = 0;
> + u8 idx;
>
> /* Alloc an spi_device */
> ancillary = spi_alloc_device(ctlr);
> @@ -2524,6 +2529,9 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
>
> strscpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias));
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(ancillary, idx, 0xFF);
> +
> /* Use provided chip-select for ancillary device */
> spi_set_chipselect(ancillary, 0, chip_select);
>
> @@ -2732,6 +2740,7 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
> struct acpi_spi_lookup lookup = {};
> struct spi_device *spi;
> int ret;
> + u8 idx;
>
> if (!ctlr && index == -1)
> return ERR_PTR(-EINVAL);
> @@ -2767,6 +2776,9 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
> return ERR_PTR(-ENOMEM);
> }
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(spi, idx, 0xFF);
> +
> ACPI_COMPANION_SET(&spi->dev, adev);
> spi->max_speed_hz = lookup.max_speed_hz;
> spi->mode |= lookup.mode;
>
> Regards,
> Amit
>
Hi,
I no longer see that error, or any errors printed from SPI, however, all
of the transactions are now broken.
Every transaction seems to read back 0x0, on all SPI devices, whether
native CS or GPIO CS, and I dont see it toggling the CS GPIO anymore.
Thanks,
Stefan
>> Thanks,
>>
>> Stefan
>>
>>>> Hi,
>>>>
>>>> I still see the same error:
>>>>
>>>> [Â Â Â 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
>>> Thank you for the quick testing. For further analysis I have
>>> incorporated additional debug prints on top of 1/8 patch. The
>>> corresponding diff is shared below. Kindly implement the specified
>>> changes, rerun your test and share the kernel logs.
>>>
>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>> ff66147ba95f..7f59ea81593d 100644
>>> --- a/drivers/spi/spi.c
>>> +++ b/drivers/spi/spi.c
>>> @@ -618,8 +618,10 @@ static int spi_dev_check(struct device *dev, void
>> *data)
>>> if (spi->controller == new_spi->controller) {
>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> cs = spi_get_chipselect(spi, idx);
>>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
>>> + __LINE__, idx, cs);
>>> for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
>>> - cs_nw = spi_get_chipselect(spi, nw_idx);
>>> + cs_nw = spi_get_chipselect(new_spi, nw_idx);
>>> + printk("%s() [%d] CS_NEW[%d] =
>>> + [%d]\n", __func__, __LINE__, nw_idx, cs_nw);
>>> if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
>>> dev_err(dev, "chipselect %d already in use\n",
>> cs_nw);
>>> return -EBUSY; @@ -659,8
>>> +661,10 @@ static int __spi_add_device(struct spi_device *spi)
>>> */
>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> cs = spi_get_chipselect(spi, idx);
>>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
>>> + __LINE__, idx, cs);
>>> for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
>>> nw_cs = spi_get_chipselect(spi, nw_idx);
>>> + printk("%s() [%d] CS_NEW[%d] = [%d]\n",
>>> + __func__, __LINE__, nw_idx, nw_cs);
>>> if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
>>> dev_err(dev, "chipselect %d already in use\n", nw_cs);
>>> return -EBUSY; @@ -2401,6 +2405,9 @@
>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>>> for (idx = 0; idx < rc; idx++)
>>> spi_set_chipselect(spi, idx, cs[idx]);
>>>
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
>>> + __LINE__, idx, spi_get_chipselect(spi, idx));
>>> +
>>> /* spi->chip_select[i] gives the corresponding physical CS for logical CS i
>>> * logical CS number is represented by setting the ith bit in spi-
>>> cs_index_mask
>>> * So, for example, if spi->cs_index_mask = 0x01 then logical
>>> CS number is 0 and
>>>
>>> Regards,
>>> Amit
>>>
>>>> Thanks,
>>>>
>>>> Stefan
>>>>
>>>>>>> + if (cs != 0xFF && cs_nw != 0xFF && cs
>> ==
>>>>>> cs_nw) {
>>>>>>> + dev_err(dev, "chipselect %d
>> already in
>>>>>> use\n", cs_nw);
>>>>>>> + return -EBUSY;
>>>>>>> + }
>>>>>>> + }
>>>>>>> + }
>>>>>>> + }
>>>>>>> return 0;
>>>>>>> }
>>>>>>>
>>>>>>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct
>>>>>>> spi_device
>>>> *spi)
>>>>>>> {
>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>> - int status;
>>>>>>> + int status, idx, nw_idx;
>>>>>>> + u8 cs, nw_cs;
>>>>>>> +
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>>>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
>>>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>>> spi_get_chipselect(spi, idx),
>>>>>>> + ctlr->num_chipselect);
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> + }
>>>>>>>
>>>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>>>> - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
>>>>>>> - ctlr->num_chipselect);
>>>>>>> - return -EINVAL;
>>>>>>> + /*
>>>>>>> + * Make sure that multiple logical CS doesn't map to the same
>>>>>> physical CS.
>>>>>>> + * For example, spi->chip_select[0] != spi->chip_select[1] and
>> so on.
>>>>>>> + */
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>>>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX;
>> nw_idx++) {
>>>>>>> + nw_cs = spi_get_chipselect(spi, nw_idx);
>>>>>>> + if (cs != 0xFF && nw_cs != 0xFF && cs ==
>> nw_cs) {
>>>>>>> + dev_err(dev, "chipselect %d already in
>> use\n",
>>>>>> nw_cs);
>>>>>>> + return -EBUSY;
>>>>>>> + }
>>>>>>> + }
>>>>>>> }
>>>>>>>
>>>>>>> /* Set the bus ID string */
>>>>>>> @@ -647,11 +677,8 @@ static int __spi_add_device(struct spi_device
>>>> *spi)
>>>>>>> * its configuration.
>>>>>>> */
>>>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
>> spi_dev_check);
>>>>>>> - if (status) {
>>>>>>> - dev_err(dev, "chipselect %d already in use\n",
>>>>>>> - spi_get_chipselect(spi, 0));
>>>>>>> + if (status)
>>>>>>> return status;
>>>>>>> - }
>>>>>>>
>>>>>>> /* Controller may unregister concurrently */
>>>>>>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8
>> +686,15 @@
>>>>>> static
>>>>>>> int __spi_add_device(struct spi_device *spi)
>>>>>>> return -ENODEV;
>>>>>>> }
>>>>>>>
>>>>>>> - if (ctlr->cs_gpiods)
>>>>>>> - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi,
>>>>>> 0)]);
>>>>>>> + if (ctlr->cs_gpiods) {
>>>>>>> + u8 cs;
>>>>>>> +
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + cs = spi_get_chipselect(spi, idx);
>>>>>>> + if (cs != 0xFF)
>>>>>>> + spi_set_csgpiod(spi, idx, ctlr-
>>> cs_gpiods[cs]);
>>>>>>> + }
>>>>>>> + }
>>>>>>>
>>>>>>> /*
>>>>>>> * Drivers may modify this initial i/o setup, but will @@
>>>>>>> -701,6
>>>>>>> +735,9 @@ int spi_add_device(struct spi_device *spi)
>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>> int status;
>>>>>>>
>>>>>>> + /* Set the bus ID string */
>>>>>>> + spi_dev_set_name(spi);
>>>>>>> +
>>>>>>> mutex_lock(&ctlr->add_lock);
>>>>>>> status = __spi_add_device(spi);
>>>>>>> mutex_unlock(&ctlr->add_lock); @@ -942,32 +979,51 @@
>> static
>>>>>>> void spi_res_release(struct spi_controller
>>>>>> *ctlr, struct spi_message *mes
>>>>>>> }
>>>>>>>
>>>>>>>
>>>>>>> /*----------------------------------------------------------------
>>>>>>> --
>>>>>>> --
>>>>>>> -----*/
>>>>>>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
>>>>>>> + u8 idx;
>>>>>>> + bool last = false;
>>>>>>> +
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + if ((spi->cs_index_mask >> idx) & 0x01) {
>>>>>>> + if (spi->controller->last_cs[idx] ==
>>>>>> spi_get_chipselect(spi, idx))
>>>>>>> + last = true;
>>>>>>> + }
>>>>>>> + }
>>>>>>> + return last;
>>>>>>> +}
>>>>>>> +
>>>>>>>
>>>>>>> static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
>>>>>>> {
>>>>>>> bool activate = enable;
>>>>>>> + u8 idx;
>>>>>>>
>>>>>>> /*
>>>>>>> * Avoid calling into the driver (or doing delays) if the chip
>> select
>>>>>>> * isn't actually changing from the last time this was called.
>>>>>>> */
>>>>>>> - if (!force && ((enable && spi->controller->last_cs ==
>>>>>> spi_get_chipselect(spi, 0)) ||
>>>>>>> - (!enable && spi->controller->last_cs !=
>>>>>> spi_get_chipselect(spi, 0))) &&
>>>>>>> + if (!force && ((enable && spi->controller->last_cs_index_mask
>> ==
>>>>>>> +spi-
>>>>>>> cs_index_mask &&
>>>>>>> + spi_is_last_cs(spi)) ||
>>>>>>> + (!enable && spi->controller->last_cs_index_mask
>> == spi-
>>>>>>> cs_index_mask &&
>>>>>>> + !spi_is_last_cs(spi))) &&
>>>>>>> (spi->controller->last_cs_mode_high == (spi->mode &
>>>>>> SPI_CS_HIGH)))
>>>>>>> return;
>>>>>>>
>>>>>>> trace_spi_set_cs(spi, activate);
>>>>>>>
>>>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
>>>>>>> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>>>> + spi->controller->last_cs[idx] = enable ?
>>>>>>> +spi_get_chipselect(spi,
>>>>>> 0)
>>>>>>> +: -1;
>>>>>>> spi->controller->last_cs_mode_high = spi->mode &
>> SPI_CS_HIGH;
>>>>>>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) &&
>>>>>> !activate)
>>>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>> -
>>>>>>> if (spi->mode & SPI_CS_HIGH)
>>>>>>> enable = !enable;
>>>>>>>
>>>>>>> - if (spi_get_csgpiod(spi, 0)) {
>>>>>>> + if (spi_is_csgpiod(spi)) {
>>>>>>> + if (!spi->controller->set_cs_timing && !activate)
>>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>> +
>>>>>>> if (!(spi->mode & SPI_NO_CS)) {
>>>>>>> /*
>>>>>>> * Historically ACPI has no means of the GPIO
>> polarity
>>>>>> and @@
>>>>>>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device *spi,
>>>>>>> bool
>>>>>> enable, bool force)
>>>>>>> * ambiguity. That's why we use enable, that
>> takes
>>>>>> SPI_CS_HIGH
>>>>>>> * into account.
>>>>>>> */
>>>>>>> - if (has_acpi_companion(&spi->dev))
>>>>>>> -
>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>>>>>> - else
>>>>>>> - /* Polarity handled by GPIO library */
>>>>>>> -
>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + if (((spi->cs_index_mask >> idx) &
>> 0x01) &&
>>>>>>> + spi_get_csgpiod(spi, idx)) {
>>>>>>> + if (has_acpi_companion(&spi-
>>> dev))
>>>>>>> +
>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>>>> +
>>>>>> !enable);
>>>>>>> + else
>>>>>>> + /* Polarity handled by
>> GPIO
>>>>>> library */
>>>>>>> +
>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>>>> +
>>>>>> activate);
>>>>>>> +
>>>>>>> + if (activate)
>>>>>>> + spi_delay_exec(&spi-
>>>>>>> cs_setup, NULL);
>>>>>>> + else
>>>>>>> + spi_delay_exec(&spi-
>>>>>>> cs_inactive, NULL);
>>>>>>> + }
>>>>>>> + }
>>>>>>> }
>>>>>>> /* Some SPI masters need both GPIO CS &
>> slave_select */
>>>>>>> if ((spi->controller->flags &
>> SPI_CONTROLLER_GPIO_SS) &&
>>>>>>> spi->controller->set_cs)
>>>>>>> spi->controller->set_cs(spi, !enable);
>>>>>>> +
>>>>>>> + if (!spi->controller->set_cs_timing) {
>>>>>>> + if (activate)
>>>>>>> + spi_delay_exec(&spi->cs_setup,
>> NULL);
>>>>>>> + else
>>>>>>> + spi_delay_exec(&spi->cs_inactive,
>> NULL);
>>>>>>> + }
>>>>>>> } else if (spi->controller->set_cs) {
>>>>>>> spi->controller->set_cs(spi, !enable);
>>>>>>> }
>>>>>>> -
>>>>>>> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
>>>>>>> - if (activate)
>>>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>>>>>> - else
>>>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>>>>>> - }
>>>>>>> }
>>>>>>>
>>>>>>> #ifdef CONFIG_HAS_DMA
>>>>>>> @@ -2222,8 +2290,8 @@ static void of_spi_parse_dt_cs_delay(struct
>>>>>> device_node *nc,
>>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
>>>>>>> spi_device
>>>> *spi,
>>>>>>> struct device_node *nc)
>>>>>>> {
>>>>>>> - u32 value;
>>>>>>> - int rc;
>>>>>>> + u32 value, cs[SPI_CS_CNT_MAX];
>>>>>>> + int rc, idx;
>>>>>>>
>>>>>>> /* Mode (clock phase/polarity/etc.) */
>>>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14
>>>>>>> +2363,52
>>>>>> @@
>>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device
>> *spi,
>>>>>>> return 0;
>>>>>>> }
>>>>>>>
>>>>>>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
>>>>>>> + dev_err(&ctlr->dev, "No. of CS is more than max. no.
>> of
>>>>>> supported CS\n");
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> +
>>>>>>> + /*
>>>>>>> + * Zero(0) is a valid physical CS value and can be located at
>> any
>>>>>>> + * logical CS in the spi->chip_select[]. If all the physical CS
>>>>>>> + * are initialized to 0 then It would be difficult to differentiate
>>>>>>> + * between a valid physical CS 0 & an unused logical CS whose
>>>>>> physical
>>>>>>> + * CS can be 0. As a solution to this issue initialize all the CS to
>> 0xFF.
>>>>>>> + * Now all the unused logical CS will have 0xFF physical CS
>>>>>>> +value & can
>>>>>> be
>>>>>>> + * ignore while performing physical CS validity checks.
>>>>>>> + */
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>>>> + spi_set_chipselect(spi, idx, 0xFF);
>>>>>>> +
>>>>>>> /* Device address */
>>>>>>> - rc = of_property_read_u32(nc, "reg", &value);
>>>>>>> - if (rc) {
>>>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
>> 1,
>>>>>>> + SPI_CS_CNT_MAX);
>>>>>>> + if (rc < 0) {
>>>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>>>>>> (%d)\n",
>>>>>>> nc, rc);
>>>>>>> return rc;
>>>>>>> }
>>>>>>> - spi_set_chipselect(spi, 0, value);
>>>>>>> + if (rc > ctlr->num_chipselect) {
>>>>>>> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
>>>>>>> num_chipselect (%d)\n",
>>>>>>> + nc, rc);
>>>>>>> + return rc;
>>>>>>> + }
>>>>>>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
>>>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
>> multi
>>>>>> CS\n");
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> + for (idx = 0; idx < rc; idx++)
>>>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>>>>>> +
>>>>>>> + /* spi->chip_select[i] gives the corresponding physical CS for
>>>>>>> +logical CS
>>>>>> i
>>>>>>> + * logical CS number is represented by setting the ith bit in
>>>>>>> +spi-
>>>>>>> cs_index_mask
>>>>>>> + * So, for example, if spi->cs_index_mask = 0x01 then logical
>> CS
>>>>>> number is 0 and
>>>>>>> + * spi->chip_select[0] will give the physical CS.
>>>>>>> + * By default spi->chip_select[0] will hold the physical CS
>>>>>>> +number so,
>>>>>> set
>>>>>>> + * spi->cs_index_mask as 0x01.
>>>>>>> + */
>>>>>>> + spi->cs_index_mask = 0x01;
>>>>>>>
>>>>>>> /* Device speed */
>>>>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
>>>>>>> @@
>>>>>>> -3100,6 +3206,7 @@ int spi_register_controller(struct spi_controller
>> *ctlr)
>>>>>>> struct boardinfo *bi;
>>>>>>> int first_dynamic;
>>>>>>> int status;
>>>>>>> + int idx;
>>>>>>>
>>>>>>> if (!dev)
>>>>>>> return -ENODEV;
>>>>>>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct
>>>>>>> spi_controller
>>>>>> *ctlr)
>>>>>>> }
>>>>>>>
>>>>>>> /* Setting last_cs to -1 means no chip selected */
>>>>>>> - ctlr->last_cs = -1;
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>>>> + ctlr->last_cs[idx] = -1;
>>>>>>>
>>>>>>> status = device_add(&ctlr->dev);
>>>>>>> if (status < 0)
>>>>>>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct spi_device
>>>>>>> *spi,
>>>>>> struct spi_message *message)
>>>>>>> * cs_change is set for each transfer.
>>>>>>> */
>>>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>>>>>> SPI_CS_WORD) ||
>>>>>>> - spi_get_csgpiod(spi, 0))) {
>>>>>>> + spi_is_csgpiod(spi))) {
>>>>>>> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
>>>>>>> int ret;
>>>>>>>
>>>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
>>>>>>> index 7b4baff63c5c..871d3a6d879b 100644
>>>>>>> --- a/include/linux/spi/spi.h
>>>>>>> +++ b/include/linux/spi/spi.h
>>>>>>> @@ -20,6 +20,9 @@
>>>>>>>
>>>>>>> #include <uapi/linux/spi/spi.h>
>>>>>>>
>>>>>>> +/* Max no. of CS supported per spi device */ #define
>>>>>>> +SPI_CS_CNT_MAX
>>>>>>> +4
>>>>>>> +
>>>>>>> struct dma_chan;
>>>>>>> struct software_node;
>>>>>>> struct ptp_system_timestamp;
>>>>>>> @@ -132,7 +135,8 @@ extern void
>>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>>>> * @max_speed_hz: Maximum clock rate to be used with this chip
>>>>>>> * (on this board); may be changed by the device's driver.
>>>>>>> * The spi_transfer.speed_hz can override this for each transfer.
>>>>>>> - * @chip_select: Chipselect, distinguishing chips handled by
>> @controller.
>>>>>>> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
>>>>>>> + * the corresponding physical CS for logical CS i.
>>>>>>> * @mode: The spi mode defines how data is clocked out and in.
>>>>>>> * This may be changed by the device's driver.
>>>>>>> * The "active low" default for chipselect mode can be
>> overridden
>>>>>>> @@ -157,8 +161,8 @@ extern void
>>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>>>> * the device will bind to the named driver and only the named
>> driver.
>>>>>>> * Do not set directly, because core frees it; use
>> driver_set_override() to
>>>>>>> * set or clear it.
>>>>>>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional,
>>>>>>> NULL
>>>> when
>>>>>>> - * not using a GPIO line)
>>>>>>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding
>>>>>>> + chipselect
>>>>>> lines
>>>>>>> + * (optional, NULL when not using a GPIO line)
>>>>>>> * @word_delay: delay to be inserted between consecutive
>>>>>>> * words of a transfer
>>>>>>> * @cs_setup: delay to be introduced by the controller after
>>>>>>> CS is asserted @@ -167,6 +171,7 @@ extern void
>>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>>>> * deasserted. If @cs_change_delay is used from @spi_transfer,
>> then
>>>>>> the
>>>>>>> * two delays will be added up.
>>>>>>> * @pcpu_statistics: statistics for the spi_device
>>>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>>>>>> + chipselect array
>>>>>>> *
>>>>>>> * A @spi_device is used to interchange data between an SPI slave
>>>>>>> * (usually a discrete chip) and CPU memory.
>>>>>>> @@ -182,7 +187,7 @@ struct spi_device {
>>>>>>> struct spi_controller *controller;
>>>>>>> struct spi_controller *master; /* Compatibility layer
>> */
>>>>>>> u32 max_speed_hz;
>>>>>>> - u8 chip_select;
>>>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>>>>>> u8 bits_per_word;
>>>>>>> bool rt;
>>>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>>>>>> @@ -213,7 +218,7 @@ struct spi_device {
>>>>>>> void *controller_data;
>>>>>>> char modalias[SPI_NAME_SIZE];
>>>>>>> const char *driver_override;
>>>>>>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor
>>>>>> */
>>>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
>> Chip select
>>>>>> gpio desc */
>>>>>>> struct spi_delay word_delay; /* Inter-word delay */
>>>>>>> /* CS delays */
>>>>>>> struct spi_delay cs_setup;
>>>>>>> @@ -223,6 +228,13 @@ struct spi_device {
>>>>>>> /* The statistics */
>>>>>>> struct spi_statistics __percpu *pcpu_statistics;
>>>>>>>
>>>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
>> from
>>>>>>> + * the chipselect array.When the controller is capable to
>> handle
>>>>>>> + * multiple chip selects & memories are connected in parallel
>>>>>>> + * then more than one bit need to be set in cs_index_mask.
>>>>>>> + */
>>>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>>>>>> +
>>>>>>> /*
>>>>>>> * Likely need more hooks for more protocol options affecting
>> how
>>>>>>> * the controller talks to each chip, like:
>>>>>>> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const
>>>>>>> struct spi_device *spi)
>>>>>>>
>>>>>>> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
>>>>>>> {
>>>>>>> - return spi->chip_select;
>>>>>>> + return spi->chip_select[idx];
>>>>>>> }
>>>>>>>
>>>>>>> static inline void spi_set_chipselect(struct spi_device *spi,
>>>>>>> u8 idx, u8
>>>>>> chipselect)
>>>>>>> {
>>>>>>> - spi->chip_select = chipselect;
>>>>>>> + spi->chip_select[idx] = chipselect;
>>>>>>> }
>>>>>>>
>>>>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
>>>>>>> spi_device *spi,
>>>>>> u8 idx)
>>>>>>> {
>>>>>>> - return spi->cs_gpiod;
>>>>>>> + return spi->cs_gpiod[idx];
>>>>>>> }
>>>>>>>
>>>>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
>>>>>>> idx, struct
>>>>>> gpio_desc *csgpiod)
>>>>>>> {
>>>>>>> - spi->cs_gpiod = csgpiod;
>>>>>>> + spi->cs_gpiod[idx] = csgpiod;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
>>>>>>> + u8 idx;
>>>>>>> +
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + if (spi_get_csgpiod(spi, idx))
>>>>>>> + return true;
>>>>>>> + }
>>>>>>> + return false;
>>>>>>> }
>>>>>>>
>>>>>>> /**
>>>>>>> @@ -399,6 +422,8 @@ extern struct spi_device
>>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>>>>>>> exclusive use
>>>>>>> + * @multi_cs_cap: indicates that the SPI Controller can assert/de-
>> assert
>>>>>>> + * more than one chip select at once.
>>>>>>> * @setup: updates the device mode and clocking records used by a
>>>>>>> * device's SPI controller; protocol code may call this. This
>>>>>>> * must fail if an unrecognized or unsupported mode is
>> requested.
>>>>>>> @@ -567,6 +592,11 @@ struct spi_controller {
>>>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
>>>> */
>>>>>>> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS
>>>> must
>>>>>> select slave */
>>>>>>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
>>>>>> suspended */
>>>>>>> + /*
>>>>>>> + * The spi-controller has multi chip select capability and can
>>>>>>> + * assert/de-assert more than one chip select at once.
>>>>>>> + */
>>>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
>>>>>>>
>>>>>>> /* Flag indicating if the allocation of this struct is devres-
>> managed */
>>>>>>> bool devm_allocated;
>>>>>>> @@ -677,7 +707,8 @@ struct spi_controller {
>>>>>>> bool rt;
>>>>>>> bool auto_runtime_pm;
>>>>>>> bool cur_msg_mapped;
>>>>>>> - char last_cs;
>>>>>>> + char last_cs[SPI_CS_CNT_MAX];
>>>>>>> + char last_cs_index_mask;
>>>>>>> bool last_cs_mode_high;
>>>>>>> bool fallback;
>>>>>>> struct completion xfer_completion;
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Wednesday, November 22, 2023 4:51 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>; linux-
> [email protected]; git (AMD-Xilinx) <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
>
>
> On 21/11/2023 19:18, Mahapatra, Amit Kumar wrote:
> > Hello Stefan,
> >
> >> -----Original Message-----
> >> From: Stefan Binding <[email protected]>
> >> Sent: Tuesday, November 21, 2023 11:07 PM
> >> To: Mahapatra, Amit Kumar <[email protected]>;
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected]
> >> Cc: [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Simek, Michal <[email protected]>;
> >> linux- [email protected]; git (AMD-Xilinx)
> >> <[email protected]>; [email protected];
> >> [email protected]
> >> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> >> SPI core
> >>
> >>
> >> On 21/11/2023 16:35, Mahapatra, Amit Kumar wrote:
> >>> Hello Stefan,
> >>>
> >>>> -----Original Message-----
> >>>> From: Stefan Binding <[email protected]>
> >>>> Sent: Tuesday, November 21, 2023 7:28 PM
> >>>> To: Mahapatra, Amit Kumar <[email protected]>;
> >>>> [email protected]; [email protected]; [email protected];
> >>>> [email protected]; [email protected]; [email protected]
> >>>> Cc: [email protected]; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected]; Simek, Michal <[email protected]>;
> >>>> linux- [email protected]; git (AMD-Xilinx)
> >>>> <[email protected]>; [email protected];
> >>>> [email protected]
> >>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> >>>> SPI core
> >>>>
> >>>>
> >>>> On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
> >>>>> Hello Stefan,
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: Stefan Binding <[email protected]>
> >>>>>> Sent: Monday, November 20, 2023 8:00 PM
> >>>>>> To: Mahapatra, Amit Kumar <[email protected]>;
> >>>>>> [email protected]; [email protected];
> >>>>>> [email protected]; [email protected]; [email protected];
> >>>>>> [email protected]
> >>>>>> Cc: [email protected]; [email protected];
> >>>>>> [email protected]; [email protected];
> >>>>>> [email protected]; [email protected];
> >>>>>> [email protected]; Simek, Michal
> <[email protected]>;
> >>>>>> linux- [email protected]; git (AMD-Xilinx)
> >>>>>> <[email protected]>; [email protected];
> >>>>>> [email protected]
> >>>>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support
> >>>>>> in SPI core
> >>>>>>
> >>>>>>
> >>>>>> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
> >>>>>>> AMD-Xilinx GQSPI controller has two advanced mode that allows
> >>>>>>> the controller to consider two flashes as one single device.
> >>>>>>>
> >>>>>>> One of these two mode is the parallel mode in which each byte of
> >>>>>>> data is stored in both devices, the even bits in the lower flash
> >>>>>>> & the odd bits in the upper flash. The byte split is
> >>>>>>> automatically handled by the QSPI controller.
> >>>>>>>
> >>>>>>> The other mode is the stacked mode in which both the flashes
> >>>>>>> share the same SPI bus but each of the device contain half of the
> data.
> >>>>>>> In this mode, the controller does not follow CS requests but
> >>>>>>> instead internally wires the two CS levels with the value of the
> >>>>>>> most significant
> >>>>>> address bit.
> >>>>>>> For supporting both these modes SPI core need to be updated for
> >>>>>>> providing multiple CS for a single SPI device.
> >>>>>>>
> >>>>>>> For adding multi CS support the SPI device need to be aware of
> >>>>>>> all the CS values. So, the "chip_select" member in the
> >>>>>>> spi_device structure is now an array that holds all the CS values.
> >>>>>>>
> >>>>>>> spi_device structure now has a "cs_index_mask" member. This acts
> >>>>>>> as an index to the chip_select array. If nth bit of
> >>>>>>> spi->cs_index_mask is set then the driver would assert spi-
> >>> chip_select[n].
> >>>>>>> In parallel mode all the chip selects are asserted/de-asserted
> >>>>>>> simultaneously and each byte of data is stored in both devices,
> >>>>>>> the even bits in one, the odd bits in the other. The split is
> >>>>>>> automatically handled by the GQSPI controller. The GQSPI
> >>>>>>> controller supports a maximum of two flashes connected in
> >>>>>>> parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is added in
> >>>>>>> the spi controller flags, through ctlr->flags the spi core will
> >>>>>>> make sure that the controller is capable of handling multiple chip
> selects at once.
> >>>>>>>
> >>>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
> >>>>>>> spi_device structure is now an array that holds the gpio
> >>>>>>> descriptor for each chipselect.
> >>>>>>>
> >>>>>>> CS GPIO is not tested due to unavailability of necessary
> >>>>>>> hardware
> >> setup.
> >>>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> >>>> [email protected]>
> >>>>>>> ---
> >>>>>>> Hello @Stefen,
> >>>>>>> We restructured the SPI core implementation, for handling
> >>>>>>> arbitrary number of devices connected in parallel(multi-cs) or
> >>>>>>> stacked
> >> mode.
> >>>>>>> We have tested this updated patch on native-cs setup but
> >>>>>>> couldn't test cs-gpio due to unavailability of a proper setup.
> >>>>>>> If possible, could you please retest the cs-gpio use case with
> >>>>>>> this updated patch and provide
> >>>>>> your feedback.
> >>>>>>
> >>>>>> Hi,
> >>>>>>
> >>>>>> I tested this chain on 2 different systems using GPIOs as chip
> >>>>>> selects, and see the same error on both:
> >>>>>> [Â Â Â 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in
> >>>>>> use
> >>>>>>
> >>>>>> Let me know if you need any further testing.
> >>>>>>
> >>>>>> Thanks,
> >>>>>>
> >>>>>> Stefan Binding
> >>>>>>
> >>>>>>> ---
> >>>>>>> drivers/spi/spi.c | 192 +++++++++++++++++++++++++++++++---
> ----
> >> --
> >>>>>>> include/linux/spi/spi.h | 51 ++++++++---
> >>>>>>> 2 files changed, 191 insertions(+), 52 deletions(-)
> >>>>>>>
> >>>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>>>>>> 8ead7acb99f3..ff66147ba95f 100644
> >>>>>>> --- a/drivers/spi/spi.c
> >>>>>>> +++ b/drivers/spi/spi.c
> >>>>>>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct device
> >>>>>>> *dev, void
> >>>>>> *data)
> >>>>>>> {
> >>>>>>> struct spi_device *spi = to_spi_device(dev);
> >>>>>>> struct spi_device *new_spi = data;
> >>>>>>> -
> >>>>>>> - if (spi->controller == new_spi->controller &&
> >>>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
> >>>>>>> - return -EBUSY;
> >>>>>>> + int idx, nw_idx;
> >>>>>>> + u8 cs, cs_nw;
> >>>>>>> +
> >>>>>>> + if (spi->controller == new_spi->controller) {
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> >>>>>> nw_idx++) {
> >>>>>>> + cs_nw = spi_get_chipselect(spi,
> >> nw_idx);
> >>>>> Thank you for dedicating your time to test my patch.
> >>>>> As per my analysis the error is reported from here as we are
> >>>>> supplying the former SPI device structure to retrieve the CS value
> >>>>> for the new SPI devices.
> >>>>> To fix this, could you kindly substitute the above line with
> >>>>>
> >>>>> cs_nw = spi_get_chipselect(new_spi, nw_idx);
> >>>>>
> >>>>> and rerun your tests?
> >>>>> If it works correctly, I will incorporate this fix into my
> >>>>> upcoming series.
> >>>>>
> >>>>> Regards,
> >>>>> Amit
> >> Hi,
> >>
> >> I've attached my log.
> >> I notice that you add a print to of_spi_parse_dt, however since the
> >> laptop I am using is an x86 laptop, it uses ACPI rather than OF, and
> >> I don't think this function isnt even compiled in.
> > That’s correct, I missed it.
> > Upon reviewing the logs, I discovered that in the ACPI flow, I am not
> > initializing the unused CS[] to FF, as I am doing in the OF flow.
> > Consequently, in the ACPI flow, all the unused CS[] are automatically
> > initialized to 0. During the __spi_add_device process, the SPI core
> > faces difficulty distinguishing between a valid CS value of 0 and an
> > unused CS value of 0, leading to a failure in the driver probe.
> >
> > Incorporating the following modifications should resolve this issue.
> > Kindly apply these changes on top of 1/8 and re-run the test.
> >
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > ff66147ba95f..d0301c17d4f8 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -619,7 +619,7 @@ static int spi_dev_check(struct device *dev, void
> *data)
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > cs = spi_get_chipselect(spi, idx);
> > for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> > - cs_nw = spi_get_chipselect(spi, nw_idx);
> > + cs_nw = spi_get_chipselect(new_spi,
> > + nw_idx);
> > if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> > dev_err(dev, "chipselect %d already in use\n",
> cs_nw);
> > return -EBUSY; @@ -764,6
> > +764,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
> > {
> > struct spi_device *proxy;
> > int status;
> > + u8 idx;
> >
> > /*
> > * NOTE: caller did any chip->bus_num checks necessary.
> > @@ -779,6 +780,9 @@ struct spi_device *spi_new_device(struct
> > spi_controller *ctlr,
> >
> > WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
> >
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + spi_set_chipselect(proxy, idx, 0xFF);
> > +
> > spi_set_chipselect(proxy, 0, chip->chip_select);
> > proxy->max_speed_hz = chip->max_speed_hz;
> > proxy->mode = chip->mode;
> > @@ -2514,6 +2518,7 @@ struct spi_device
> *spi_new_ancillary_device(struct spi_device *spi,
> > struct spi_controller *ctlr = spi->controller;
> > struct spi_device *ancillary;
> > int rc = 0;
> > + u8 idx;
> >
> > /* Alloc an spi_device */
> > ancillary = spi_alloc_device(ctlr); @@ -2524,6 +2529,9 @@
> > struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
> >
> > strscpy(ancillary->modalias, "dummy",
> > sizeof(ancillary->modalias));
> >
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + spi_set_chipselect(ancillary, idx, 0xFF);
> > +
> > /* Use provided chip-select for ancillary device */
> > spi_set_chipselect(ancillary, 0, chip_select);
> >
> > @@ -2732,6 +2740,7 @@ struct spi_device *acpi_spi_device_alloc(struct
> spi_controller *ctlr,
> > struct acpi_spi_lookup lookup = {};
> > struct spi_device *spi;
> > int ret;
> > + u8 idx;
> >
> > if (!ctlr && index == -1)
> > return ERR_PTR(-EINVAL); @@ -2767,6 +2776,9 @@ struct
> > spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
> > return ERR_PTR(-ENOMEM);
> > }
> >
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + spi_set_chipselect(spi, idx, 0xFF);
> > +
> > ACPI_COMPANION_SET(&spi->dev, adev);
> > spi->max_speed_hz = lookup.max_speed_hz;
> > spi->mode |= lookup.mode;
> >
> > Regards,
> > Amit
> >
>
> Hi,
>
> I no longer see that error, or any errors printed from SPI, however, all of the
> transactions are now broken.
> Every transaction seems to read back 0x0, on all SPI devices, whether native
> CS or GPIO CS, and I dont see it toggling the CS GPIO anymore.
I believe the issue stems from the fact that in the ACPI patch,
spi->cs_index_mask is not set to 0x01. As a result, in spi_set_cs,
it fails to meet the condition that governs the CS asset code snippet.
In the following code diff, I've included the necessary fix along with
the earlier changes on top of 1/8. I've also included a couple of debug
prints to aid in further debugging in case my analysis is incorrect.
Please apply these changes on top of 1/8 and re-run the test.
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ff66147ba95f..b2e035c3d494 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -619,7 +619,7 @@ static int spi_dev_check(struct device *dev, void *data)
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
cs = spi_get_chipselect(spi, idx);
for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
- cs_nw = spi_get_chipselect(spi, nw_idx);
+ cs_nw = spi_get_chipselect(new_spi, nw_idx);
if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
dev_err(dev, "chipselect %d already in use\n", cs_nw);
return -EBUSY;
@@ -764,6 +764,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
{
struct spi_device *proxy;
int status;
+ u8 idx;
/*
* NOTE: caller did any chip->bus_num checks necessary.
@@ -779,6 +780,9 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(proxy, idx, 0xFF);
+
spi_set_chipselect(proxy, 0, chip->chip_select);
proxy->max_speed_hz = chip->max_speed_hz;
proxy->mode = chip->mode;
@@ -787,6 +791,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr,
proxy->dev.platform_data = (void *) chip->platform_data;
proxy->controller_data = chip->controller_data;
proxy->controller_state = NULL;
+ proxy->cs_index_mask = 0x01;
if (chip->swnode) {
status = device_add_software_node(&proxy->dev, chip->swnode);
@@ -1024,6 +1029,8 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
if (!spi->controller->set_cs_timing && !activate)
spi_delay_exec(&spi->cs_hold, NULL);
+ printk("%s() [%d] spi->cs_index_mask == [%d]\n",__func__, __LINE__, spi->cs_index_mask);
+
if (!(spi->mode & SPI_NO_CS)) {
/*
* Historically ACPI has no means of the GPIO polarity and
@@ -1038,6 +1045,7 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
if (((spi->cs_index_mask >> idx) & 0x01) &&
spi_get_csgpiod(spi, idx)) {
+ printk("%s() [%d] idx == [%d]\n",__func__, __LINE__, idx);
if (has_acpi_companion(&spi->dev))
gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
!enable);
@@ -2514,6 +2522,7 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
struct spi_controller *ctlr = spi->controller;
struct spi_device *ancillary;
int rc = 0;
+ u8 idx;
/* Alloc an spi_device */
ancillary = spi_alloc_device(ctlr);
@@ -2524,12 +2533,16 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
strscpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias));
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(ancillary, idx, 0xFF);
+
/* Use provided chip-select for ancillary device */
spi_set_chipselect(ancillary, 0, chip_select);
/* Take over SPI mode/speed from SPI main device */
ancillary->max_speed_hz = spi->max_speed_hz;
ancillary->mode = spi->mode;
+ ancillary->cs_index_mask = 0x01;
WARN_ON(!mutex_is_locked(&ctlr->add_lock));
@@ -2732,6 +2745,7 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
struct acpi_spi_lookup lookup = {};
struct spi_device *spi;
int ret;
+ u8 idx;
if (!ctlr && index == -1)
return ERR_PTR(-EINVAL);
@@ -2767,12 +2781,16 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
return ERR_PTR(-ENOMEM);
}
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_chipselect(spi, idx, 0xFF);
+
ACPI_COMPANION_SET(&spi->dev, adev);
spi->max_speed_hz = lookup.max_speed_hz;
spi->mode |= lookup.mode;
spi->irq = lookup.irq;
spi->bits_per_word = lookup.bits_per_word;
spi_set_chipselect(spi, 0, lookup.chip_select);
+ spi->cs_index_mask = 0x01;
return spi;
}
Regards,
Amit
>
> Thanks,
>
> Stefan
>
> >> Thanks,
> >>
> >> Stefan
> >>
> >>>> Hi,
> >>>>
> >>>> I still see the same error:
> >>>>
> >>>> [Â Â Â 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
> >>> Thank you for the quick testing. For further analysis I have
> >>> incorporated additional debug prints on top of 1/8 patch. The
> >>> corresponding diff is shared below. Kindly implement the specified
> >>> changes, rerun your test and share the kernel logs.
> >>>
> >>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>> ff66147ba95f..7f59ea81593d 100644
> >>> --- a/drivers/spi/spi.c
> >>> +++ b/drivers/spi/spi.c
> >>> @@ -618,8 +618,10 @@ static int spi_dev_check(struct device *dev,
> >>> void
> >> *data)
> >>> if (spi->controller == new_spi->controller) {
> >>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> cs = spi_get_chipselect(spi, idx);
> >>> + printk("%s() [%d] CS[%d] = [%d]\n",
> >>> + __func__, __LINE__, idx, cs);
> >>> for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> >>> - cs_nw = spi_get_chipselect(spi, nw_idx);
> >>> + cs_nw = spi_get_chipselect(new_spi, nw_idx);
> >>> + printk("%s() [%d] CS_NEW[%d] =
> >>> + [%d]\n", __func__, __LINE__, nw_idx, cs_nw);
> >>> if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> >>> dev_err(dev, "chipselect
> >>> %d already in use\n",
> >> cs_nw);
> >>> return -EBUSY; @@ -659,8
> >>> +661,10 @@ static int __spi_add_device(struct spi_device *spi)
> >>> */
> >>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> cs = spi_get_chipselect(spi, idx);
> >>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> >>> + __LINE__, idx, cs);
> >>> for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> >>> nw_cs = spi_get_chipselect(spi, nw_idx);
> >>> + printk("%s() [%d] CS_NEW[%d] = [%d]\n",
> >>> + __func__, __LINE__, nw_idx, nw_cs);
> >>> if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> >>> dev_err(dev, "chipselect %d already in use\n", nw_cs);
> >>> return -EBUSY; @@ -2401,6 +2405,9
> >>> @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device
> *spi,
> >>> for (idx = 0; idx < rc; idx++)
> >>> spi_set_chipselect(spi, idx, cs[idx]);
> >>>
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> >>> + __LINE__, idx, spi_get_chipselect(spi, idx));
> >>> +
> >>> /* spi->chip_select[i] gives the corresponding physical CS for logical
> CS i
> >>> * logical CS number is represented by setting the ith bit
> >>> in spi- cs_index_mask
> >>> * So, for example, if spi->cs_index_mask = 0x01 then
> >>> logical CS number is 0 and
> >>>
> >>> Regards,
> >>> Amit
> >>>
> >>>> Thanks,
> >>>>
> >>>> Stefan
> >>>>
> >>>>>>> + if (cs != 0xFF && cs_nw != 0xFF && cs
> >> ==
> >>>>>> cs_nw) {
> >>>>>>> + dev_err(dev, "chipselect %d
> >> already in
> >>>>>> use\n", cs_nw);
> >>>>>>> + return -EBUSY;
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> return 0;
> >>>>>>> }
> >>>>>>>
> >>>>>>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct
> >>>>>>> spi_device
> >>>> *spi)
> >>>>>>> {
> >>>>>>> struct spi_controller *ctlr = spi->controller;
> >>>>>>> struct device *dev = ctlr->dev.parent;
> >>>>>>> - int status;
> >>>>>>> + int status, idx, nw_idx;
> >>>>>>> + u8 cs, nw_cs;
> >>>>>>> +
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + /* Chipselects are numbered 0..max; validate. */
> >>>>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>>>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
> >>>>>>> + dev_err(dev, "cs%d >= max %d\n",
> >>>>>> spi_get_chipselect(spi, idx),
> >>>>>>> + ctlr->num_chipselect);
> >>>>>>> + return -EINVAL;
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>>
> >>>>>>> - /* Chipselects are numbered 0..max; validate. */
> >>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>>>>>> - dev_err(dev, "cs%d >= max %d\n",
> spi_get_chipselect(spi, 0),
> >>>>>>> - ctlr->num_chipselect);
> >>>>>>> - return -EINVAL;
> >>>>>>> + /*
> >>>>>>> + * Make sure that multiple logical CS doesn't map to the same
> >>>>>> physical CS.
> >>>>>>> + * For example, spi->chip_select[0] != spi->chip_select[1] and
> >> so on.
> >>>>>>> + */
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>>>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX;
> >> nw_idx++) {
> >>>>>>> + nw_cs = spi_get_chipselect(spi, nw_idx);
> >>>>>>> + if (cs != 0xFF && nw_cs != 0xFF && cs ==
> >> nw_cs) {
> >>>>>>> + dev_err(dev, "chipselect %d already in
> >> use\n",
> >>>>>> nw_cs);
> >>>>>>> + return -EBUSY;
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> }
> >>>>>>>
> >>>>>>> /* Set the bus ID string */ @@ -647,11 +677,8 @@ static
> >>>>>>> int __spi_add_device(struct spi_device
> >>>> *spi)
> >>>>>>> * its configuration.
> >>>>>>> */
> >>>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> >> spi_dev_check);
> >>>>>>> - if (status) {
> >>>>>>> - dev_err(dev, "chipselect %d already in use\n",
> >>>>>>> - spi_get_chipselect(spi, 0));
> >>>>>>> + if (status)
> >>>>>>> return status;
> >>>>>>> - }
> >>>>>>>
> >>>>>>> /* Controller may unregister concurrently */
> >>>>>>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8
> >> +686,15 @@
> >>>>>> static
> >>>>>>> int __spi_add_device(struct spi_device *spi)
> >>>>>>> return -ENODEV;
> >>>>>>> }
> >>>>>>>
> >>>>>>> - if (ctlr->cs_gpiods)
> >>>>>>> - spi_set_csgpiod(spi, 0, ctlr-
> >cs_gpiods[spi_get_chipselect(spi,
> >>>>>> 0)]);
> >>>>>>> + if (ctlr->cs_gpiods) {
> >>>>>>> + u8 cs;
> >>>>>>> +
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + cs = spi_get_chipselect(spi, idx);
> >>>>>>> + if (cs != 0xFF)
> >>>>>>> + spi_set_csgpiod(spi, idx, ctlr-
> >>> cs_gpiods[cs]);
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>>
> >>>>>>> /*
> >>>>>>> * Drivers may modify this initial i/o setup, but will @@
> >>>>>>> -701,6
> >>>>>>> +735,9 @@ int spi_add_device(struct spi_device *spi)
> >>>>>>> struct spi_controller *ctlr = spi->controller;
> >>>>>>> int status;
> >>>>>>>
> >>>>>>> + /* Set the bus ID string */
> >>>>>>> + spi_dev_set_name(spi);
> >>>>>>> +
> >>>>>>> mutex_lock(&ctlr->add_lock);
> >>>>>>> status = __spi_add_device(spi);
> >>>>>>> mutex_unlock(&ctlr->add_lock); @@ -942,32 +979,51 @@
> >> static
> >>>>>>> void spi_res_release(struct spi_controller
> >>>>>> *ctlr, struct spi_message *mes
> >>>>>>> }
> >>>>>>>
> >>>>>>>
> >>>>>>> /*--------------------------------------------------------------
> >>>>>>> --
> >>>>>>> --
> >>>>>>> --
> >>>>>>> -----*/
> >>>>>>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
> >>>>>>> + u8 idx;
> >>>>>>> + bool last = false;
> >>>>>>> +
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + if ((spi->cs_index_mask >> idx) & 0x01) {
> >>>>>>> + if (spi->controller->last_cs[idx] ==
> >>>>>> spi_get_chipselect(spi, idx))
> >>>>>>> + last = true;
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> + return last;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>>
> >>>>>>> static void spi_set_cs(struct spi_device *spi, bool enable, bool
> force)
> >>>>>>> {
> >>>>>>> bool activate = enable;
> >>>>>>> + u8 idx;
> >>>>>>>
> >>>>>>> /*
> >>>>>>> * Avoid calling into the driver (or doing delays) if the
> >>>>>>> chip
> >> select
> >>>>>>> * isn't actually changing from the last time this was called.
> >>>>>>> */
> >>>>>>> - if (!force && ((enable && spi->controller->last_cs ==
> >>>>>> spi_get_chipselect(spi, 0)) ||
> >>>>>>> - (!enable && spi->controller->last_cs !=
> >>>>>> spi_get_chipselect(spi, 0))) &&
> >>>>>>> + if (!force && ((enable && spi->controller->last_cs_index_mask
> >> ==
> >>>>>>> +spi-
> >>>>>>> cs_index_mask &&
> >>>>>>> + spi_is_last_cs(spi)) ||
> >>>>>>> + (!enable && spi->controller->last_cs_index_mask
> >> == spi-
> >>>>>>> cs_index_mask &&
> >>>>>>> + !spi_is_last_cs(spi))) &&
> >>>>>>> (spi->controller->last_cs_mode_high == (spi->mode &
> >>>>>> SPI_CS_HIGH)))
> >>>>>>> return;
> >>>>>>>
> >>>>>>> trace_spi_set_cs(spi, activate);
> >>>>>>>
> >>>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -
> 1;
> >>>>>>> + spi->controller->last_cs_index_mask = spi->cs_index_mask;
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>>>> + spi->controller->last_cs[idx] = enable ?
> >>>>>>> +spi_get_chipselect(spi,
> >>>>>> 0)
> >>>>>>> +: -1;
> >>>>>>> spi->controller->last_cs_mode_high = spi->mode &
> >> SPI_CS_HIGH;
> >>>>>>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing)
> &&
> >>>>>> !activate)
> >>>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
> >>>>>>> -
> >>>>>>> if (spi->mode & SPI_CS_HIGH)
> >>>>>>> enable = !enable;
> >>>>>>>
> >>>>>>> - if (spi_get_csgpiod(spi, 0)) {
> >>>>>>> + if (spi_is_csgpiod(spi)) {
> >>>>>>> + if (!spi->controller->set_cs_timing && !activate)
> >>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>>>>>> +
> >>>>>>> if (!(spi->mode & SPI_NO_CS)) {
> >>>>>>> /*
> >>>>>>> * Historically ACPI has no means of the GPIO
> >> polarity
> >>>>>> and @@
> >>>>>>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device
> >>>>>>> *spi, bool
> >>>>>> enable, bool force)
> >>>>>>> * ambiguity. That's why we use enable, that
> >> takes
> >>>>>> SPI_CS_HIGH
> >>>>>>> * into account.
> >>>>>>> */
> >>>>>>> - if (has_acpi_companion(&spi->dev))
> >>>>>>> -
> >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> >>>>>>> - else
> >>>>>>> - /* Polarity handled by GPIO library */
> >>>>>>> -
> >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + if (((spi->cs_index_mask >> idx) &
> >> 0x01) &&
> >>>>>>> + spi_get_csgpiod(spi, idx)) {
> >>>>>>> + if (has_acpi_companion(&spi-
> >>> dev))
> >>>>>>> +
> >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>>>> +
> >>>>>> !enable);
> >>>>>>> + else
> >>>>>>> + /* Polarity handled by
> >> GPIO
> >>>>>> library */
> >>>>>>> +
> >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>>>> +
> >>>>>> activate);
> >>>>>>> +
> >>>>>>> + if (activate)
> >>>>>>> + spi_delay_exec(&spi-
> >>>>>>> cs_setup, NULL);
> >>>>>>> + else
> >>>>>>> + spi_delay_exec(&spi-
> >>>>>>> cs_inactive, NULL);
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> }
> >>>>>>> /* Some SPI masters need both GPIO CS &
> >> slave_select */
> >>>>>>> if ((spi->controller->flags &
> >> SPI_CONTROLLER_GPIO_SS) &&
> >>>>>>> spi->controller->set_cs)
> >>>>>>> spi->controller->set_cs(spi, !enable);
> >>>>>>> +
> >>>>>>> + if (!spi->controller->set_cs_timing) {
> >>>>>>> + if (activate)
> >>>>>>> + spi_delay_exec(&spi->cs_setup,
> >> NULL);
> >>>>>>> + else
> >>>>>>> + spi_delay_exec(&spi->cs_inactive,
> >> NULL);
> >>>>>>> + }
> >>>>>>> } else if (spi->controller->set_cs) {
> >>>>>>> spi->controller->set_cs(spi, !enable);
> >>>>>>> }
> >>>>>>> -
> >>>>>>> - if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
> >>>>>>> - if (activate)
> >>>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
> >>>>>>> - else
> >>>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
> >>>>>>> - }
> >>>>>>> }
> >>>>>>>
> >>>>>>> #ifdef CONFIG_HAS_DMA
> >>>>>>> @@ -2222,8 +2290,8 @@ static void
> >>>>>>> of_spi_parse_dt_cs_delay(struct
> >>>>>> device_node *nc,
> >>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr,
> >>>>>>> struct spi_device
> >>>> *spi,
> >>>>>>> struct device_node *nc)
> >>>>>>> {
> >>>>>>> - u32 value;
> >>>>>>> - int rc;
> >>>>>>> + u32 value, cs[SPI_CS_CNT_MAX];
> >>>>>>> + int rc, idx;
> >>>>>>>
> >>>>>>> /* Mode (clock phase/polarity/etc.) */
> >>>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14
> >>>>>>> +2363,52
> >>>>>> @@
> >>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> >>>>>>> spi_device
> >> *spi,
> >>>>>>> return 0;
> >>>>>>> }
> >>>>>>>
> >>>>>>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
> >>>>>>> + dev_err(&ctlr->dev, "No. of CS is more than max. no.
> >> of
> >>>>>> supported CS\n");
> >>>>>>> + return -EINVAL;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + /*
> >>>>>>> + * Zero(0) is a valid physical CS value and can be located at
> >> any
> >>>>>>> + * logical CS in the spi->chip_select[]. If all the physical CS
> >>>>>>> + * are initialized to 0 then It would be difficult to differentiate
> >>>>>>> + * between a valid physical CS 0 & an unused logical CS whose
> >>>>>> physical
> >>>>>>> + * CS can be 0. As a solution to this issue initialize all the
> >>>>>>> +CS to
> >> 0xFF.
> >>>>>>> + * Now all the unused logical CS will have 0xFF physical CS
> >>>>>>> +value & can
> >>>>>> be
> >>>>>>> + * ignore while performing physical CS validity checks.
> >>>>>>> + */
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>>>> + spi_set_chipselect(spi, idx, 0xFF);
> >>>>>>> +
> >>>>>>> /* Device address */
> >>>>>>> - rc = of_property_read_u32(nc, "reg", &value);
> >>>>>>> - if (rc) {
> >>>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
> >> 1,
> >>>>>>> + SPI_CS_CNT_MAX);
> >>>>>>> + if (rc < 0) {
> >>>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> >>>>>> (%d)\n",
> >>>>>>> nc, rc);
> >>>>>>> return rc;
> >>>>>>> }
> >>>>>>> - spi_set_chipselect(spi, 0, value);
> >>>>>>> + if (rc > ctlr->num_chipselect) {
> >>>>>>> + dev_err(&ctlr->dev, "%pOF has number of CS > ctlr-
> >>>>>>> num_chipselect (%d)\n",
> >>>>>>> + nc, rc);
> >>>>>>> + return rc;
> >>>>>>> + }
> >>>>>>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
> >>>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> >>>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
> >> multi
> >>>>>> CS\n");
> >>>>>>> + return -EINVAL;
> >>>>>>> + }
> >>>>>>> + for (idx = 0; idx < rc; idx++)
> >>>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
> >>>>>>> +
> >>>>>>> + /* spi->chip_select[i] gives the corresponding physical CS for
> >>>>>>> +logical CS
> >>>>>> i
> >>>>>>> + * logical CS number is represented by setting the ith bit in
> >>>>>>> +spi-
> >>>>>>> cs_index_mask
> >>>>>>> + * So, for example, if spi->cs_index_mask = 0x01 then logical
> >> CS
> >>>>>> number is 0 and
> >>>>>>> + * spi->chip_select[0] will give the physical CS.
> >>>>>>> + * By default spi->chip_select[0] will hold the physical CS
> >>>>>>> +number so,
> >>>>>> set
> >>>>>>> + * spi->cs_index_mask as 0x01.
> >>>>>>> + */
> >>>>>>> + spi->cs_index_mask = 0x01;
> >>>>>>>
> >>>>>>> /* Device speed */
> >>>>>>> if (!of_property_read_u32(nc, "spi-max-frequency",
> >>>>>>> &value)) @@
> >>>>>>> -3100,6 +3206,7 @@ int spi_register_controller(struct
> >>>>>>> spi_controller
> >> *ctlr)
> >>>>>>> struct boardinfo *bi;
> >>>>>>> int first_dynamic;
> >>>>>>> int status;
> >>>>>>> + int idx;
> >>>>>>>
> >>>>>>> if (!dev)
> >>>>>>> return -ENODEV;
> >>>>>>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct
> >>>>>>> spi_controller
> >>>>>> *ctlr)
> >>>>>>> }
> >>>>>>>
> >>>>>>> /* Setting last_cs to -1 means no chip selected */
> >>>>>>> - ctlr->last_cs = -1;
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>>>> + ctlr->last_cs[idx] = -1;
> >>>>>>>
> >>>>>>> status = device_add(&ctlr->dev);
> >>>>>>> if (status < 0)
> >>>>>>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct
> >>>>>>> spi_device *spi,
> >>>>>> struct spi_message *message)
> >>>>>>> * cs_change is set for each transfer.
> >>>>>>> */
> >>>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> >>>>>> SPI_CS_WORD) ||
> >>>>>>> - spi_get_csgpiod(spi, 0))) {
> >>>>>>> + spi_is_csgpiod(spi))) {
> >>>>>>> size_t maxsize = BITS_TO_BYTES(spi->bits_per_word);
> >>>>>>> int ret;
> >>>>>>>
> >>>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> >>>>>>> index 7b4baff63c5c..871d3a6d879b 100644
> >>>>>>> --- a/include/linux/spi/spi.h
> >>>>>>> +++ b/include/linux/spi/spi.h
> >>>>>>> @@ -20,6 +20,9 @@
> >>>>>>>
> >>>>>>> #include <uapi/linux/spi/spi.h>
> >>>>>>>
> >>>>>>> +/* Max no. of CS supported per spi device */ #define
> >>>>>>> +SPI_CS_CNT_MAX
> >>>>>>> +4
> >>>>>>> +
> >>>>>>> struct dma_chan;
> >>>>>>> struct software_node;
> >>>>>>> struct ptp_system_timestamp; @@ -132,7 +135,8 @@ extern
> >>>>>>> void
> >>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>>>> * @max_speed_hz: Maximum clock rate to be used with this chip
> >>>>>>> * (on this board); may be changed by the device's driver.
> >>>>>>> * The spi_transfer.speed_hz can override this for each transfer.
> >>>>>>> - * @chip_select: Chipselect, distinguishing chips handled by
> >> @controller.
> >>>>>>> + * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
> >>>>>>> + * the corresponding physical CS for logical CS i.
> >>>>>>> * @mode: The spi mode defines how data is clocked out and in.
> >>>>>>> * This may be changed by the device's driver.
> >>>>>>> * The "active low" default for chipselect mode can be
> >> overridden
> >>>>>>> @@ -157,8 +161,8 @@ extern void
> >>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>>>> * the device will bind to the named driver and only the named
> >> driver.
> >>>>>>> * Do not set directly, because core frees it; use
> >> driver_set_override() to
> >>>>>>> * set or clear it.
> >>>>>>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional,
> >>>>>>> NULL
> >>>> when
> >>>>>>> - * not using a GPIO line)
> >>>>>>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding
> >>>>>>> + chipselect
> >>>>>> lines
> >>>>>>> + * (optional, NULL when not using a GPIO line)
> >>>>>>> * @word_delay: delay to be inserted between consecutive
> >>>>>>> * words of a transfer
> >>>>>>> * @cs_setup: delay to be introduced by the controller
> >>>>>>> after CS is asserted @@ -167,6 +171,7 @@ extern void
> >>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>>>> * deasserted. If @cs_change_delay is used from @spi_transfer,
> >> then
> >>>>>> the
> >>>>>>> * two delays will be added up.
> >>>>>>> * @pcpu_statistics: statistics for the spi_device
> >>>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> >>>>>>> + chipselect array
> >>>>>>> *
> >>>>>>> * A @spi_device is used to interchange data between an SPI slave
> >>>>>>> * (usually a discrete chip) and CPU memory.
> >>>>>>> @@ -182,7 +187,7 @@ struct spi_device {
> >>>>>>> struct spi_controller *controller;
> >>>>>>> struct spi_controller *master; /* Compatibility layer
> >> */
> >>>>>>> u32 max_speed_hz;
> >>>>>>> - u8 chip_select;
> >>>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
> >>>>>>> u8 bits_per_word;
> >>>>>>> bool rt;
> >>>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
> >>>>>>> @@ -213,7 +218,7 @@ struct spi_device {
> >>>>>>> void *controller_data;
> >>>>>>> char modalias[SPI_NAME_SIZE];
> >>>>>>> const char *driver_override;
> >>>>>>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO
> descriptor
> >>>>>> */
> >>>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> >> Chip select
> >>>>>> gpio desc */
> >>>>>>> struct spi_delay word_delay; /* Inter-word delay */
> >>>>>>> /* CS delays */
> >>>>>>> struct spi_delay cs_setup;
> >>>>>>> @@ -223,6 +228,13 @@ struct spi_device {
> >>>>>>> /* The statistics */
> >>>>>>> struct spi_statistics __percpu *pcpu_statistics;
> >>>>>>>
> >>>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
> >> from
> >>>>>>> + * the chipselect array.When the controller is capable to
> >> handle
> >>>>>>> + * multiple chip selects & memories are connected in parallel
> >>>>>>> + * then more than one bit need to be set in cs_index_mask.
> >>>>>>> + */
> >>>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> >>>>>>> +
> >>>>>>> /*
> >>>>>>> * Likely need more hooks for more protocol options
> >>>>>>> affecting
> >> how
> >>>>>>> * the controller talks to each chip, like:
> >>>>>>> @@ -279,22 +291,33 @@ static inline void *spi_get_drvdata(const
> >>>>>>> struct spi_device *spi)
> >>>>>>>
> >>>>>>> static inline u8 spi_get_chipselect(const struct spi_device *spi, u8
> idx)
> >>>>>>> {
> >>>>>>> - return spi->chip_select;
> >>>>>>> + return spi->chip_select[idx];
> >>>>>>> }
> >>>>>>>
> >>>>>>> static inline void spi_set_chipselect(struct spi_device
> >>>>>>> *spi,
> >>>>>>> u8 idx, u8
> >>>>>> chipselect)
> >>>>>>> {
> >>>>>>> - spi->chip_select = chipselect;
> >>>>>>> + spi->chip_select[idx] = chipselect;
> >>>>>>> }
> >>>>>>>
> >>>>>>> static inline struct gpio_desc *spi_get_csgpiod(const
> >>>>>>> struct spi_device *spi,
> >>>>>> u8 idx)
> >>>>>>> {
> >>>>>>> - return spi->cs_gpiod;
> >>>>>>> + return spi->cs_gpiod[idx];
> >>>>>>> }
> >>>>>>>
> >>>>>>> static inline void spi_set_csgpiod(struct spi_device *spi,
> >>>>>>> u8 idx, struct
> >>>>>> gpio_desc *csgpiod)
> >>>>>>> {
> >>>>>>> - spi->cs_gpiod = csgpiod;
> >>>>>>> + spi->cs_gpiod[idx] = csgpiod;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
> >>>>>>> + u8 idx;
> >>>>>>> +
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + if (spi_get_csgpiod(spi, idx))
> >>>>>>> + return true;
> >>>>>>> + }
> >>>>>>> + return false;
> >>>>>>> }
> >>>>>>>
> >>>>>>> /**
> >>>>>>> @@ -399,6 +422,8 @@ extern struct spi_device
> >>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> >>>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
> >>>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> >>>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
> >>>>>>> exclusive use
> >>>>>>> + * @multi_cs_cap: indicates that the SPI Controller can
> >>>>>>> + assert/de-
> >> assert
> >>>>>>> + * more than one chip select at once.
> >>>>>>> * @setup: updates the device mode and clocking records used by
> a
> >>>>>>> * device's SPI controller; protocol code may call this. This
> >>>>>>> * must fail if an unrecognized or unsupported mode is
> >> requested.
> >>>>>>> @@ -567,6 +592,11 @@ struct spi_controller {
> >>>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /*
> Requires tx
> >>>> */
> >>>>>>> #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS
> >>>> must
> >>>>>> select slave */
> >>>>>>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently
> >>>>>> suspended */
> >>>>>>> + /*
> >>>>>>> + * The spi-controller has multi chip select capability and can
> >>>>>>> + * assert/de-assert more than one chip select at once.
> >>>>>>> + */
> >>>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
> >>>>>>>
> >>>>>>> /* Flag indicating if the allocation of this struct is
> >>>>>>> devres-
> >> managed */
> >>>>>>> bool devm_allocated;
> >>>>>>> @@ -677,7 +707,8 @@ struct spi_controller {
> >>>>>>> bool rt;
> >>>>>>> bool auto_runtime_pm;
> >>>>>>> bool cur_msg_mapped;
> >>>>>>> - char last_cs;
> >>>>>>> + char last_cs[SPI_CS_CNT_MAX];
> >>>>>>> + char last_cs_index_mask;
> >>>>>>> bool last_cs_mode_high;
> >>>>>>> bool fallback;
> >>>>>>> struct completion xfer_completion;
> -----Original Message-----
> From: Mahapatra, Amit Kumar <[email protected]>
> Sent: Wednesday, November 22, 2023 1:23 PM
> To: Stefan Binding <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>;
> [email protected]; git (AMD-Xilinx) <[email protected]>;
> [email protected]; [email protected]
> Subject: RE: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI
> core
>
>
>
> > -----Original Message-----
> > From: Stefan Binding <[email protected]>
> > Sent: Wednesday, November 22, 2023 4:51 PM
> > To: Mahapatra, Amit Kumar <[email protected]>;
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; Simek, Michal <[email protected]>;
> linux-
> > [email protected]; git (AMD-Xilinx) <[email protected]>;
> > [email protected]; [email protected]
> > Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI
> core
> >
> >
> > On 21/11/2023 19:18, Mahapatra, Amit Kumar wrote:
> > > Hello Stefan,
> > >
> > >> -----Original Message-----
> > >> From: Stefan Binding <[email protected]>
> > >> Sent: Tuesday, November 21, 2023 11:07 PM
> > >> To: Mahapatra, Amit Kumar <[email protected]>;
> > >> [email protected]; [email protected];
> [email protected];
> > >> [email protected]; [email protected]; [email protected]
> > >> Cc: [email protected]; [email protected];
> > >> [email protected]; [email protected];
> > >> [email protected]; [email protected];
> > >> [email protected]; Simek, Michal
> <[email protected]>;
> > >> linux- [email protected]; git (AMD-Xilinx)
> > >> <[email protected]>; [email protected];
> > >> [email protected]
> > >> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> > >> SPI core
> > >>
> > >>
> > >> On 21/11/2023 16:35, Mahapatra, Amit Kumar wrote:
> > >>> Hello Stefan,
> > >>>
> > >>>> -----Original Message-----
> > >>>> From: Stefan Binding <[email protected]>
> > >>>> Sent: Tuesday, November 21, 2023 7:28 PM
> > >>>> To: Mahapatra, Amit Kumar <[email protected]>;
> > >>>> [email protected]; [email protected];
> [email protected];
> > >>>> [email protected]; [email protected]; [email protected]
> > >>>> Cc: [email protected]; [email protected];
> > >>>> [email protected]; [email protected];
> > >>>> [email protected]; [email protected];
> > >>>> [email protected]; Simek, Michal
> <[email protected]>;
> > >>>> linux- [email protected]; git (AMD-Xilinx)
> > >>>> <[email protected]>; [email protected];
> > >>>> [email protected]
> > >>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in
> > >>>> SPI core
> > >>>>
> > >>>>
> > >>>> On 21/11/2023 07:39, Mahapatra, Amit Kumar wrote:
> > >>>>> Hello Stefan,
> > >>>>>
> > >>>>>> -----Original Message-----
> > >>>>>> From: Stefan Binding <[email protected]>
> > >>>>>> Sent: Monday, November 20, 2023 8:00 PM
> > >>>>>> To: Mahapatra, Amit Kumar <amit.kumar-
> [email protected]>;
> > >>>>>> [email protected]; [email protected];
> > >>>>>> [email protected]; [email protected];
> [email protected];
> > >>>>>> [email protected]
> > >>>>>> Cc: [email protected]; [email protected];
> > >>>>>> [email protected]; [email protected];
> > >>>>>> [email protected]; [email protected];
> > >>>>>> [email protected]; Simek, Michal
> > <[email protected]>;
> > >>>>>> linux- [email protected]; git (AMD-Xilinx)
> > >>>>>> <[email protected]>; [email protected];
> > >>>>>> [email protected]
> > >>>>>> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support
> > >>>>>> in SPI core
> > >>>>>>
> > >>>>>>
> > >>>>>> On 18/11/2023 13:54, Amit Kumar Mahapatra wrote:
> > >>>>>>> AMD-Xilinx GQSPI controller has two advanced mode that
> allows
> > >>>>>>> the controller to consider two flashes as one single device.
> > >>>>>>>
> > >>>>>>> One of these two mode is the parallel mode in which each byte
> of
> > >>>>>>> data is stored in both devices, the even bits in the lower flash
> > >>>>>>> & the odd bits in the upper flash. The byte split is
> > >>>>>>> automatically handled by the QSPI controller.
> > >>>>>>>
> > >>>>>>> The other mode is the stacked mode in which both the flashes
> > >>>>>>> share the same SPI bus but each of the device contain half of
> the
> > data.
> > >>>>>>> In this mode, the controller does not follow CS requests but
> > >>>>>>> instead internally wires the two CS levels with the value of the
> > >>>>>>> most significant
> > >>>>>> address bit.
> > >>>>>>> For supporting both these modes SPI core need to be updated
> for
> > >>>>>>> providing multiple CS for a single SPI device.
> > >>>>>>>
> > >>>>>>> For adding multi CS support the SPI device need to be aware of
> > >>>>>>> all the CS values. So, the "chip_select" member in the
> > >>>>>>> spi_device structure is now an array that holds all the CS values.
> > >>>>>>>
> > >>>>>>> spi_device structure now has a "cs_index_mask" member. This
> acts
> > >>>>>>> as an index to the chip_select array. If nth bit of
> > >>>>>>> spi->cs_index_mask is set then the driver would assert spi-
> > >>> chip_select[n].
> > >>>>>>> In parallel mode all the chip selects are asserted/de-asserted
> > >>>>>>> simultaneously and each byte of data is stored in both devices,
> > >>>>>>> the even bits in one, the odd bits in the other. The split is
> > >>>>>>> automatically handled by the GQSPI controller. The GQSPI
> > >>>>>>> controller supports a maximum of two flashes connected in
> > >>>>>>> parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is added
> in
> > >>>>>>> the spi controller flags, through ctlr->flags the spi core will
> > >>>>>>> make sure that the controller is capable of handling multiple
> chip
> > selects at once.
> > >>>>>>>
> > >>>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
> > >>>>>>> spi_device structure is now an array that holds the gpio
> > >>>>>>> descriptor for each chipselect.
> > >>>>>>>
> > >>>>>>> CS GPIO is not tested due to unavailability of necessary
> > >>>>>>> hardware
> > >> setup.
> > >>>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> > >>>> [email protected]>
> > >>>>>>> ---
> > >>>>>>> Hello @Stefen,
> > >>>>>>> We restructured the SPI core implementation, for handling
> > >>>>>>> arbitrary number of devices connected in parallel(multi-cs) or
> > >>>>>>> stacked
> > >> mode.
> > >>>>>>> We have tested this updated patch on native-cs setup but
> > >>>>>>> couldn't test cs-gpio due to unavailability of a proper setup.
> > >>>>>>> If possible, could you please retest the cs-gpio use case with
> > >>>>>>> this updated patch and provide
> > >>>>>> your feedback.
> > >>>>>>
> > >>>>>> Hi,
> > >>>>>>
> > >>>>>> I tested this chain on 2 different systems using GPIOs as chip
> > >>>>>> selects, and see the same error on both:
> > >>>>>> [ 2.842045] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in
> > >>>>>> use
> > >>>>>>
> > >>>>>> Let me know if you need any further testing.
> > >>>>>>
> > >>>>>> Thanks,
> > >>>>>>
> > >>>>>> Stefan Binding
> > >>>>>>
> > >>>>>>> ---
> > >>>>>>> drivers/spi/spi.c | 192
> +++++++++++++++++++++++++++++++---
> > ----
> > >> --
> > >>>>>>> include/linux/spi/spi.h | 51 ++++++++---
> > >>>>>>> 2 files changed, 191 insertions(+), 52 deletions(-)
> > >>>>>>>
> > >>>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > >>>>>>> 8ead7acb99f3..ff66147ba95f 100644
> > >>>>>>> --- a/drivers/spi/spi.c
> > >>>>>>> +++ b/drivers/spi/spi.c
> > >>>>>>> @@ -612,10 +612,21 @@ static int spi_dev_check(struct
> device
> > >>>>>>> *dev, void
> > >>>>>> *data)
> > >>>>>>> {
> > >>>>>>> struct spi_device *spi = to_spi_device(dev);
> > >>>>>>> struct spi_device *new_spi = data;
> > >>>>>>> -
> > >>>>>>> - if (spi->controller == new_spi->controller &&
> > >>>>>>> - spi_get_chipselect(spi, 0) ==
> spi_get_chipselect(new_spi, 0))
> > >>>>>>> - return -EBUSY;
> > >>>>>>> + int idx, nw_idx;
> > >>>>>>> + u8 cs, cs_nw;
> > >>>>>>> +
> > >>>>>>> + if (spi->controller == new_spi->controller) {
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>>>>>> + cs = spi_get_chipselect(spi, idx);
> > >>>>>>> + for (nw_idx = 0; nw_idx <
> SPI_CS_CNT_MAX;
> > >>>>>> nw_idx++) {
> > >>>>>>> + cs_nw = spi_get_chipselect(spi,
> > >> nw_idx);
> > >>>>> Thank you for dedicating your time to test my patch.
> > >>>>> As per my analysis the error is reported from here as we are
> > >>>>> supplying the former SPI device structure to retrieve the CS value
> > >>>>> for the new SPI devices.
> > >>>>> To fix this, could you kindly substitute the above line with
> > >>>>>
> > >>>>> cs_nw = spi_get_chipselect(new_spi, nw_idx);
> > >>>>>
> > >>>>> and rerun your tests?
> > >>>>> If it works correctly, I will incorporate this fix into my
> > >>>>> upcoming series.
> > >>>>>
> > >>>>> Regards,
> > >>>>> Amit
> > >> Hi,
> > >>
> > >> I've attached my log.
> > >> I notice that you add a print to of_spi_parse_dt, however since the
> > >> laptop I am using is an x86 laptop, it uses ACPI rather than OF, and
> > >> I don't think this function isnt even compiled in.
> > > That’s correct, I missed it.
> > > Upon reviewing the logs, I discovered that in the ACPI flow, I am not
> > > initializing the unused CS[] to FF, as I am doing in the OF flow.
> > > Consequently, in the ACPI flow, all the unused CS[] are automatically
> > > initialized to 0. During the __spi_add_device process, the SPI core
> > > faces difficulty distinguishing between a valid CS value of 0 and an
> > > unused CS value of 0, leading to a failure in the driver probe.
> > >
> > > Incorporating the following modifications should resolve this issue.
> > > Kindly apply these changes on top of 1/8 and re-run the test.
> > >
> > > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > > ff66147ba95f..d0301c17d4f8 100644
> > > --- a/drivers/spi/spi.c
> > > +++ b/drivers/spi/spi.c
> > > @@ -619,7 +619,7 @@ static int spi_dev_check(struct device *dev,
> void
> > *data)
> > > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > > cs = spi_get_chipselect(spi, idx);
> > > for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> > > - cs_nw = spi_get_chipselect(spi, nw_idx);
> > > + cs_nw = spi_get_chipselect(new_spi,
> > > + nw_idx);
> > > if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> > > dev_err(dev, "chipselect %d already in use\n",
> > cs_nw);
> > > return -EBUSY; @@ -764,6
> > > +764,7 @@ struct spi_device *spi_new_device(struct spi_controller
> *ctlr,
> > > {
> > > struct spi_device *proxy;
> > > int status;
> > > + u8 idx;
> > >
> > > /*
> > > * NOTE: caller did any chip->bus_num checks necessary.
> > > @@ -779,6 +780,9 @@ struct spi_device *spi_new_device(struct
> > > spi_controller *ctlr,
> > >
> > > WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
> > >
> > > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > > + spi_set_chipselect(proxy, idx, 0xFF);
> > > +
> > > spi_set_chipselect(proxy, 0, chip->chip_select);
> > > proxy->max_speed_hz = chip->max_speed_hz;
> > > proxy->mode = chip->mode;
> > > @@ -2514,6 +2518,7 @@ struct spi_device
> > *spi_new_ancillary_device(struct spi_device *spi,
> > > struct spi_controller *ctlr = spi->controller;
> > > struct spi_device *ancillary;
> > > int rc = 0;
> > > + u8 idx;
> > >
> > > /* Alloc an spi_device */
> > > ancillary = spi_alloc_device(ctlr); @@ -2524,6 +2529,9 @@
> > > struct spi_device *spi_new_ancillary_device(struct spi_device *spi,
> > >
> > > strscpy(ancillary->modalias, "dummy",
> > > sizeof(ancillary->modalias));
> > >
> > > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > > + spi_set_chipselect(ancillary, idx, 0xFF);
> > > +
> > > /* Use provided chip-select for ancillary device */
> > > spi_set_chipselect(ancillary, 0, chip_select);
> > >
> > > @@ -2732,6 +2740,7 @@ struct spi_device
> *acpi_spi_device_alloc(struct
> > spi_controller *ctlr,
> > > struct acpi_spi_lookup lookup = {};
> > > struct spi_device *spi;
> > > int ret;
> > > + u8 idx;
> > >
> > > if (!ctlr && index == -1)
> > > return ERR_PTR(-EINVAL); @@ -2767,6 +2776,9 @@ struct
> > > spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr,
> > > return ERR_PTR(-ENOMEM);
> > > }
> > >
> > > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > > + spi_set_chipselect(spi, idx, 0xFF);
> > > +
> > > ACPI_COMPANION_SET(&spi->dev, adev);
> > > spi->max_speed_hz = lookup.max_speed_hz;
> > > spi->mode |= lookup.mode;
> > >
> > > Regards,
> > > Amit
> > >
> >
> > Hi,
> >
> > I no longer see that error, or any errors printed from SPI, however, all of
> the
> > transactions are now broken.
> > Every transaction seems to read back 0x0, on all SPI devices, whether
> native
> > CS or GPIO CS, and I dont see it toggling the CS GPIO anymore.
>
> I believe the issue stems from the fact that in the ACPI patch,
> spi->cs_index_mask is not set to 0x01. As a result, in spi_set_cs,
> it fails to meet the condition that governs the CS asset code snippet.
> In the following code diff, I've included the necessary fix along with
> the earlier changes on top of 1/8. I've also included a couple of debug
> prints to aid in further debugging in case my analysis is incorrect.
> Please apply these changes on top of 1/8 and re-run the test.
>
Hi,
I've tested this on several laptops, and it all seems to work now.
Tested-by: Stefan Binding <[email protected]>
Thanks,
Stefan
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index ff66147ba95f..b2e035c3d494 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -619,7 +619,7 @@ static int spi_dev_check(struct device *dev, void
> *data)
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> cs = spi_get_chipselect(spi, idx);
> for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
> - cs_nw = spi_get_chipselect(spi, nw_idx);
> + cs_nw = spi_get_chipselect(new_spi, nw_idx);
> if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> dev_err(dev, "chipselect %d already in use\n",
> cs_nw);
> return -EBUSY;
> @@ -764,6 +764,7 @@ struct spi_device *spi_new_device(struct
> spi_controller *ctlr,
> {
> struct spi_device *proxy;
> int status;
> + u8 idx;
>
> /*
> * NOTE: caller did any chip->bus_num checks necessary.
> @@ -779,6 +780,9 @@ struct spi_device *spi_new_device(struct
> spi_controller *ctlr,
>
> WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(proxy, idx, 0xFF);
> +
> spi_set_chipselect(proxy, 0, chip->chip_select);
> proxy->max_speed_hz = chip->max_speed_hz;
> proxy->mode = chip->mode;
> @@ -787,6 +791,7 @@ struct spi_device *spi_new_device(struct
> spi_controller *ctlr,
> proxy->dev.platform_data = (void *) chip->platform_data;
> proxy->controller_data = chip->controller_data;
> proxy->controller_state = NULL;
> + proxy->cs_index_mask = 0x01;
>
> if (chip->swnode) {
> status = device_add_software_node(&proxy->dev, chip-
> >swnode);
> @@ -1024,6 +1029,8 @@ static void spi_set_cs(struct spi_device *spi,
> bool enable, bool force)
> if (!spi->controller->set_cs_timing && !activate)
> spi_delay_exec(&spi->cs_hold, NULL);
>
> + printk("%s() [%d] spi->cs_index_mask == [%d]\n",__func__,
> __LINE__, spi->cs_index_mask);
> +
> if (!(spi->mode & SPI_NO_CS)) {
> /*
> * Historically ACPI has no means of the GPIO polarity and
> @@ -1038,6 +1045,7 @@ static void spi_set_cs(struct spi_device *spi,
> bool enable, bool force)
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> if (((spi->cs_index_mask >> idx) & 0x01) &&
> spi_get_csgpiod(spi, idx)) {
> + printk("%s() [%d] idx == [%d]\n",__func__, __LINE__,
> idx);
> if (has_acpi_companion(&spi->dev))
> gpiod_set_value_cansleep(spi_get_csgpiod(spi,
> idx),
> !enable);
> @@ -2514,6 +2522,7 @@ struct spi_device
> *spi_new_ancillary_device(struct spi_device *spi,
> struct spi_controller *ctlr = spi->controller;
> struct spi_device *ancillary;
> int rc = 0;
> + u8 idx;
>
> /* Alloc an spi_device */
> ancillary = spi_alloc_device(ctlr);
> @@ -2524,12 +2533,16 @@ struct spi_device
> *spi_new_ancillary_device(struct spi_device *spi,
>
> strscpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias));
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(ancillary, idx, 0xFF);
> +
> /* Use provided chip-select for ancillary device */
> spi_set_chipselect(ancillary, 0, chip_select);
>
> /* Take over SPI mode/speed from SPI main device */
> ancillary->max_speed_hz = spi->max_speed_hz;
> ancillary->mode = spi->mode;
> + ancillary->cs_index_mask = 0x01;
>
> WARN_ON(!mutex_is_locked(&ctlr->add_lock));
>
> @@ -2732,6 +2745,7 @@ struct spi_device *acpi_spi_device_alloc(struct
> spi_controller *ctlr,
> struct acpi_spi_lookup lookup = {};
> struct spi_device *spi;
> int ret;
> + u8 idx;
>
> if (!ctlr && index == -1)
> return ERR_PTR(-EINVAL);
> @@ -2767,12 +2781,16 @@ struct spi_device
> *acpi_spi_device_alloc(struct spi_controller *ctlr,
> return ERR_PTR(-ENOMEM);
> }
>
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_chipselect(spi, idx, 0xFF);
> +
> ACPI_COMPANION_SET(&spi->dev, adev);
> spi->max_speed_hz = lookup.max_speed_hz;
> spi->mode |= lookup.mode;
> spi->irq = lookup.irq;
> spi->bits_per_word = lookup.bits_per_word;
> spi_set_chipselect(spi, 0, lookup.chip_select);
> + spi->cs_index_mask = 0x01;
>
> return spi;
> }
>
> Regards,
> Amit
>
> >
> > Thanks,
> >
> > Stefan
> >
> > >> Thanks,
> > >>
> > >> Stefan
> > >>
> > >>>> Hi,
> > >>>>
> > >>>> I still see the same error:
> > >>>>
> > >>>> [ 2.748546] pxa2xx-spi pxa2xx-spi.6: chipselect 0 already in use
> > >>> Thank you for the quick testing. For further analysis I have
> > >>> incorporated additional debug prints on top of 1/8 patch. The
> > >>> corresponding diff is shared below. Kindly implement the specified
> > >>> changes, rerun your test and share the kernel logs.
> > >>>
> > >>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > >>> ff66147ba95f..7f59ea81593d 100644
> > >>> --- a/drivers/spi/spi.c
> > >>> +++ b/drivers/spi/spi.c
> > >>> @@ -618,8 +618,10 @@ static int spi_dev_check(struct device *dev,
> > >>> void
> > >> *data)
> > >>> if (spi->controller == new_spi->controller) {
> > >>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>> cs = spi_get_chipselect(spi, idx);
> > >>> + printk("%s() [%d] CS[%d] = [%d]\n",
> > >>> + __func__, __LINE__, idx, cs);
> > >>> for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> nw_idx++) {
> > >>> - cs_nw = spi_get_chipselect(spi, nw_idx);
> > >>> + cs_nw = spi_get_chipselect(new_spi, nw_idx);
> > >>> + printk("%s() [%d] CS_NEW[%d] =
> > >>> + [%d]\n", __func__, __LINE__, nw_idx, cs_nw);
> > >>> if (cs != 0xFF && cs_nw != 0xFF && cs == cs_nw) {
> > >>> dev_err(dev, "chipselect
> > >>> %d already in use\n",
> > >> cs_nw);
> > >>> return -EBUSY; @@ -659,8
> > >>> +661,10 @@ static int __spi_add_device(struct spi_device *spi)
> > >>> */
> > >>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>> cs = spi_get_chipselect(spi, idx);
> > >>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> > >>> + __LINE__, idx, cs);
> > >>> for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX;
> nw_idx++) {
> > >>> nw_cs = spi_get_chipselect(spi, nw_idx);
> > >>> + printk("%s() [%d] CS_NEW[%d] = [%d]\n",
> > >>> + __func__, __LINE__, nw_idx, nw_cs);
> > >>> if (cs != 0xFF && nw_cs != 0xFF && cs == nw_cs) {
> > >>> dev_err(dev, "chipselect %d already in use\n",
> nw_cs);
> > >>> return -EBUSY; @@ -2401,6 +2405,9
> > >>> @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> spi_device
> > *spi,
> > >>> for (idx = 0; idx < rc; idx++)
> > >>> spi_set_chipselect(spi, idx, cs[idx]);
> > >>>
> > >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > >>> + printk("%s() [%d] CS[%d] = [%d]\n", __func__,
> > >>> + __LINE__, idx, spi_get_chipselect(spi, idx));
> > >>> +
> > >>> /* spi->chip_select[i] gives the corresponding physical CS for
> logical
> > CS i
> > >>> * logical CS number is represented by setting the ith bit
> > >>> in spi- cs_index_mask
> > >>> * So, for example, if spi->cs_index_mask = 0x01 then
> > >>> logical CS number is 0 and
> > >>>
> > >>> Regards,
> > >>> Amit
> > >>>
> > >>>> Thanks,
> > >>>>
> > >>>> Stefan
> > >>>>
> > >>>>>>> + if (cs != 0xFF && cs_nw != 0xFF
> && cs
> > >> ==
> > >>>>>> cs_nw) {
> > >>>>>>> + dev_err(dev, "chipselect
> %d
> > >> already in
> > >>>>>> use\n", cs_nw);
> > >>>>>>> + return -EBUSY;
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>> return 0;
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> @@ -629,13 +640,32 @@ static int __spi_add_device(struct
> > >>>>>>> spi_device
> > >>>> *spi)
> > >>>>>>> {
> > >>>>>>> struct spi_controller *ctlr = spi->controller;
> > >>>>>>> struct device *dev = ctlr->dev.parent;
> > >>>>>>> - int status;
> > >>>>>>> + int status, idx, nw_idx;
> > >>>>>>> + u8 cs, nw_cs;
> > >>>>>>> +
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>>>>>> + /* Chipselects are numbered 0..max; validate. */
> > >>>>>>> + cs = spi_get_chipselect(spi, idx);
> > >>>>>>> + if (cs != 0xFF && cs >= ctlr->num_chipselect) {
> > >>>>>>> + dev_err(dev, "cs%d >= max %d\n",
> > >>>>>> spi_get_chipselect(spi, idx),
> > >>>>>>> + ctlr->num_chipselect);
> > >>>>>>> + return -EINVAL;
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>>
> > >>>>>>> - /* Chipselects are numbered 0..max; validate. */
> > >>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> > >>>>>>> - dev_err(dev, "cs%d >= max %d\n",
> > spi_get_chipselect(spi, 0),
> > >>>>>>> - ctlr->num_chipselect);
> > >>>>>>> - return -EINVAL;
> > >>>>>>> + /*
> > >>>>>>> + * Make sure that multiple logical CS doesn't map to the
> same
> > >>>>>> physical CS.
> > >>>>>>> + * For example, spi->chip_select[0] != spi->chip_select[1]
> and
> > >> so on.
> > >>>>>>> + */
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>>>>>> + cs = spi_get_chipselect(spi, idx);
> > >>>>>>> + for (nw_idx = idx + 1; nw_idx < SPI_CS_CNT_MAX;
> > >> nw_idx++) {
> > >>>>>>> + nw_cs = spi_get_chipselect(spi, nw_idx);
> > >>>>>>> + if (cs != 0xFF && nw_cs != 0xFF && cs ==
> > >> nw_cs) {
> > >>>>>>> + dev_err(dev, "chipselect %d
> already in
> > >> use\n",
> > >>>>>> nw_cs);
> > >>>>>>> + return -EBUSY;
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> /* Set the bus ID string */ @@ -647,11 +677,8 @@ static
> > >>>>>>> int __spi_add_device(struct spi_device
> > >>>> *spi)
> > >>>>>>> * its configuration.
> > >>>>>>> */
> > >>>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> > >> spi_dev_check);
> > >>>>>>> - if (status) {
> > >>>>>>> - dev_err(dev, "chipselect %d already in use\n",
> > >>>>>>> - spi_get_chipselect(spi, 0));
> > >>>>>>> + if (status)
> > >>>>>>> return status;
> > >>>>>>> - }
> > >>>>>>>
> > >>>>>>> /* Controller may unregister concurrently */
> > >>>>>>> if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && @@ -659,8
> > >> +686,15 @@
> > >>>>>> static
> > >>>>>>> int __spi_add_device(struct spi_device *spi)
> > >>>>>>> return -ENODEV;
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> - if (ctlr->cs_gpiods)
> > >>>>>>> - spi_set_csgpiod(spi, 0, ctlr-
> > >cs_gpiods[spi_get_chipselect(spi,
> > >>>>>> 0)]);
> > >>>>>>> + if (ctlr->cs_gpiods) {
> > >>>>>>> + u8 cs;
> > >>>>>>> +
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>>>>>> + cs = spi_get_chipselect(spi, idx);
> > >>>>>>> + if (cs != 0xFF)
> > >>>>>>> + spi_set_csgpiod(spi, idx, ctlr-
> > >>> cs_gpiods[cs]);
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>>
> > >>>>>>> /*
> > >>>>>>> * Drivers may modify this initial i/o setup, but will @@
> > >>>>>>> -701,6
> > >>>>>>> +735,9 @@ int spi_add_device(struct spi_device *spi)
> > >>>>>>> struct spi_controller *ctlr = spi->controller;
> > >>>>>>> int status;
> > >>>>>>>
> > >>>>>>> + /* Set the bus ID string */
> > >>>>>>> + spi_dev_set_name(spi);
> > >>>>>>> +
> > >>>>>>> mutex_lock(&ctlr->add_lock);
> > >>>>>>> status = __spi_add_device(spi);
> > >>>>>>> mutex_unlock(&ctlr->add_lock); @@ -942,32 +979,51
> @@
> > >> static
> > >>>>>>> void spi_res_release(struct spi_controller
> > >>>>>> *ctlr, struct spi_message *mes
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>>
> > >>>>>>> /*--------------------------------------------------------------
> > >>>>>>> --
> > >>>>>>> --
> > >>>>>>> --
> > >>>>>>> -----*/
> > >>>>>>> +static inline bool spi_is_last_cs(struct spi_device *spi) {
> > >>>>>>> + u8 idx;
> > >>>>>>> + bool last = false;
> > >>>>>>> +
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>>>>>> + if ((spi->cs_index_mask >> idx) & 0x01) {
> > >>>>>>> + if (spi->controller->last_cs[idx] ==
> > >>>>>> spi_get_chipselect(spi, idx))
> > >>>>>>> + last = true;
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>> + return last;
> > >>>>>>> +}
> > >>>>>>> +
> > >>>>>>>
> > >>>>>>> static void spi_set_cs(struct spi_device *spi, bool enable,
> bool
> > force)
> > >>>>>>> {
> > >>>>>>> bool activate = enable;
> > >>>>>>> + u8 idx;
> > >>>>>>>
> > >>>>>>> /*
> > >>>>>>> * Avoid calling into the driver (or doing delays) if the
> > >>>>>>> chip
> > >> select
> > >>>>>>> * isn't actually changing from the last time this was
> called.
> > >>>>>>> */
> > >>>>>>> - if (!force && ((enable && spi->controller->last_cs ==
> > >>>>>> spi_get_chipselect(spi, 0)) ||
> > >>>>>>> - (!enable && spi->controller->last_cs !=
> > >>>>>> spi_get_chipselect(spi, 0))) &&
> > >>>>>>> + if (!force && ((enable && spi->controller-
> >last_cs_index_mask
> > >> ==
> > >>>>>>> +spi-
> > >>>>>>> cs_index_mask &&
> > >>>>>>> + spi_is_last_cs(spi)) ||
> > >>>>>>> + (!enable && spi->controller-
> >last_cs_index_mask
> > >> == spi-
> > >>>>>>> cs_index_mask &&
> > >>>>>>> + !spi_is_last_cs(spi))) &&
> > >>>>>>> (spi->controller->last_cs_mode_high == (spi->mode &
> > >>>>>> SPI_CS_HIGH)))
> > >>>>>>> return;
> > >>>>>>>
> > >>>>>>> trace_spi_set_cs(spi, activate);
> > >>>>>>>
> > >>>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi,
> 0) : -
> > 1;
> > >>>>>>> + spi->controller->last_cs_index_mask = spi-
> >cs_index_mask;
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > >>>>>>> + spi->controller->last_cs[idx] = enable ?
> > >>>>>>> +spi_get_chipselect(spi,
> > >>>>>> 0)
> > >>>>>>> +: -1;
> > >>>>>>> spi->controller->last_cs_mode_high = spi->mode &
> > >> SPI_CS_HIGH;
> > >>>>>>> - if ((spi_get_csgpiod(spi, 0) || !spi->controller-
> >set_cs_timing)
> > &&
> > >>>>>> !activate)
> > >>>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
> > >>>>>>> -
> > >>>>>>> if (spi->mode & SPI_CS_HIGH)
> > >>>>>>> enable = !enable;
> > >>>>>>>
> > >>>>>>> - if (spi_get_csgpiod(spi, 0)) {
> > >>>>>>> + if (spi_is_csgpiod(spi)) {
> > >>>>>>> + if (!spi->controller->set_cs_timing && !activate)
> > >>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> > >>>>>>> +
> > >>>>>>> if (!(spi->mode & SPI_NO_CS)) {
> > >>>>>>> /*
> > >>>>>>> * Historically ACPI has no means of the
> GPIO
> > >> polarity
> > >>>>>> and @@
> > >>>>>>> -979,26 +1035,38 @@ static void spi_set_cs(struct spi_device
> > >>>>>>> *spi, bool
> > >>>>>> enable, bool force)
> > >>>>>>> * ambiguity. That's why we use enable,
> that
> > >> takes
> > >>>>>> SPI_CS_HIGH
> > >>>>>>> * into account.
> > >>>>>>> */
> > >>>>>>> - if (has_acpi_companion(&spi->dev))
> > >>>>>>> -
> > >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0),
> !enable);
> > >>>>>>> - else
> > >>>>>>> - /* Polarity handled by GPIO
> library */
> > >>>>>>> -
> > >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0),
> activate);
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX;
> idx++) {
> > >>>>>>> + if (((spi->cs_index_mask >> idx)
> &
> > >> 0x01) &&
> > >>>>>>> + spi_get_csgpiod(spi, idx)) {
> > >>>>>>> + if
> (has_acpi_companion(&spi-
> > >>> dev))
> > >>>>>>> +
> > >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> > >>>>>>> +
> > >>>>>> !enable);
> > >>>>>>> + else
> > >>>>>>> + /* Polarity
> handled by
> > >> GPIO
> > >>>>>> library */
> > >>>>>>> +
> > >>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> > >>>>>>> +
> > >>>>>> activate);
> > >>>>>>> +
> > >>>>>>> + if (activate)
> > >>>>>>> +
> spi_delay_exec(&spi-
> > >>>>>>> cs_setup, NULL);
> > >>>>>>> + else
> > >>>>>>> +
> spi_delay_exec(&spi-
> > >>>>>>> cs_inactive, NULL);
> > >>>>>>> + }
> > >>>>>>> + }
> > >>>>>>> }
> > >>>>>>> /* Some SPI masters need both GPIO CS &
> > >> slave_select */
> > >>>>>>> if ((spi->controller->flags &
> > >> SPI_CONTROLLER_GPIO_SS) &&
> > >>>>>>> spi->controller->set_cs)
> > >>>>>>> spi->controller->set_cs(spi, !enable);
> > >>>>>>> +
> > >>>>>>> + if (!spi->controller->set_cs_timing) {
> > >>>>>>> + if (activate)
> > >>>>>>> + spi_delay_exec(&spi->cs_setup,
> > >> NULL);
> > >>>>>>> + else
> > >>>>>>> + spi_delay_exec(&spi-
> >cs_inactive,
> > >> NULL);
> > >>>>>>> + }
> > >>>>>>> } else if (spi->controller->set_cs) {
> > >>>>>>> spi->controller->set_cs(spi, !enable);
> > >>>>>>> }
> > >>>>>>> -
> > >>>>>>> - if (spi_get_csgpiod(spi, 0) || !spi->controller-
> >set_cs_timing) {
> > >>>>>>> - if (activate)
> > >>>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
> > >>>>>>> - else
> > >>>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
> > >>>>>>> - }
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> #ifdef CONFIG_HAS_DMA
> > >>>>>>> @@ -2222,8 +2290,8 @@ static void
> > >>>>>>> of_spi_parse_dt_cs_delay(struct
> > >>>>>> device_node *nc,
> > >>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr,
> > >>>>>>> struct spi_device
> > >>>> *spi,
> > >>>>>>> struct device_node *nc)
> > >>>>>>> {
> > >>>>>>> - u32 value;
> > >>>>>>> - int rc;
> > >>>>>>> + u32 value, cs[SPI_CS_CNT_MAX];
> > >>>>>>> + int rc, idx;
> > >>>>>>>
> > >>>>>>> /* Mode (clock phase/polarity/etc.) */
> > >>>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2295,14
> > >>>>>>> +2363,52
> > >>>>>> @@
> > >>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> > >>>>>>> spi_device
> > >> *spi,
> > >>>>>>> return 0;
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> + if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
> > >>>>>>> + dev_err(&ctlr->dev, "No. of CS is more than max.
> no.
> > >> of
> > >>>>>> supported CS\n");
> > >>>>>>> + return -EINVAL;
> > >>>>>>> + }
> > >>>>>>> +
> > >>>>>>> + /*
> > >>>>>>> + * Zero(0) is a valid physical CS value and can be located at
> > >> any
> > >>>>>>> + * logical CS in the spi->chip_select[]. If all the physical CS
> > >>>>>>> + * are initialized to 0 then It would be difficult to
> differentiate
> > >>>>>>> + * between a valid physical CS 0 & an unused logical CS
> whose
> > >>>>>> physical
> > >>>>>>> + * CS can be 0. As a solution to this issue initialize all the
> > >>>>>>> +CS to
> > >> 0xFF.
> > >>>>>>> + * Now all the unused logical CS will have 0xFF physical CS
> > >>>>>>> +value & can
> > >>>>>> be
> > >>>>>>> + * ignore while performing physical CS validity checks.
> > >>>>>>> + */
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > >>>>>>> + spi_set_chipselect(spi, idx, 0xFF);
> > >>>>>>> +
> > >>>>>>> /* Device address */
> > >>>>>>> - rc = of_property_read_u32(nc, "reg", &value);
> > >>>>>>> - if (rc) {
> > >>>>>>> + rc = of_property_read_variable_u32_array(nc, "reg",
> &cs[0],
> > >> 1,
> > >>>>>>> +
> SPI_CS_CNT_MAX);
> > >>>>>>> + if (rc < 0) {
> > >>>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg'
> property
> > >>>>>> (%d)\n",
> > >>>>>>> nc, rc);
> > >>>>>>> return rc;
> > >>>>>>> }
> > >>>>>>> - spi_set_chipselect(spi, 0, value);
> > >>>>>>> + if (rc > ctlr->num_chipselect) {
> > >>>>>>> + dev_err(&ctlr->dev, "%pOF has number of CS >
> ctlr-
> > >>>>>>> num_chipselect (%d)\n",
> > >>>>>>> + nc, rc);
> > >>>>>>> + return rc;
> > >>>>>>> + }
> > >>>>>>> + if ((of_property_read_bool(nc, "parallel-memories")) &&
> > >>>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> > >>>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't
> support
> > >> multi
> > >>>>>> CS\n");
> > >>>>>>> + return -EINVAL;
> > >>>>>>> + }
> > >>>>>>> + for (idx = 0; idx < rc; idx++)
> > >>>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
> > >>>>>>> +
> > >>>>>>> + /* spi->chip_select[i] gives the corresponding physical CS
> for
> > >>>>>>> +logical CS
> > >>>>>> i
> > >>>>>>> + * logical CS number is represented by setting the ith bit in
> > >>>>>>> +spi-
> > >>>>>>> cs_index_mask
> > >>>>>>> + * So, for example, if spi->cs_index_mask = 0x01 then
> logical
> > >> CS
> > >>>>>> number is 0 and
> > >>>>>>> + * spi->chip_select[0] will give the physical CS.
> > >>>>>>> + * By default spi->chip_select[0] will hold the physical CS
> > >>>>>>> +number so,
> > >>>>>> set
> > >>>>>>> + * spi->cs_index_mask as 0x01.
> > >>>>>>> + */
> > >>>>>>> + spi->cs_index_mask = 0x01;
> > >>>>>>>
> > >>>>>>> /* Device speed */
> > >>>>>>> if (!of_property_read_u32(nc, "spi-max-frequency",
> > >>>>>>> &value)) @@
> > >>>>>>> -3100,6 +3206,7 @@ int spi_register_controller(struct
> > >>>>>>> spi_controller
> > >> *ctlr)
> > >>>>>>> struct boardinfo *bi;
> > >>>>>>> int first_dynamic;
> > >>>>>>> int status;
> > >>>>>>> + int idx;
> > >>>>>>>
> > >>>>>>> if (!dev)
> > >>>>>>> return -ENODEV;
> > >>>>>>> @@ -3164,7 +3271,8 @@ int spi_register_controller(struct
> > >>>>>>> spi_controller
> > >>>>>> *ctlr)
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> /* Setting last_cs to -1 means no chip selected */
> > >>>>>>> - ctlr->last_cs = -1;
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > >>>>>>> + ctlr->last_cs[idx] = -1;
> > >>>>>>>
> > >>>>>>> status = device_add(&ctlr->dev);
> > >>>>>>> if (status < 0)
> > >>>>>>> @@ -3889,7 +3997,7 @@ static int __spi_validate(struct
> > >>>>>>> spi_device *spi,
> > >>>>>> struct spi_message *message)
> > >>>>>>> * cs_change is set for each transfer.
> > >>>>>>> */
> > >>>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> > >>>>>> SPI_CS_WORD) ||
> > >>>>>>> - spi_get_csgpiod(spi, 0)))
> {
> > >>>>>>> + spi_is_csgpiod(spi))) {
> > >>>>>>> size_t maxsize = BITS_TO_BYTES(spi-
> >bits_per_word);
> > >>>>>>> int ret;
> > >>>>>>>
> > >>>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> > >>>>>>> index 7b4baff63c5c..871d3a6d879b 100644
> > >>>>>>> --- a/include/linux/spi/spi.h
> > >>>>>>> +++ b/include/linux/spi/spi.h
> > >>>>>>> @@ -20,6 +20,9 @@
> > >>>>>>>
> > >>>>>>> #include <uapi/linux/spi/spi.h>
> > >>>>>>>
> > >>>>>>> +/* Max no. of CS supported per spi device */ #define
> > >>>>>>> +SPI_CS_CNT_MAX
> > >>>>>>> +4
> > >>>>>>> +
> > >>>>>>> struct dma_chan;
> > >>>>>>> struct software_node;
> > >>>>>>> struct ptp_system_timestamp; @@ -132,7 +135,8 @@
> extern
> > >>>>>>> void
> > >>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > >>>>>>> * @max_speed_hz: Maximum clock rate to be used with this
> chip
> > >>>>>>> * (on this board); may be changed by the device's driver.
> > >>>>>>> * The spi_transfer.speed_hz can override this for each
> transfer.
> > >>>>>>> - * @chip_select: Chipselect, distinguishing chips handled by
> > >> @controller.
> > >>>>>>> + * @chip_select: Array of physical chipselect, spi->chipselect[i]
> gives
> > >>>>>>> + * the corresponding physical CS for logical CS i.
> > >>>>>>> * @mode: The spi mode defines how data is clocked out and
> in.
> > >>>>>>> * This may be changed by the device's driver.
> > >>>>>>> * The "active low" default for chipselect mode can be
> > >> overridden
> > >>>>>>> @@ -157,8 +161,8 @@ extern void
> > >>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > >>>>>>> * the device will bind to the named driver and only the
> named
> > >> driver.
> > >>>>>>> * Do not set directly, because core frees it; use
> > >> driver_set_override() to
> > >>>>>>> * set or clear it.
> > >>>>>>> - * @cs_gpiod: GPIO descriptor of the chipselect line (optional,
> > >>>>>>> NULL
> > >>>> when
> > >>>>>>> - * not using a GPIO line)
> > >>>>>>> + * @cs_gpiod: Array of GPIO descriptors of the corresponding
> > >>>>>>> + chipselect
> > >>>>>> lines
> > >>>>>>> + * (optional, NULL when not using a GPIO line)
> > >>>>>>> * @word_delay: delay to be inserted between consecutive
> > >>>>>>> * words of a transfer
> > >>>>>>> * @cs_setup: delay to be introduced by the controller
> > >>>>>>> after CS is asserted @@ -167,6 +171,7 @@ extern void
> > >>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > >>>>>>> * deasserted. If @cs_change_delay is used from
> @spi_transfer,
> > >> then
> > >>>>>> the
> > >>>>>>> * two delays will be added up.
> > >>>>>>> * @pcpu_statistics: statistics for the spi_device
> > >>>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> > >>>>>>> + chipselect array
> > >>>>>>> *
> > >>>>>>> * A @spi_device is used to interchange data between an SPI
> slave
> > >>>>>>> * (usually a discrete chip) and CPU memory.
> > >>>>>>> @@ -182,7 +187,7 @@ struct spi_device {
> > >>>>>>> struct spi_controller *controller;
> > >>>>>>> struct spi_controller *master; /* Compatibility
> layer
> > >> */
> > >>>>>>> u32 max_speed_hz;
> > >>>>>>> - u8 chip_select;
> > >>>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
> > >>>>>>> u8 bits_per_word;
> > >>>>>>> bool rt;
> > >>>>>>> #define SPI_NO_TX BIT(31) /* No
> transmit wire */
> > >>>>>>> @@ -213,7 +218,7 @@ struct spi_device {
> > >>>>>>> void *controller_data;
> > >>>>>>> char modalias[SPI_NAME_SIZE];
> > >>>>>>> const char *driver_override;
> > >>>>>>> - struct gpio_desc *cs_gpiod; /* Chip select GPIO
> > descriptor
> > >>>>>> */
> > >>>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> > >> Chip select
> > >>>>>> gpio desc */
> > >>>>>>> struct spi_delay word_delay; /* Inter-word delay */
> > >>>>>>> /* CS delays */
> > >>>>>>> struct spi_delay cs_setup;
> > >>>>>>> @@ -223,6 +228,13 @@ struct spi_device {
> > >>>>>>> /* The statistics */
> > >>>>>>> struct spi_statistics __percpu *pcpu_statistics;
> > >>>>>>>
> > >>>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
> > >> from
> > >>>>>>> + * the chipselect array.When the controller is capable to
> > >> handle
> > >>>>>>> + * multiple chip selects & memories are connected in
> parallel
> > >>>>>>> + * then more than one bit need to be set in
> cs_index_mask.
> > >>>>>>> + */
> > >>>>>>> + u32 cs_index_mask :
> SPI_CS_CNT_MAX;
> > >>>>>>> +
> > >>>>>>> /*
> > >>>>>>> * Likely need more hooks for more protocol options
> > >>>>>>> affecting
> > >> how
> > >>>>>>> * the controller talks to each chip, like:
> > >>>>>>> @@ -279,22 +291,33 @@ static inline void
> *spi_get_drvdata(const
> > >>>>>>> struct spi_device *spi)
> > >>>>>>>
> > >>>>>>> static inline u8 spi_get_chipselect(const struct spi_device
> *spi, u8
> > idx)
> > >>>>>>> {
> > >>>>>>> - return spi->chip_select;
> > >>>>>>> + return spi->chip_select[idx];
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> static inline void spi_set_chipselect(struct spi_device
> > >>>>>>> *spi,
> > >>>>>>> u8 idx, u8
> > >>>>>> chipselect)
> > >>>>>>> {
> > >>>>>>> - spi->chip_select = chipselect;
> > >>>>>>> + spi->chip_select[idx] = chipselect;
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> static inline struct gpio_desc *spi_get_csgpiod(const
> > >>>>>>> struct spi_device *spi,
> > >>>>>> u8 idx)
> > >>>>>>> {
> > >>>>>>> - return spi->cs_gpiod;
> > >>>>>>> + return spi->cs_gpiod[idx];
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> static inline void spi_set_csgpiod(struct spi_device *spi,
> > >>>>>>> u8 idx, struct
> > >>>>>> gpio_desc *csgpiod)
> > >>>>>>> {
> > >>>>>>> - spi->cs_gpiod = csgpiod;
> > >>>>>>> + spi->cs_gpiod[idx] = csgpiod;
> > >>>>>>> +}
> > >>>>>>> +
> > >>>>>>> +static inline bool spi_is_csgpiod(struct spi_device *spi) {
> > >>>>>>> + u8 idx;
> > >>>>>>> +
> > >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > >>>>>>> + if (spi_get_csgpiod(spi, idx))
> > >>>>>>> + return true;
> > >>>>>>> + }
> > >>>>>>> + return false;
> > >>>>>>> }
> > >>>>>>>
> > >>>>>>> /**
> > >>>>>>> @@ -399,6 +422,8 @@ extern struct spi_device
> > >>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> > >>>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
> > >>>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> > >>>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
> > >>>>>>> exclusive use
> > >>>>>>> + * @multi_cs_cap: indicates that the SPI Controller can
> > >>>>>>> + assert/de-
> > >> assert
> > >>>>>>> + * more than one chip select at once.
> > >>>>>>> * @setup: updates the device mode and clocking records
> used by
> > a
> > >>>>>>> * device's SPI controller; protocol code may call this. This
> > >>>>>>> * must fail if an unrecognized or unsupported mode is
> > >> requested.
> > >>>>>>> @@ -567,6 +592,11 @@ struct spi_controller {
> > >>>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4)
> /*
> > Requires tx
> > >>>> */
> > >>>>>>> #define SPI_CONTROLLER_GPIO_SS BIT(5)
> /* GPIO CS
> > >>>> must
> > >>>>>> select slave */
> > >>>>>>> #define SPI_CONTROLLER_SUSPENDED BIT(6) /*
> Currently
> > >>>>>> suspended */
> > >>>>>>> + /*
> > >>>>>>> + * The spi-controller has multi chip select capability and
> can
> > >>>>>>> + * assert/de-assert more than one chip select at once.
> > >>>>>>> + */
> > >>>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(7)
> > >>>>>>>
> > >>>>>>> /* Flag indicating if the allocation of this struct is
> > >>>>>>> devres-
> > >> managed */
> > >>>>>>> bool devm_allocated;
> > >>>>>>> @@ -677,7 +707,8 @@ struct spi_controller {
> > >>>>>>> bool rt;
> > >>>>>>> bool auto_runtime_pm;
> > >>>>>>> bool cur_msg_mapped;
> > >>>>>>> - char last_cs;
> > >>>>>>> + char
> last_cs[SPI_CS_CNT_MAX];
> > >>>>>>> + char last_cs_index_mask;
> > >>>>>>> bool last_cs_mode_high;
> > >>>>>>> bool fallback;
> > >>>>>>> struct completion xfer_completion;
On Sat, 18 Nov 2023 19:24:38 +0530, Amit Kumar Mahapatra wrote:
> This patch is in the continuation to the discussions which happened on
> 'commit f89504300e94 ("spi: Stacked/parallel memories bindings")' for
> adding dt-binding support for stacked/parallel memories.
>
> This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI
> driver to add stacked and parallel memories support.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/8] spi: Add multi-cs memories support in SPI core
commit: 4d8ff6b0991d5e86b17b235fc46ec62e9195cb9b
[6/8] spi: spi-zynqmp-gqspi: Add stacked memories support in GQSPI driver
(no commit info)
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark