2019-03-29 12:41:28

by Yannick FERTRE

Subject: [PATCH] media: platform: stm32: wait end of transmission

It is mandatory to write CEC_CFGR only when CECEN=0. To protect
transmission, a check have been added to delayed logical address
modification. This patch is necessary tp pass all tests of compliance.

Signed-off-by: Yannick Fertré <[email protected]>
---
drivers/media/platform/stm32/stm32-cec.c | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/drivers/media/platform/stm32/stm32-cec.c b/drivers/media/platform/stm32/stm32-cec.c
index 7c496bc..8a86b2c 100644
--- a/drivers/media/platform/stm32/stm32-cec.c
+++ b/drivers/media/platform/stm32/stm32-cec.c
@@ -56,6 +56,13 @@
#define ALL_TX_IT (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
#define ALL_RX_IT (RXEND | RXBR | RXACKE | RXOVR)

+/*
+ * 400 ms is the time it takes for one 16 byte message to be
+ * transferred and 5 is the maximum number of retries. Add
+ * another 100 ms as a margin.
+ */
+#define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
+
struct stm32_cec {
struct cec_adapter *adap;
struct device *dev;
@@ -188,7 +195,11 @@ static int stm32_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
{
struct stm32_cec *cec = adap->priv;
u32 oar = (1 << logical_addr) << 16;
+ u32 val;

+ /* Poll every 100µs the register CEC_CR to wait end of transmission */
+ regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM),
+ 100, CEC_XFER_TIMEOUT_MS * 1000);
regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);

if (logical_addr == CEC_LOG_ADDR_INVALID)
--
2.7.4

2019-03-29 14:04:37

by Benjamin Gaignard

Subject: Re: [PATCH] media: platform: stm32: wait end of transmission

Le ven. 29 mars 2019 à 13:40, Yannick Fertré <[email protected]> a écrit :
>
> It is mandatory to write CEC_CFGR only when CECEN=0. To protect
> transmission, a check have been added to delayed logical address
> modification. This patch is necessary tp pass all tests of compliance.

Reviewed-by: Benjamin Gaignard <[email protected]>

>
> Signed-off-by: Yannick Fertré <[email protected]>
> ---
> drivers/media/platform/stm32/stm32-cec.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/media/platform/stm32/stm32-cec.c b/drivers/media/platform/stm32/stm32-cec.c
> index 7c496bc..8a86b2c 100644
> --- a/drivers/media/platform/stm32/stm32-cec.c
> +++ b/drivers/media/platform/stm32/stm32-cec.c
> @@ -56,6 +56,13 @@
> #define ALL_TX_IT (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
> #define ALL_RX_IT (RXEND | RXBR | RXACKE | RXOVR)
>
> +/*
> + * 400 ms is the time it takes for one 16 byte message to be
> + * transferred and 5 is the maximum number of retries. Add
> + * another 100 ms as a margin.
> + */
> +#define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
> +
> struct stm32_cec {
> struct cec_adapter *adap;
> struct device *dev;
> @@ -188,7 +195,11 @@ static int stm32_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
> {
> struct stm32_cec *cec = adap->priv;
> u32 oar = (1 << logical_addr) << 16;
> + u32 val;
>
> + /* Poll every 100µs the register CEC_CR to wait end of transmission */
> + regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM),
> + 100, CEC_XFER_TIMEOUT_MS * 1000);
> regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
>
> if (logical_addr == CEC_LOG_ADDR_INVALID)
> --
> 2.7.4
>
>
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