Hi All,
This patch series adds CANFD support to Renesas RZ/G2L family.
CANFD block on RZ/G2L SoC is almost identical to one found on
R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
are split into individual sources.
Cheers,
Prabhakar
Changes for v4:
* Included RB tag from Rob for DT binding patch.
* Split up the global IRQ handlers so that the code is re-used
by both RZ/G2L and R-Car Gen3 SoC's as suggested by Geert.
Changes for v3:
* Dropped core clock addition patches from this series (its queued
up already in renesas-clk-for-v5.15)
* Added reset-names in binding doc as suggested by Philipp
* Updated interrupt names in binding doc as suggested by Geert
* Updated the driver to handle the above DT binding changes
Changes for v2:
* Added interrupt-names property and marked it as required for
RZ/G2L family
* Added descriptions for reset property
* Re-used irq handlers on RZ/G2L SoC
* Added new enum for chip_id
* Dropped R9A07G044_LAST_CORE_CLK
* Dropped patch (clk: renesas: r9a07g044-cpg: Add clock and reset
entries for CANFD) as its been merged into renesas tree
v1: https://patchwork.kernel.org/project/linux-renesas-soc/
cover/[email protected]/
Lad Prabhakar (3):
dt-bindings: net: can: renesas,rcar-canfd: Document RZ/G2L SoC
can: rcar_canfd: Add support for RZ/G2L family
arm64: dts: renesas: r9a07g044: Add CANFD node
.../bindings/net/can/renesas,rcar-canfd.yaml | 69 +++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 +++
drivers/net/can/rcar/rcar_canfd.c | 338 ++++++++++++++----
3 files changed, 369 insertions(+), 79 deletions(-)
--
2.17.1
CANFD block on RZ/G2L SoC is almost identical to one found on
R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
are split into different sources and the IP doesn't divide (1/2)
CANFD clock within the IP.
This patch adds compatible string for RZ/G2L family and splits
the irq handlers to accommodate both RZ/G2L and R-Car Gen3 SoC's.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/net/can/rcar/rcar_canfd.c | 338 +++++++++++++++++++++++-------
1 file changed, 265 insertions(+), 73 deletions(-)
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 311e6ca3bdc4..adb0c6a787ce 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -37,9 +37,15 @@
#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
+#include <linux/reset.h>
#define RCANFD_DRV_NAME "rcar_canfd"
+enum rcanfd_chip_id {
+ RENESAS_RCAR_GEN3 = 0,
+ RENESAS_RZG2L,
+};
+
/* Global register bits */
/* RSCFDnCFDGRMCFG */
@@ -513,6 +519,9 @@ struct rcar_canfd_global {
enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
unsigned long channels_mask; /* Enabled channels mask */
bool fdmode; /* CAN FD or Classical CAN only mode */
+ struct reset_control *rstc1;
+ struct reset_control *rstc2;
+ enum rcanfd_chip_id chip_id;
};
/* CAN FD mode nominal rate constants */
@@ -1070,38 +1079,70 @@ static void rcar_canfd_tx_done(struct net_device *ndev)
can_led_event(ndev, CAN_LED_EVENT_TX);
}
+static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
+ struct net_device *ndev = priv->ndev;
+ u32 gerfl;
+
+ /* Handle global error interrupts */
+ gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+ if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
+ rcar_canfd_global_error(ndev);
+}
+
+static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_global_err(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
+static void rcar_canfd_handle_global_recieve(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
+ u32 ridx = ch + RCANFD_RFFIFO_IDX;
+ u32 sts;
+
+ /* Handle Rx interrupts */
+ sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+ if (likely(sts & RCANFD_RFSTS_RFIF)) {
+ if (napi_schedule_prep(&priv->napi)) {
+ /* Disable Rx FIFO interrupts */
+ rcar_canfd_clear_bit(priv->base,
+ RCANFD_RFCC(ridx),
+ RCANFD_RFCC_RFIE);
+ __napi_schedule(&priv->napi);
+ }
+ }
+}
+
+static irqreturn_t rcar_canfd_global_recieve_fifo_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_global_recieve(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
{
struct rcar_canfd_global *gpriv = dev_id;
- struct net_device *ndev;
- struct rcar_canfd_channel *priv;
- u32 sts, gerfl;
- u32 ch, ridx;
+ u32 ch;
/* Global error interrupts still indicate a condition specific
* to a channel. RxFIFO interrupt is a global interrupt.
*/
for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
- priv = gpriv->ch[ch];
- ndev = priv->ndev;
- ridx = ch + RCANFD_RFFIFO_IDX;
-
- /* Global error interrupts */
- gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
- if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
- rcar_canfd_global_error(ndev);
-
- /* Handle Rx interrupts */
- sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
- if (likely(sts & RCANFD_RFSTS_RFIF)) {
- if (napi_schedule_prep(&priv->napi)) {
- /* Disable Rx FIFO interrupts */
- rcar_canfd_clear_bit(priv->base,
- RCANFD_RFCC(ridx),
- RCANFD_RFCC_RFIE);
- __napi_schedule(&priv->napi);
- }
- }
+ rcar_canfd_handle_global_err(gpriv, ch);
+ rcar_canfd_handle_global_recieve(gpriv, ch);
}
return IRQ_HANDLED;
}
@@ -1139,38 +1180,73 @@ static void rcar_canfd_state_change(struct net_device *ndev,
}
}
-static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = priv = gpriv->ch[ch];
+ struct net_device *ndev = priv->ndev;
+ u32 sts;
+
+ /* Handle Tx interrupts */
+ sts = rcar_canfd_read(priv->base,
+ RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+ if (likely(sts & RCANFD_CFSTS_CFTXIF))
+ rcar_canfd_tx_done(ndev);
+}
+
+static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
{
struct rcar_canfd_global *gpriv = dev_id;
- struct net_device *ndev;
- struct rcar_canfd_channel *priv;
- u32 sts, ch, cerfl;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_channel_tx(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
+static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
+ struct net_device *ndev = priv->ndev;
u16 txerr, rxerr;
+ u32 sts, cerfl;
+
+ /* Handle channel error interrupts */
+ cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+ sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+ txerr = RCANFD_CSTS_TECCNT(sts);
+ rxerr = RCANFD_CSTS_RECCNT(sts);
+ if (unlikely(RCANFD_CERFL_ERR(cerfl)))
+ rcar_canfd_error(ndev, cerfl, txerr, rxerr);
+
+ /* Handle state change to lower states */
+ if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
+ priv->can.state != CAN_STATE_BUS_OFF))
+ rcar_canfd_state_change(ndev, txerr, rxerr);
+}
+
+static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_channel_err(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
/* Common FIFO is a per channel resource */
for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
- priv = gpriv->ch[ch];
- ndev = priv->ndev;
-
- /* Channel error interrupts */
- cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
- sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
- txerr = RCANFD_CSTS_TECCNT(sts);
- rxerr = RCANFD_CSTS_RECCNT(sts);
- if (unlikely(RCANFD_CERFL_ERR(cerfl)))
- rcar_canfd_error(ndev, cerfl, txerr, rxerr);
-
- /* Handle state change to lower states */
- if (unlikely((priv->can.state != CAN_STATE_ERROR_ACTIVE) &&
- (priv->can.state != CAN_STATE_BUS_OFF)))
- rcar_canfd_state_change(ndev, txerr, rxerr);
-
- /* Handle Tx interrupts */
- sts = rcar_canfd_read(priv->base,
- RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
- if (likely(sts & RCANFD_CFSTS_CFTXIF))
- rcar_canfd_tx_done(ndev);
+ rcar_canfd_handle_channel_err(gpriv, ch);
+ rcar_canfd_handle_channel_tx(gpriv, ch);
}
+
return IRQ_HANDLED;
}
@@ -1577,6 +1653,53 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
priv->can.clock.freq = fcan_freq;
dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+ if (gpriv->chip_id == RENESAS_RZG2L) {
+ char *irq_name;
+ int err_irq;
+ int tx_irq;
+
+ err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
+ if (err_irq < 0) {
+ err = err_irq;
+ goto fail;
+ }
+
+ tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
+ if (tx_irq < 0) {
+ err = tx_irq;
+ goto fail;
+ }
+
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+ "canfd.ch%d_err", ch);
+ if (!irq_name) {
+ err = -ENOMEM;
+ goto fail;
+ }
+ err = devm_request_irq(&pdev->dev, err_irq,
+ rcar_canfd_channel_err_interrupt, 0,
+ irq_name, gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq CH Err(%d) failed, error %d\n",
+ err_irq, err);
+ goto fail;
+ }
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+ "canfd.ch%d_trx", ch);
+ if (!irq_name) {
+ err = -ENOMEM;
+ goto fail;
+ }
+ err = devm_request_irq(&pdev->dev, tx_irq,
+ rcar_canfd_channel_tx_interrupt, 0,
+ irq_name, gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq Tx (%d) failed, error %d\n",
+ tx_irq, err);
+ goto fail;
+ }
+ }
+
if (gpriv->fdmode) {
priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
priv->can.data_bittiming_const =
@@ -1636,7 +1759,11 @@ static int rcar_canfd_probe(struct platform_device *pdev)
struct device_node *of_child;
unsigned long channels_mask = 0;
int err, ch_irq, g_irq;
+ int g_err_irq, g_recc_irq;
bool fdmode = true; /* CAN FD only mode - default */
+ enum rcanfd_chip_id chip_id;
+
+ chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
fdmode = false; /* Classical CAN only mode */
@@ -1649,16 +1776,30 @@ static int rcar_canfd_probe(struct platform_device *pdev)
if (of_child && of_device_is_available(of_child))
channels_mask |= BIT(1); /* Channel 1 */
- ch_irq = platform_get_irq(pdev, 0);
- if (ch_irq < 0) {
- err = ch_irq;
- goto fail_dev;
- }
+ if (chip_id == RENESAS_RCAR_GEN3) {
+ ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
+ if (ch_irq < 0) {
+ /* For backward compatibility get irq by index */
+ ch_irq = platform_get_irq(pdev, 0);
+ if (ch_irq < 0)
+ return ch_irq;
+ }
- g_irq = platform_get_irq(pdev, 1);
- if (g_irq < 0) {
- err = g_irq;
- goto fail_dev;
+ g_irq = platform_get_irq_byname_optional(pdev, "g_int");
+ if (g_irq < 0) {
+ /* For backward compatibility get irq by index */
+ g_irq = platform_get_irq(pdev, 1);
+ if (g_irq < 0)
+ return g_irq;
+ }
+ } else {
+ g_err_irq = platform_get_irq_byname(pdev, "g_err");
+ if (g_err_irq < 0)
+ return g_err_irq;
+
+ g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
+ if (g_recc_irq < 0)
+ return g_recc_irq;
}
/* Global controller context */
@@ -1670,6 +1811,19 @@ static int rcar_canfd_probe(struct platform_device *pdev)
gpriv->pdev = pdev;
gpriv->channels_mask = channels_mask;
gpriv->fdmode = fdmode;
+ gpriv->chip_id = chip_id;
+
+ if (gpriv->chip_id == RENESAS_RZG2L) {
+ gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
+ if (IS_ERR(gpriv->rstc1))
+ return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
+ "failed to get rstp_n\n");
+
+ gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
+ if (IS_ERR(gpriv->rstc2))
+ return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
+ "failed to get rstc_n\n");
+ }
/* Peripheral clock */
gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
@@ -1699,7 +1853,7 @@ static int rcar_canfd_probe(struct platform_device *pdev)
}
fcan_freq = clk_get_rate(gpriv->can_clk);
- if (gpriv->fcan == RCANFD_CANFDCLK)
+ if (gpriv->fcan == RCANFD_CANFDCLK && gpriv->chip_id == RENESAS_RCAR_GEN3)
/* CANFD clock is further divided by (1/2) within the IP */
fcan_freq /= 2;
@@ -1711,20 +1865,51 @@ static int rcar_canfd_probe(struct platform_device *pdev)
gpriv->base = addr;
/* Request IRQ that's common for both channels */
- err = devm_request_irq(&pdev->dev, ch_irq,
- rcar_canfd_channel_interrupt, 0,
- "canfd.chn", gpriv);
- if (err) {
- dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
- ch_irq, err);
- goto fail_dev;
+ if (gpriv->chip_id == RENESAS_RCAR_GEN3) {
+ err = devm_request_irq(&pdev->dev, ch_irq,
+ rcar_canfd_channel_interrupt, 0,
+ "canfd.ch_int", gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ ch_irq, err);
+ goto fail_dev;
+ }
+
+ err = devm_request_irq(&pdev->dev, g_irq,
+ rcar_canfd_global_interrupt, 0,
+ "canfd.g_int", gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ g_irq, err);
+ goto fail_dev;
+ }
+ } else {
+ err = devm_request_irq(&pdev->dev, g_recc_irq,
+ rcar_canfd_global_recieve_fifo_interrupt, 0,
+ "canfd.g_recc", gpriv);
+
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ g_recc_irq, err);
+ goto fail_dev;
+ }
+
+ err = devm_request_irq(&pdev->dev, g_err_irq,
+ rcar_canfd_global_err_interrupt, 0,
+ "canfd.g_err", gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ g_err_irq, err);
+ goto fail_dev;
+ }
}
- err = devm_request_irq(&pdev->dev, g_irq,
- rcar_canfd_global_interrupt, 0,
- "canfd.gbl", gpriv);
+
+ err = reset_control_reset(gpriv->rstc1);
+ if (err)
+ goto fail_dev;
+ err = reset_control_reset(gpriv->rstc2);
if (err) {
- dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
- g_irq, err);
+ reset_control_assert(gpriv->rstc1);
goto fail_dev;
}
@@ -1733,7 +1918,7 @@ static int rcar_canfd_probe(struct platform_device *pdev)
if (err) {
dev_err(&pdev->dev,
"failed to enable peripheral clock, error %d\n", err);
- goto fail_dev;
+ goto fail_reset;
}
err = rcar_canfd_reset_controller(gpriv);
@@ -1790,6 +1975,9 @@ static int rcar_canfd_probe(struct platform_device *pdev)
rcar_canfd_disable_global_interrupts(gpriv);
fail_clk:
clk_disable_unprepare(gpriv->clkp);
+fail_reset:
+ reset_control_assert(gpriv->rstc1);
+ reset_control_assert(gpriv->rstc2);
fail_dev:
return err;
}
@@ -1810,6 +1998,9 @@ static int rcar_canfd_remove(struct platform_device *pdev)
/* Enter global sleep mode */
rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
clk_disable_unprepare(gpriv->clkp);
+ reset_control_assert(gpriv->rstc1);
+ reset_control_assert(gpriv->rstc2);
+
return 0;
}
@@ -1827,7 +2018,8 @@ static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
rcar_canfd_resume);
static const struct of_device_id rcar_canfd_of_table[] = {
- { .compatible = "renesas,rcar-gen3-canfd" },
+ { .compatible = "renesas,rcar-gen3-canfd", .data = (void *)RENESAS_RCAR_GEN3 },
+ { .compatible = "renesas,rzg2l-canfd", .data = (void *)RENESAS_RZG2L },
{ }
};
--
2.17.1
Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a7489dc70d1..51655c09f1f8 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -13,6 +13,13 @@
#address-cells = <2>;
#size-cells = <2>;
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
compatible = "fixed-clock";
@@ -89,6 +96,40 @@
status = "disabled";
};
+ canfd: can@10050000 {
+ compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
+ reg = <0 0x10050000 0 0x8000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx";
+ clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
+ <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
+ assigned-clock-rates = <50000000>;
+ resets = <&cpg R9A07G044_CANFD_RSTP_N>,
+ <&cpg R9A07G044_CANFD_RSTC_N>;
+ reset-names = "rstp_n", "rstc_n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ };
+
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> ---
> arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index 9a7489dc70d1..51655c09f1f8 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -13,6 +13,13 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + /* External CAN clock - to be overridden by boards that provide it */
> + can_clk: can {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> extal_clk: extal {
> compatible = "fixed-clock";
> @@ -89,6 +96,40 @@
> status = "disabled";
> };
>
> + canfd: can@10050000 {
> + compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> + reg = <0 0x10050000 0 0x8000>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "g_err", "g_recc",
> + "ch0_err", "ch0_rec", "ch0_trx",
> + "ch1_err", "ch1_rec", "ch1_trx";
> + clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> + <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> + <&can_clk>;
> + clock-names = "fck", "canfd", "can_clk";
> + assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> + assigned-clock-rates = <50000000>;
> + resets = <&cpg R9A07G044_CANFD_RSTP_N>,
> + <&cpg R9A07G044_CANFD_RSTC_N>;
> + reset-names = "rstp_n", "rstc_n";
> + power-domains = <&cpg>;
> + status = "disabled";
> +
> + channel0 {
> + status = "disabled";
> + };
> + channel1 {
> + status = "disabled";
> + };
> + };
> +
> i2c0: i2c@10058000 {
> #address-cells = <1>;
> #size-cells = <0>;
This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung West/Dortmund | Phone: +49-231-2826-924 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Marc,
On Wed, Aug 4, 2021 at 8:59 AM Marc Kleine-Budde <[email protected]> wrote:
>
> On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> > Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Biju Das <[email protected]>
> > ---
> > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
> > 1 file changed, 41 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > index 9a7489dc70d1..51655c09f1f8 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -13,6 +13,13 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + /* External CAN clock - to be overridden by boards that provide it */
> > + can_clk: can {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <0>;
> > + };
> > +
> > /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > extal_clk: extal {
> > compatible = "fixed-clock";
> > @@ -89,6 +96,40 @@
> > status = "disabled";
> > };
> >
> > + canfd: can@10050000 {
> > + compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> > + reg = <0 0x10050000 0 0x8000>;
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "g_err", "g_recc",
> > + "ch0_err", "ch0_rec", "ch0_trx",
> > + "ch1_err", "ch1_rec", "ch1_trx";
> > + clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> > + <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> > + <&can_clk>;
> > + clock-names = "fck", "canfd", "can_clk";
> > + assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> > + assigned-clock-rates = <50000000>;
> > + resets = <&cpg R9A07G044_CANFD_RSTP_N>,
> > + <&cpg R9A07G044_CANFD_RSTC_N>;
> > + reset-names = "rstp_n", "rstc_n";
> > + power-domains = <&cpg>;
> > + status = "disabled";
> > +
> > + channel0 {
> > + status = "disabled";
> > + };
> > + channel1 {
> > + status = "disabled";
> > + };
> > + };
> > +
> > i2c0: i2c@10058000 {
> > #address-cells = <1>;
> > #size-cells = <0>;
>
> This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
> i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
>
I had based the patch on top [1] (sorry I should have mentioned the
dependency), usually Geert picks up the DTS/I patches and queues it
via ARM tree. Shall I rebase it on net-next and re-send ?
@Geert Uytterhoeven Is that OK ?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v5.15
Cheers,
Prabhakar
> Marc
>
> --
> Pengutronix e.K. | Marc Kleine-Budde |
> Embedded Linux | https://www.pengutronix.de |
> Vertretung West/Dortmund | Phone: +49-231-2826-924 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Marc,
On Wed, Aug 4, 2021 at 10:11 AM Lad, Prabhakar
<[email protected]> wrote:
> On Wed, Aug 4, 2021 at 8:59 AM Marc Kleine-Budde <[email protected]> wrote:
> > On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> > > Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > Reviewed-by: Biju Das <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
> > > 1 file changed, 41 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > index 9a7489dc70d1..51655c09f1f8 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > @@ -13,6 +13,13 @@
> > > #address-cells = <2>;
> > > #size-cells = <2>;
> > >
> > > + /* External CAN clock - to be overridden by boards that provide it */
> > > + can_clk: can {
> > > + compatible = "fixed-clock";
> > > + #clock-cells = <0>;
> > > + clock-frequency = <0>;
> > > + };
> > > +
> > > /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > > extal_clk: extal {
> > > compatible = "fixed-clock";
> > > @@ -89,6 +96,40 @@
> > > status = "disabled";
> > > };
> > >
> > > + canfd: can@10050000 {
> > > + compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> > > + reg = <0 0x10050000 0 0x8000>;
> > > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-names = "g_err", "g_recc",
> > > + "ch0_err", "ch0_rec", "ch0_trx",
> > > + "ch1_err", "ch1_rec", "ch1_trx";
> > > + clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> > > + <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> > > + <&can_clk>;
> > > + clock-names = "fck", "canfd", "can_clk";
> > > + assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> > > + assigned-clock-rates = <50000000>;
> > > + resets = <&cpg R9A07G044_CANFD_RSTP_N>,
> > > + <&cpg R9A07G044_CANFD_RSTC_N>;
> > > + reset-names = "rstp_n", "rstc_n";
> > > + power-domains = <&cpg>;
> > > + status = "disabled";
> > > +
> > > + channel0 {
> > > + status = "disabled";
> > > + };
> > > + channel1 {
> > > + status = "disabled";
> > > + };
> > > + };
> > > +
> > > i2c0: i2c@10058000 {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> >
> > This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
> > i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
> >
> I had based the patch on top [1] (sorry I should have mentioned the
> dependency), usually Geert picks up the DTS/I patches and queues it
> via ARM tree. Shall I rebase it on net-next and re-send ?
>
> @Geert Uytterhoeven Is that OK ?
Please do not take Renesas DTS patches through the netdev tree
(or any other subsystem tree).
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v5.15
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 09.08.2021 15:05:30, Geert Uytterhoeven wrote:
> > > This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
> > > i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
> > >
> > I had based the patch on top [1] (sorry I should have mentioned the
> > dependency), usually Geert picks up the DTS/I patches and queues it
> > via ARM tree. Shall I rebase it on net-next and re-send ?
> >
> > @Geert Uytterhoeven Is that OK ?
>
> Please do not take Renesas DTS patches through the netdev tree
> (or any other subsystem tree).
Ok, I'm taking path 1 and 2 then.
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung West/Dortmund | Phone: +49-231-2826-924 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Geert,
On Tue, Aug 10, 2021 at 9:27 AM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Tue, Jul 27, 2021 at 3:30 PM Lad Prabhakar
> <[email protected]> wrote:
> > CANFD block on RZ/G2L SoC is almost identical to one found on
> > R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
> > are split into different sources and the IP doesn't divide (1/2)
> > CANFD clock within the IP.
> >
> > This patch adds compatible string for RZ/G2L family and splits
> > the irq handlers to accommodate both RZ/G2L and R-Car Gen3 SoC's.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Biju Das <[email protected]>
>
> Thanks for your patch!
>
> I've just noticed a set of silly typos:
>
> > --- a/drivers/net/can/rcar/rcar_canfd.c
> > +++ b/drivers/net/can/rcar/rcar_canfd.c
>
> > +static void rcar_canfd_handle_global_recieve(struct rcar_canfd_global *gpriv, u32 ch)
>
> receive (everywhere)
>
Ouch, I'll respin with the typo's fixed.
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
On Tue, Aug 10, 2021 at 9:39 AM Marc Kleine-Budde <[email protected]> wrote:
>
> On 10.08.2021 09:36:50, Lad, Prabhakar wrote:
> > > > +static void rcar_canfd_handle_global_recieve(struct rcar_canfd_global *gpriv, u32 ch)
> > >
> > > receive (everywhere)
> > >
> > Ouch, I'll respin with the typo's fixed.
>
> No need, I've fixed it here.
>
Thanks Marc.
Cheers,
Prabhakar
> Marc
>
> --
> Pengutronix e.K. | Marc Kleine-Budde |
> Embedded Linux | https://www.pengutronix.de |
> Vertretung West/Dortmund | Phone: +49-231-2826-924 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Prabhakar,
On Tue, Jul 27, 2021 at 3:30 PM Lad Prabhakar
<[email protected]> wrote:
> CANFD block on RZ/G2L SoC is almost identical to one found on
> R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
> are split into different sources and the IP doesn't divide (1/2)
> CANFD clock within the IP.
>
> This patch adds compatible string for RZ/G2L family and splits
> the irq handlers to accommodate both RZ/G2L and R-Car Gen3 SoC's.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Thanks for your patch!
I've just noticed a set of silly typos:
> --- a/drivers/net/can/rcar/rcar_canfd.c
> +++ b/drivers/net/can/rcar/rcar_canfd.c
> +static void rcar_canfd_handle_global_recieve(struct rcar_canfd_global *gpriv, u32 ch)
receive (everywhere)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 10.08.2021 09:36:50, Lad, Prabhakar wrote:
> > > +static void rcar_canfd_handle_global_recieve(struct rcar_canfd_global *gpriv, u32 ch)
> >
> > receive (everywhere)
> >
> Ouch, I'll respin with the typo's fixed.
No need, I've fixed it here.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung West/Dortmund | Phone: +49-231-2826-924 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Tue, Jul 27, 2021 at 3:30 PM Lad Prabhakar
<[email protected]> wrote:
> Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds