From: Abel Vesa <[email protected]>
This work is taken from NXP's internal tree. In order to fast track
the upstreaming, I took the latest versions of the files, trying to
keep the original author where possible.
With this patchset, i.MX8DXL boots to prompt with SD rootfs.
Abel Vesa (2):
arm64: dts: imx8-ss-lsio: Add mu5a mailbox
arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
Jacky Bai (5):
arm64: dts: freescale: Add the top level dtsi support for imx8dxl
arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
arm64: dts: imx8dxl: Add i.MX8DXL evk board support
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 53 +++
.../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 133 ++++++
.../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 34 ++
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 68 +++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 ++++++++++++
8 files changed, 1013 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
--
2.31.1
From: Jacky Bai <[email protected]>
On i.MX8DXL, the Connectivity subsystem includes below peripherals:
1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
1x eMMC, 2x SD, 1x NAND.
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
---
.../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 133 ++++++++++++++++++
1 file changed, 133 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
new file mode 100644
index 000000000000..c10801926de3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/delete-node/ &enet1_lpcg;
+/delete-node/ &fec2;
+
+&conn_subsys {
+ conn_enet0_root_clk: clock-conn-enet0-root {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "conn_enet0_root_clk";
+ };
+
+ eqos: ethernet@5b050000 {
+ compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
+ reg = <0x5b050000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth_wake_irq", "macirq";
+ clocks = <&eqos_lpcg 2>,
+ <&eqos_lpcg 4>,
+ <&eqos_lpcg 0>,
+ <&eqos_lpcg 3>,
+ <&eqos_lpcg 1>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <125000000>;
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ clk_csr = <0>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@5b0e0000 {
+ compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
+ reg = <0x5b0e0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ /*
+ * usbotg1 and usbotg2 share one clcok
+ * scfw disable clock access and keep it always on
+ * in case other core (M4) use one of these.
+ */
+ clocks = <&clk_dummy>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ #stream-id-cells = <1>;
+ power-domains = <&pd IMX_SC_R_USB_1>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@5b0e0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
+ reg = <0x5b0e0200 0x200>;
+ };
+
+ usbphy2: usbphy@0x5b110000 {
+ compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
+ reg = <0x5b110000 0x1000>;
+ clocks = <&usb2_2_lpcg 0>;
+ status = "disabled";
+ };
+
+ eqos_lpcg: clock-controller@5b240000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b240000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_enet0_root_clk>,
+ <&conn_axi_clk>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>;
+ bit-offset = <0 8 16 20 24>;
+ clock-output-names = "eqos_ptp",
+ "eqos_mem_clk",
+ "eqos_aclk",
+ "eqos_clk",
+ "eqos_csr_clk";
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ };
+
+ usb2_2_lpcg: clock-controller@5b280000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b280000 0x10000>;
+ #clock-cells = <1>;
+
+ bit-offset = <28>;
+ clocks = <&conn_ipg_clk>;
+ clock-output-names = "usboh3_2_phy_ipg_clk";
+ };
+
+};
+
+&enet0_lpcg {
+ clocks = <&conn_enet0_root_clk>,
+ <&conn_enet0_root_clk>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
+};
+
+&fec1 {
+ compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <125000000>;
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc3 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.31.1
From: Abel Vesa <[email protected]>
Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
the i.MX8DXL specific properties.
Signed-off-by: Clark Wang <[email protected]>
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
---
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
new file mode 100644
index 000000000000..12ccbc6587ca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+&audio_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&dma_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&i2c0 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c3 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart0 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart1 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart2 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart3 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+};
+
--
2.31.1
From: Jacky Bai <[email protected]>
On i.MX8DXL, the LSIO subsystem includes below devices:
1x Inline Encryption Engine (IEE)
1x FlexSPI
4x Pulse Width Modulator (PWM)
5x General Purpose Timer (GPT)
8x GPIO
14x Message Unit (MU)
256KB On-Chip Memory (OCRAM)
compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
property need to be updated.
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
---
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
new file mode 100644
index 000000000000..7496a38694df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+&lsio_gpio0 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.31.1
On Tue, May 18, 2021 at 1:15 AM <[email protected]> wrote:
>
> From: Abel Vesa <[email protected]>
>
> Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
> the i.MX8DXL specific properties.
>
> Signed-off-by: Clark Wang <[email protected]>
> Signed-off-by: Jacky Bai <[email protected]>
> Signed-off-by: Abel Vesa <[email protected]>
Please add dt-binding update as well.
Better along with this patch series
> ---
> .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 53 +++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> new file mode 100644
> index 000000000000..12ccbc6587ca
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +&audio_ipg_clk {
> + clock-frequency = <160000000>;
> +};
> +
> +&dma_ipg_clk {
> + clock-frequency = <160000000>;
> +};
> +
> +&i2c0 {
> + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c1 {
> + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c2 {
> + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c3 {
> + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart0 {
> + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart1 {
> + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart2 {
> + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart3 {
> + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, May 18, 2021 at 1:16 AM <[email protected]> wrote:
>
> From: Jacky Bai <[email protected]>
>
> On i.MX8DXL, the LSIO subsystem includes below devices:
>
> 1x Inline Encryption Engine (IEE)
> 1x FlexSPI
> 4x Pulse Width Modulator (PWM)
> 5x General Purpose Timer (GPT)
> 8x GPIO
> 14x Message Unit (MU)
> 256KB On-Chip Memory (OCRAM)
>
> compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
> property need to be updated.
>
> Signed-off-by: Jacky Bai <[email protected]>
> Signed-off-by: Abel Vesa <[email protected]>
> ---
> .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
> new file mode 100644
> index 000000000000..7496a38694df
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +&lsio_gpio0 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio1 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio2 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio3 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio4 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio5 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio6 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio7 {
> + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu0 {
> + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu1 {
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu2 {
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu3 {
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu4 {
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +};
pls add the missing mu5/13
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, May 18, 2021 at 1:15 AM <[email protected]> wrote:
>
> From: Jacky Bai <[email protected]>
>
> On i.MX8DXL, the Connectivity subsystem includes below peripherals:
> 1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
> 1x eMMC, 2x SD, 1x NAND.
>
> Signed-off-by: Jacky Bai <[email protected]>
> Signed-off-by: Abel Vesa <[email protected]>
> ---
> .../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 133 ++++++++++++++++++
> 1 file changed, 133 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> new file mode 100644
> index 000000000000..c10801926de3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +/delete-node/ &enet1_lpcg;
> +/delete-node/ &fec2;
> +
> +&conn_subsys {
> + conn_enet0_root_clk: clock-conn-enet0-root {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <250000000>;
> + clock-output-names = "conn_enet0_root_clk";
> + };
> +
> + eqos: ethernet@5b050000 {
> + compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
> + reg = <0x5b050000 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eth_wake_irq", "macirq";
> + clocks = <&eqos_lpcg 2>,
> + <&eqos_lpcg 4>,
> + <&eqos_lpcg 0>,
> + <&eqos_lpcg 3>,
> + <&eqos_lpcg 1>;
need fix LPCG index
pls refer to binding doc
> + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
> + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <125000000>;
> + power-domains = <&pd IMX_SC_R_ENET_1>;
> + clk_csr = <0>;
> + status = "disabled";
> + };
> +
> + usbotg2: usb@5b0e0000 {
> + compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
> + reg = <0x5b0e0000 0x200>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,usbphy = <&usbphy2>;
> + fsl,usbmisc = <&usbmisc2 0>;
> + /*
> + * usbotg1 and usbotg2 share one clcok
> + * scfw disable clock access and keep it always on
> + * in case other core (M4) use one of these.
> + */
> + clocks = <&clk_dummy>;
> + ahb-burst-config = <0x0>;
> + tx-burst-size-dword = <0x10>;
> + rx-burst-size-dword = <0x10>;
> + #stream-id-cells = <1>;
> + power-domains = <&pd IMX_SC_R_USB_1>;
> + status = "disabled";
> + };
> +
> + usbmisc2: usbmisc@5b0e0200 {
> + #index-cells = <1>;
> + compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
> + reg = <0x5b0e0200 0x200>;
> + };
> +
> + usbphy2: usbphy@0x5b110000 {
> + compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
> + reg = <0x5b110000 0x1000>;
> + clocks = <&usb2_2_lpcg 0>;
> + status = "disabled";
> + };
> +
> + eqos_lpcg: clock-controller@5b240000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5b240000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&conn_enet0_root_clk>,
> + <&conn_axi_clk>,
> + <&conn_axi_clk>,
> + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
> + <&conn_ipg_clk>;
> + bit-offset = <0 8 16 20 24>;
> + clock-output-names = "eqos_ptp",
> + "eqos_mem_clk",
> + "eqos_aclk",
> + "eqos_clk",
> + "eqos_csr_clk";
> + power-domains = <&pd IMX_SC_R_ENET_1>;
> + };
> +
> + usb2_2_lpcg: clock-controller@5b280000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5b280000 0x10000>;
> + #clock-cells = <1>;
> +
> + bit-offset = <28>;
> + clocks = <&conn_ipg_clk>;
> + clock-output-names = "usboh3_2_phy_ipg_clk";
> + };
> +
> +};
> +
> +&enet0_lpcg {
> + clocks = <&conn_enet0_root_clk>,
> + <&conn_enet0_root_clk>,
> + <&conn_axi_clk>,
> + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
> + <&conn_ipg_clk>,
> + <&conn_ipg_clk>;
> +};
> +
> +&fec1 {
> + compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
> + assigned-clock-rates = <125000000>;
> +};
> +
> +&usdhc1 {
> + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&usdhc2 {
> + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&usdhc3 {
> + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 21-05-18 15:52:00, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:15 AM <[email protected]> wrote:
> >
> > From: Abel Vesa <[email protected]>
> >
> > Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
> > the i.MX8DXL specific properties.
> >
> > Signed-off-by: Clark Wang <[email protected]>
> > Signed-off-by: Jacky Bai <[email protected]>
> > Signed-off-by: Abel Vesa <[email protected]>
>
> Please add dt-binding update as well.
> Better along with this patch series
>
Will do in the next version.
> > ---
> > .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 53 +++++++++++++++++++
> > 1 file changed, 53 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > new file mode 100644
> > index 000000000000..12ccbc6587ca
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + */
> > +
> > +&audio_ipg_clk {
> > + clock-frequency = <160000000>;
> > +};
> > +
> > +&dma_ipg_clk {
> > + clock-frequency = <160000000>;
> > +};
> > +
> > +&i2c0 {
> > + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c1 {
> > + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c2 {
> > + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c3 {
> > + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart0 {
> > + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart1 {
> > + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart2 {
> > + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart3 {
> > + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
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