Patch series adds support for enabling the PCIe controller and
UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
PCIe1 is Gen3 X2 are added.
UNIPHY changes depends on
https://lore.kernel.org/all/[email protected]/
PCIe driver change depends on
https://lore.kernel.org/all/[email protected]/
Praveenkumar I (10):
dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY
clk: qcom: ipq5332: Add separate clocks for PCIe and USB for Combo PHY
arm64: dts: qcom: ipq5332: Add separate entry for USB pipe clock
phy: qcom: Add support for Pipe clock rate from device data
dt-bindings: phy: qcom,uniphy-pcie: Add ipq5332 bindings
phy: qcom: ipq5332: Add support for g3x1 and g3x2 PCIe PHYs
dt-bindings: PCI: qcom: Add IPQ5332 SoC
pci: qcom: Add support for IPQ5332
arm64: dts: qcom: ipq5332: Add PCIe related nodes
arm64: dts: qcom: ipq5332: Enable PCIe phys and controllers
.../bindings/clock/qcom,ipq5332-gcc.yaml | 6 +-
.../devicetree/bindings/pci/qcom,pcie.yaml | 36 ++++
.../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++-
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 188 +++++++++++++++++-
drivers/clk/qcom/gcc-ipq5332.c | 7 +-
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 49 ++++-
8 files changed, 412 insertions(+), 14 deletions(-)
--
2.34.1
Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
interface (PCIe/USB) can use this combo PHY and the PHY drivers are
different for PCIe and USB. Hence separate the PCIe and USB pipe clock
source from DT, and individual driver node can be used as a clock source
separately in the gcc. Change the dt-bindings accordingly.
Signed-off-by: Praveenkumar I <[email protected]>
---
.../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
index 718fe0625424..b22643037119 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
@@ -28,7 +28,8 @@ properties:
- description: Sleep clock source
- description: PCIE 2lane PHY pipe clock source
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
- - description: USB PCIE wrapper pipe clock source
+ - description: PCIE wrapper pipe clock source
+ - description: USB wrapper pipe clock source
required:
- compatible
@@ -45,7 +46,8 @@ examples:
<&sleep_clk>,
<&pcie_2lane_phy_pipe_clk>,
<&pcie_2lane_phy_pipe_clk_x1>,
- <&usb_pcie_wrapper_pipe_clk>;
+ <&pcie_wrapper_pipe_clk>,
+ <&usb_wrapper_pipe_clk>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
--
2.34.1
Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
interface (PCIe/USB) can use this combo PHY and the PHY drivers are
different for PCIe and USB. Hence separate the PCIe and USB pipe clock
source from DT, and individual driver node can be used as a clock source
separately in the gcc. Add separate enum for PCIe and USB pipe clock and
change the parent in corresponding structures.
Signed-off-by: Praveenkumar I <[email protected]>
---
drivers/clk/qcom/gcc-ipq5332.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index f98591148a97..aa0f616c3b1b 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -25,7 +25,8 @@ enum {
DT_SLEEP_CLK,
DT_PCIE_2LANE_PHY_PIPE_CLK,
DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
- DT_USB_PCIE_WRAPPER_PIPE_CLK,
+ DT_PCIE_WRAPPER_PIPE_CLK,
+ DT_USB_WRAPPER_PIPE_CLK,
};
enum {
@@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x1_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
- .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
+ .index = DT_PCIE_WRAPPER_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
@@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
- .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
+ .index = DT_USB_WRAPPER_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
--
2.34.1
Add separate entry in clock-controller for USB pipe clock.
Signed-off-by: Praveenkumar I <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 42e2e48b2bc3..f0d92effb783 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -213,6 +213,7 @@ gcc: clock-controller@1800000 {
<&sleep_clk>,
<0>,
<0>,
+ <0>,
<0>;
};
--
2.34.1
Qualcomm IPQ5332 has single-lane and dual-lane PCIe UNIPHY
with Gen 3 support. This UNIPHY is similar to the one found
on Qualcomm IPQ5018. Hence add the bindings in qcom,uniphy-pcie.
Clocks and resets are different for IPQ5332. Update the
bindings to support both IPQ5018 and IPQ5332.
Signed-off-by: Praveenkumar I <[email protected]>
---
This patch depends on the below series which adds PCIe support in
Qualcomm IPQ5018
https://lore.kernel.org/all/[email protected]/
.../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++++++++++++++--
1 file changed, 58 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
index 6b2574f9532e..205eaec2291e 100644
--- a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
@@ -20,19 +20,20 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
clock-names:
- items:
- - const: pipe_clk
+ minItems: 1
+ maxItems: 4
resets:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
reset-names:
- items:
- - const: phy
- - const: phy_phy
+ minItems: 2
+ maxItems: 3
"#phy-cells":
const: 0
@@ -54,6 +55,56 @@ required:
- "#clock-cells"
- clock-output-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq5018-uniphy-pcie-gen2x1
+ - qcom,ipq5018-uniphy-pcie-gen2x2
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: pipe_clk
+ resets:
+ minItems: 2
+ maxItems: 2
+ reset-name:
+ items:
+ - const: phy
+ - const: phy_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq5332-uniphy-pcie-gen3x1
+ - qcom,ipq5332-uniphy-pcie-gen3x2
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: pipe
+ - const: lane_m
+ - const: lane_s
+ - const: phy_ahb
+ resets:
+ minItems: 2
+ maxItems: 2
+ reset-name:
+ items:
+ - const: phy
+ - const: phy_ahb
+
additionalProperties: false
examples:
--
2.34.1
Qualcomm IPQ5332 has the same PCIe UNIPHY PHY with different pipe
clock rate. Add support to define the pipe clock rate in device
data.
Signed-off-by: Praveenkumar I <[email protected]>
---
This patch depends on the below series which adds PCIe support in
Qualcomm IPQ5018
https://lore.kernel.org/all/[email protected]/
drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
index 5ef6ae7276cf..9f9a03faf6fa 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
@@ -54,6 +54,7 @@ struct uniphy_pcie_data {
unsigned int phy_type;
const struct uniphy_regs *init_seq;
unsigned int init_seq_num;
+ unsigned int pipe_clk_rate;
};
struct qcom_uniphy_pcie {
@@ -117,6 +118,7 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = {
.phy_type = PHY_TYPE_PCIE_GEN2,
.init_seq = ipq5018_regs,
.init_seq_num = ARRAY_SIZE(ipq5018_regs),
+ .pipe_clk_rate = 125000000,
};
static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
@@ -232,6 +234,7 @@ static int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy,
struct device_node *np)
{
+ const struct uniphy_pcie_data *data = phy->data;
struct clk_fixed_rate *fixed;
struct clk_init_data init = { };
int ret;
@@ -247,7 +250,7 @@ static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy,
return -ENOMEM;
init.ops = &clk_fixed_rate_ops;
- fixed->fixed_rate = 125000000;
+ fixed->fixed_rate = data->pipe_clk_rate;
fixed->hw.init = &init;
ret = devm_clk_hw_register(phy->dev, &fixed->hw);
--
2.34.1
Add support for the PCIe controller on the Qualcomm
IPQ5332 SoC to the bindings.
Signed-off-by: Praveenkumar I <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index eadba38171e1..af5e67d2a984 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -21,6 +21,7 @@ properties:
- qcom,pcie-apq8064
- qcom,pcie-apq8084
- qcom,pcie-ipq4019
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq6018
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064-v2
@@ -170,6 +171,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq6018
- qcom,pcie-ipq8074-gen3
then:
@@ -332,6 +334,39 @@ allOf:
- const: ahb # AHB reset
- const: phy_ahb # PHY AHB reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq5332
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ maxItems: 6
+ clock-names:
+ items:
+ - const: ahb # AHB clock
+ - const: aux # Auxiliary clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: axi_bridge # AXI bridge clock
+ - const: rchng
+ resets:
+ minItems: 8
+ maxItems: 8
+ reset-names:
+ items:
+ - const: pipe # PIPE reset
+ - const: sticky # Core sticky reset
+ - const: axi_m_sticky # AXI master sticky reset
+ - const: axi_m # AXI master reset
+ - const: axi_s_sticky # AXI slave sticky reset
+ - const: axi_s # AXI slave reset
+ - const: ahb # AHB reset
+ - const: aux # AUX reset
+
- if:
properties:
compatible:
@@ -790,6 +825,7 @@ allOf:
enum:
- qcom,pcie-apq8064
- qcom,pcie-ipq4019
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
--
2.34.1
Add support for single-lane and dual-lane PCIe UNIPHY found on
Qualcomm IPQ5332 platform. This UNIPHY is similar to the one
present in Qualcomm IPQ5018.
Signed-off-by: Praveenkumar I <[email protected]>
---
This patch depends on the below series which adds PCIe support in
Qualcomm IPQ5018
https://lore.kernel.org/all/[email protected]/
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
index 9f9a03faf6fa..aa71b85eb50e 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
@@ -34,6 +34,10 @@
#define SSCG_CTRL_REG_6 0xb0
#define PCS_INTERNAL_CONTROL_2 0x2d8
+#define PHY_CFG_PLLCFG 0x220
+#define PHY_CFG_EIOS_DTCT_REG 0x3e4
+#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
+
#define PHY_MODE_FIXED 0x1
enum qcom_uniphy_pcie_type {
@@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = {
},
};
+static const struct uniphy_regs ipq5332_regs[] = {
+ {
+ .offset = PHY_CFG_PLLCFG,
+ .val = 0x30,
+ },
+ {
+ .offset = PHY_CFG_EIOS_DTCT_REG,
+ .val = 0x53ef,
+ },
+ {
+ .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
+ .val = 0xCf,
+ },
+};
+
static const struct uniphy_pcie_data ipq5018_2x2_data = {
.lanes = 2,
.lane_offset = 0x800,
@@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = {
.pipe_clk_rate = 125000000,
};
+static const struct uniphy_pcie_data ipq5332_x2_data = {
+ .lanes = 2,
+ .lane_offset = 0x800,
+ .phy_type = PHY_TYPE_PCIE_GEN3,
+ .init_seq = ipq5332_regs,
+ .init_seq_num = ARRAY_SIZE(ipq5332_regs),
+ .pipe_clk_rate = 250000000,
+};
+
+static const struct uniphy_pcie_data ipq5332_x1_data = {
+ .lanes = 1,
+ .phy_type = PHY_TYPE_PCIE_GEN3,
+ .init_seq = ipq5332_regs,
+ .init_seq_num = ARRAY_SIZE(ipq5332_regs),
+ .pipe_clk_rate = 250000000,
+};
+
static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
{
const struct uniphy_pcie_data *data = phy->data;
@@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
.compatible = "qcom,ipq5018-uniphy-pcie-gen2x2",
.data = &ipq5018_2x2_data,
},
+ {
+ .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2",
+ .data = &ipq5332_x2_data,
+ },
+ {
+ .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1",
+ .data = &ipq5332_x1_data,
+ },
{ /* Sentinel */ },
};
MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
--
2.34.1
Enable the PCIe controller and PHY nodes for RDP 441.
Signed-off-by: Praveenkumar I <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
index 846413817e9a..83eca8435cff 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
@@ -62,4 +62,78 @@ data-pins {
bias-pull-up;
};
};
+
+ pcie0_default: pcie0-default-state {
+ clkreq-n-pins {
+ pins = "gpio37";
+ function = "pcie0_clk";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio39";
+ function = "pcie0_wake";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default: pcie1-default-state {
+ clkreq-n-pins {
+ pins = "gpio46";
+ function = "pcie1_clk";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio47";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio48";
+ function = "pcie1_wake";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default>;
+
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default>;
+
+ perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
+ status = "okay";
};
--
2.34.1
Add phy and controller nodes for pcie0_x1 and pcie1_x2.
Signed-off-by: Praveenkumar I <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 189 +++++++++++++++++++++++++-
1 file changed, 187 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index f0d92effb783..367641ab4938 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -166,6 +166,58 @@ usbphy0: phy@7b000 {
status = "disabled";
};
+ pcie0_phy: phy@4b0000{
+ compatible = "qcom,ipq5332-uniphy-pcie-gen3x1";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_SNOC_PCIE3_1LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE3_1LANE_S_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+ clock-names = "pipe",
+ "lane_m",
+ "lane_s",
+ "phy_ahb";
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>;
+ reset-names = "phy",
+ "phy_cfg",
+ "phy_ahb";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk_src";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@4b1000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-gen3x2";
+ reg = <0x004b1000 0x1000>;
+
+ clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+ <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+ clock-names = "pipe",
+ "lane_m",
+ "lane_s",
+ "phy_ahb";
+
+ resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>;
+ reset-names = "phy",
+ "phy_ahb";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie1_pipe_clk_src";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
qfprom: efuse@a4000 {
compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x721>;
@@ -211,9 +263,9 @@ gcc: clock-controller@1800000 {
#power-domain-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
+ <&pcie1_phy>,
<0>,
- <0>,
- <0>,
+ <&pcie0_phy>,
<0>;
};
@@ -359,6 +411,139 @@ usb_dwc: usb@8a00000 {
};
};
+ pcie0: pcie@20000000 {
+ compatible = "qcom,pcie-ipq5332";
+ reg = <0x20000000 0xf1d>,
+ <0x20000F20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x00080000 0x3000>,
+ <0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, /* I/O */
+ <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* MEM */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ clocks = <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>;
+
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+ <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>;
+
+ reset-names = "pipe",
+ "sticky",
+ "axi_m_sticky",
+ "axi_m",
+ "axi_s_sticky",
+ "axi_s",
+ "ahb",
+ "aux";
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+ status = "disabled";
+ };
+
+ pcie1: pcie@18000000 {
+ compatible = "qcom,pcie-ipq5332";
+ reg = <0x18000000 0xf1d>,
+ <0x18000F20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x00088000 0x3000>,
+ <0x18100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0 0x18200000 0x18200000 0 0x00100000>, /* I/O */
+ <0x02000000 0 0x18300000 0x18300000 0 0x07d00000>; /* MEM */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 412 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 413 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 414 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ clocks = <&gcc GCC_PCIE3X2_AHB_CLK>,
+ <&gcc GCC_PCIE3X2_AUX_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>;
+
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+ <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AUX_CLK_ARES>;
+
+ reset-names = "pipe",
+ "sticky",
+ "axi_m_sticky",
+ "axi_m",
+ "axi_s_sticky",
+ "axi_s",
+ "ahb",
+ "aux";
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+ status = "disabled";
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.34.1
The Qualcomm IPQ5332 PCIe controller instances are based on
SNPS core 5.90a with Gen3 Single-lane and Dual-lane support.
The Qualcomm IP rev is 1.27.0 and hence using the 1_27_0 ops.
Signed-off-by: Praveenkumar I <[email protected]>
---
This patch depends on the below series which adds PCIe support in
Qualcomm IPQ9574
https://lore.kernel.org/all/[email protected]/
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 109df587234e..3d54de1a71df 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
+ { .compatible = "qcom,pcie-ipq5332", .data = &cfg_1_27_0 },
{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
--
2.34.1
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <[email protected]> wrote:
>
> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
> interface (PCIe/USB) can use this combo PHY and the PHY drivers are
> different for PCIe and USB. Hence separate the PCIe and USB pipe clock
> source from DT, and individual driver node can be used as a clock source
> separately in the gcc. Add separate enum for PCIe and USB pipe clock and
> change the parent in corresponding structures.
>
> Signed-off-by: Praveenkumar I <[email protected]>
Please use your full name for the git authorship and or the S-o-B
tags. This applies to the whole series.
Other than that:
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/clk/qcom/gcc-ipq5332.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> index f98591148a97..aa0f616c3b1b 100644
> --- a/drivers/clk/qcom/gcc-ipq5332.c
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -25,7 +25,8 @@ enum {
> DT_SLEEP_CLK,
> DT_PCIE_2LANE_PHY_PIPE_CLK,
> DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
> - DT_USB_PCIE_WRAPPER_PIPE_CLK,
> + DT_PCIE_WRAPPER_PIPE_CLK,
> + DT_USB_WRAPPER_PIPE_CLK,
> };
>
> enum {
> @@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
> .hw.init = &(struct clk_init_data) {
> .name = "gcc_pcie3x1_0_pipe_clk_src",
> .parent_data = &(const struct clk_parent_data) {
> - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
> + .index = DT_PCIE_WRAPPER_PIPE_CLK,
> },
> .num_parents = 1,
> .ops = &clk_regmap_phy_mux_ops,
> @@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
> .hw.init = &(struct clk_init_data) {
> .name = "gcc_usb0_pipe_clk_src",
> .parent_data = &(const struct clk_parent_data) {
> - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
> + .index = DT_USB_WRAPPER_PIPE_CLK,
> },
> .num_parents = 1,
> .ops = &clk_regmap_phy_mux_ops,
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <[email protected]> wrote:
>
> Add support for single-lane and dual-lane PCIe UNIPHY found on
> Qualcomm IPQ5332 platform. This UNIPHY is similar to the one
> present in Qualcomm IPQ5018.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> This patch depends on the below series which adds PCIe support in
> Qualcomm IPQ5018
> https://lore.kernel.org/all/[email protected]/
>
> .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> index 9f9a03faf6fa..aa71b85eb50e 100644
> --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> @@ -34,6 +34,10 @@
> #define SSCG_CTRL_REG_6 0xb0
> #define PCS_INTERNAL_CONTROL_2 0x2d8
>
> +#define PHY_CFG_PLLCFG 0x220
> +#define PHY_CFG_EIOS_DTCT_REG 0x3e4
> +#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
> +
> #define PHY_MODE_FIXED 0x1
>
> enum qcom_uniphy_pcie_type {
> @@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = {
> },
> };
>
> +static const struct uniphy_regs ipq5332_regs[] = {
> + {
> + .offset = PHY_CFG_PLLCFG,
> + .val = 0x30,
> + },
> + {
> + .offset = PHY_CFG_EIOS_DTCT_REG,
> + .val = 0x53ef,
> + },
> + {
> + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
> + .val = 0xCf,
> + },
> +};
> +
> static const struct uniphy_pcie_data ipq5018_2x2_data = {
> .lanes = 2,
> .lane_offset = 0x800,
> @@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = {
> .pipe_clk_rate = 125000000,
> };
>
> +static const struct uniphy_pcie_data ipq5332_x2_data = {
> + .lanes = 2,
> + .lane_offset = 0x800,
> + .phy_type = PHY_TYPE_PCIE_GEN3,
> + .init_seq = ipq5332_regs,
> + .init_seq_num = ARRAY_SIZE(ipq5332_regs),
> + .pipe_clk_rate = 250000000,
> +};
> +
> +static const struct uniphy_pcie_data ipq5332_x1_data = {
> + .lanes = 1,
> + .phy_type = PHY_TYPE_PCIE_GEN3,
> + .init_seq = ipq5332_regs,
> + .init_seq_num = ARRAY_SIZE(ipq5332_regs),
> + .pipe_clk_rate = 250000000,
> +};
Please keep structs sorted out.
> +
> static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
> {
> const struct uniphy_pcie_data *data = phy->data;
> @@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
> .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2",
> .data = &ipq5018_2x2_data,
> },
> + {
> + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2",
> + .data = &ipq5332_x2_data,
> + },
> + {
> + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1",
> + .data = &ipq5332_x1_data,
The entries here should be sorted out.
> + },
> { /* Sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <[email protected]> wrote:
>
> Qualcomm IPQ5332 has the same PCIe UNIPHY PHY with different pipe
> clock rate. Add support to define the pipe clock rate in device
> data.
>
> Signed-off-by: Praveenkumar I <[email protected]>
With the name fixed:
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> This patch depends on the below series which adds PCIe support in
> Qualcomm IPQ5018
> https://lore.kernel.org/all/[email protected]/
>
> drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> index 5ef6ae7276cf..9f9a03faf6fa 100644
> --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> @@ -54,6 +54,7 @@ struct uniphy_pcie_data {
> unsigned int phy_type;
> const struct uniphy_regs *init_seq;
> unsigned int init_seq_num;
> + unsigned int pipe_clk_rate;
> };
>
> struct qcom_uniphy_pcie {
> @@ -117,6 +118,7 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = {
> .phy_type = PHY_TYPE_PCIE_GEN2,
> .init_seq = ipq5018_regs,
> .init_seq_num = ARRAY_SIZE(ipq5018_regs),
> + .pipe_clk_rate = 125000000,
> };
>
> static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
> @@ -232,6 +234,7 @@ static int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
> static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy,
> struct device_node *np)
> {
> + const struct uniphy_pcie_data *data = phy->data;
> struct clk_fixed_rate *fixed;
> struct clk_init_data init = { };
> int ret;
> @@ -247,7 +250,7 @@ static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy,
> return -ENOMEM;
>
> init.ops = &clk_fixed_rate_ops;
> - fixed->fixed_rate = 125000000;
> + fixed->fixed_rate = data->pipe_clk_rate;
> fixed->hw.init = &init;
>
> ret = devm_clk_hw_register(phy->dev, &fixed->hw);
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <[email protected]> wrote:
>
> Add support for the PCIe controller on the Qualcomm
> IPQ5332 SoC to the bindings.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index eadba38171e1..af5e67d2a984 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -21,6 +21,7 @@ properties:
> - qcom,pcie-apq8064
> - qcom,pcie-apq8084
> - qcom,pcie-ipq4019
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064-v2
> @@ -170,6 +171,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8074-gen3
> then:
> @@ -332,6 +334,39 @@ allOf:
> - const: ahb # AHB reset
> - const: phy_ahb # PHY AHB reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq5332
As you seem to be depending on the ipq9574, could you please reuse the
DT entry too?
> + then:
> + properties:
> + clocks:
> + minItems: 6
> + maxItems: 6
> + clock-names:
> + items:
> + - const: ahb # AHB clock
> + - const: aux # Auxiliary clock
> + - const: axi_m # AXI Master clock
> + - const: axi_s # AXI Slave clock
> + - const: axi_bridge # AXI bridge clock
> + - const: rchng
> + resets:
> + minItems: 8
> + maxItems: 8
> + reset-names:
> + items:
> + - const: pipe # PIPE reset
> + - const: sticky # Core sticky reset
> + - const: axi_m_sticky # AXI master sticky reset
> + - const: axi_m # AXI master reset
> + - const: axi_s_sticky # AXI slave sticky reset
> + - const: axi_s # AXI slave reset
> + - const: ahb # AHB reset
> + - const: aux # AUX reset
> +
> - if:
> properties:
> compatible:
> @@ -790,6 +825,7 @@ allOf:
> enum:
> - qcom,pcie-apq8064
> - qcom,pcie-ipq4019
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064v2
> - qcom,pcie-ipq8074
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <[email protected]> wrote:
>
> The Qualcomm IPQ5332 PCIe controller instances are based on
> SNPS core 5.90a with Gen3 Single-lane and Dual-lane support.
> The Qualcomm IP rev is 1.27.0 and hence using the 1_27_0 ops.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> This patch depends on the below series which adds PCIe support in
> Qualcomm IPQ9574
> https://lore.kernel.org/all/[email protected]/
The series did not receive updates since the end of May. Should we
expect the next iteration of that series? Otherwise depending on it
sounds like a dead end.
>
> drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 109df587234e..3d54de1a71df 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
> { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
> { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
> + { .compatible = "qcom,pcie-ipq5332", .data = &cfg_1_27_0 },
> { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
> { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <[email protected]> wrote:
>
> Add separate entry in clock-controller for USB pipe clock.
In my opinion, there is no need to do that separately. Please squash
into patch 9.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index 42e2e48b2bc3..f0d92effb783 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -213,6 +213,7 @@ gcc: clock-controller@1800000 {
> <&sleep_clk>,
> <0>,
> <0>,
> + <0>,
> <0>;
> };
>
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On 12/14/2023 12:39 PM, Dmitry Baryshkov wrote:
> On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <[email protected]> wrote:
>> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
>> interface (PCIe/USB) can use this combo PHY and the PHY drivers are
>> different for PCIe and USB. Hence separate the PCIe and USB pipe clock
>> source from DT, and individual driver node can be used as a clock source
>> separately in the gcc. Add separate enum for PCIe and USB pipe clock and
>> change the parent in corresponding structures.
>>
>> Signed-off-by: Praveenkumar I <[email protected]>
> Please use your full name for the git authorship and or the S-o-B
> tags. This applies to the whole series.
My full name is "Praveenkumar I". In my region, we used to have only the
initial letter of surname.
--
Thanks,
Praveenkumar
> Other than that:
>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
>
>> ---
>> drivers/clk/qcom/gcc-ipq5332.c | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
>> index f98591148a97..aa0f616c3b1b 100644
>> --- a/drivers/clk/qcom/gcc-ipq5332.c
>> +++ b/drivers/clk/qcom/gcc-ipq5332.c
>> @@ -25,7 +25,8 @@ enum {
>> DT_SLEEP_CLK,
>> DT_PCIE_2LANE_PHY_PIPE_CLK,
>> DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
>> - DT_USB_PCIE_WRAPPER_PIPE_CLK,
>> + DT_PCIE_WRAPPER_PIPE_CLK,
>> + DT_USB_WRAPPER_PIPE_CLK,
>> };
>>
>> enum {
>> @@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
>> .hw.init = &(struct clk_init_data) {
>> .name = "gcc_pcie3x1_0_pipe_clk_src",
>> .parent_data = &(const struct clk_parent_data) {
>> - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
>> + .index = DT_PCIE_WRAPPER_PIPE_CLK,
>> },
>> .num_parents = 1,
>> .ops = &clk_regmap_phy_mux_ops,
>> @@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
>> .hw.init = &(struct clk_init_data) {
>> .name = "gcc_usb0_pipe_clk_src",
>> .parent_data = &(const struct clk_parent_data) {
>> - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
>> + .index = DT_USB_WRAPPER_PIPE_CLK,
>> },
>> .num_parents = 1,
>> .ops = &clk_regmap_phy_mux_ops,
>> --
>> 2.34.1
>>
>>
>
On 12/14/2023 12:42 PM, Dmitry Baryshkov wrote:
> On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <[email protected]> wrote:
>> Add support for single-lane and dual-lane PCIe UNIPHY found on
>> Qualcomm IPQ5332 platform. This UNIPHY is similar to the one
>> present in Qualcomm IPQ5018.
>>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> ---
>> This patch depends on the below series which adds PCIe support in
>> Qualcomm IPQ5018
>> https://lore.kernel.org/all/[email protected]/
>>
>> .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
>> index 9f9a03faf6fa..aa71b85eb50e 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
>> @@ -34,6 +34,10 @@
>> #define SSCG_CTRL_REG_6 0xb0
>> #define PCS_INTERNAL_CONTROL_2 0x2d8
>>
>> +#define PHY_CFG_PLLCFG 0x220
>> +#define PHY_CFG_EIOS_DTCT_REG 0x3e4
>> +#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
>> +
>> #define PHY_MODE_FIXED 0x1
>>
>> enum qcom_uniphy_pcie_type {
>> @@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = {
>> },
>> };
>>
>> +static const struct uniphy_regs ipq5332_regs[] = {
>> + {
>> + .offset = PHY_CFG_PLLCFG,
>> + .val = 0x30,
>> + },
>> + {
>> + .offset = PHY_CFG_EIOS_DTCT_REG,
>> + .val = 0x53ef,
>> + },
>> + {
>> + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
>> + .val = 0xCf,
>> + },
>> +};
>> +
>> static const struct uniphy_pcie_data ipq5018_2x2_data = {
>> .lanes = 2,
>> .lane_offset = 0x800,
>> @@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = {
>> .pipe_clk_rate = 125000000,
>> };
>>
>> +static const struct uniphy_pcie_data ipq5332_x2_data = {
>> + .lanes = 2,
>> + .lane_offset = 0x800,
>> + .phy_type = PHY_TYPE_PCIE_GEN3,
>> + .init_seq = ipq5332_regs,
>> + .init_seq_num = ARRAY_SIZE(ipq5332_regs),
>> + .pipe_clk_rate = 250000000,
>> +};
>> +
>> +static const struct uniphy_pcie_data ipq5332_x1_data = {
>> + .lanes = 1,
>> + .phy_type = PHY_TYPE_PCIE_GEN3,
>> + .init_seq = ipq5332_regs,
>> + .init_seq_num = ARRAY_SIZE(ipq5332_regs),
>> + .pipe_clk_rate = 250000000,
>> +};
> Please keep structs sorted out.
sure, will address in next patch set.
>
>> +
>> static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
>> {
>> const struct uniphy_pcie_data *data = phy->data;
>> @@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
>> .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2",
>> .data = &ipq5018_2x2_data,
>> },
>> + {
>> + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2",
>> + .data = &ipq5332_x2_data,
>> + },
>> + {
>> + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1",
>> + .data = &ipq5332_x1_data,
> The entries here should be sorted out.
will take care.
>
>> + },
>> { /* Sentinel */ },
>> };
>> MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
>> --
>> 2.34.1
>>
>>
>
--
Thanks,
Praveenkumar
On 12/14/2023 12:45 PM, Dmitry Baryshkov wrote:
> On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <[email protected]> wrote:
>> Add support for the PCIe controller on the Qualcomm
>> IPQ5332 SoC to the bindings.
>>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index eadba38171e1..af5e67d2a984 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -21,6 +21,7 @@ properties:
>> - qcom,pcie-apq8064
>> - qcom,pcie-apq8084
>> - qcom,pcie-ipq4019
>> + - qcom,pcie-ipq5332
>> - qcom,pcie-ipq6018
>> - qcom,pcie-ipq8064
>> - qcom,pcie-ipq8064-v2
>> @@ -170,6 +171,7 @@ allOf:
>> compatible:
>> contains:
>> enum:
>> + - qcom,pcie-ipq5332
>> - qcom,pcie-ipq6018
>> - qcom,pcie-ipq8074-gen3
>> then:
>> @@ -332,6 +334,39 @@ allOf:
>> - const: ahb # AHB reset
>> - const: phy_ahb # PHY AHB reset
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq5332
> As you seem to be depending on the ipq9574, could you please reuse the
> DT entry too?
Sure, will reuse ipq9574 entry.
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 6
>> + maxItems: 6
>> + clock-names:
>> + items:
>> + - const: ahb # AHB clock
>> + - const: aux # Auxiliary clock
>> + - const: axi_m # AXI Master clock
>> + - const: axi_s # AXI Slave clock
>> + - const: axi_bridge # AXI bridge clock
>> + - const: rchng
>> + resets:
>> + minItems: 8
>> + maxItems: 8
>> + reset-names:
>> + items:
>> + - const: pipe # PIPE reset
>> + - const: sticky # Core sticky reset
>> + - const: axi_m_sticky # AXI master sticky reset
>> + - const: axi_m # AXI master reset
>> + - const: axi_s_sticky # AXI slave sticky reset
>> + - const: axi_s # AXI slave reset
>> + - const: ahb # AHB reset
>> + - const: aux # AUX reset
>> +
>> - if:
>> properties:
>> compatible:
>> @@ -790,6 +825,7 @@ allOf:
>> enum:
>> - qcom,pcie-apq8064
>> - qcom,pcie-ipq4019
>> + - qcom,pcie-ipq5332
>> - qcom,pcie-ipq8064
>> - qcom,pcie-ipq8064v2
>> - qcom,pcie-ipq8074
>> --
>> 2.34.1
>>
>>
>
--
Thanks,
Praveenkumar
On 12/14/2023 12:51 PM, Dmitry Baryshkov wrote:
> On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <[email protected]> wrote:
>> Add separate entry in clock-controller for USB pipe clock.
> In my opinion, there is no need to do that separately. Please squash
> into patch 9.
Sure will squash this change with patch 9.
>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> index 42e2e48b2bc3..f0d92effb783 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -213,6 +213,7 @@ gcc: clock-controller@1800000 {
>> <&sleep_clk>,
>> <0>,
>> <0>,
>> + <0>,
>> <0>;
>> };
>>
>> --
>> 2.34.1
>>
>>
>
--
Thanks,
Praveenkumar
On 14/12/2023 07:28, Praveenkumar I wrote:
> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
> interface (PCIe/USB) can use this combo PHY and the PHY drivers are
> different for PCIe and USB. Hence separate the PCIe and USB pipe clock
> source from DT, and individual driver node can be used as a clock source
> separately in the gcc. Change the dt-bindings accordingly.
Adding required clock breaks the ABI and there is no explanation nor
note about it in commit msg
Best regards,
Krzysztof
On 14/12/2023 07:28, Praveenkumar I wrote:
> Qualcomm IPQ5332 has single-lane and dual-lane PCIe UNIPHY
> with Gen 3 support. This UNIPHY is similar to the one found
> on Qualcomm IPQ5018. Hence add the bindings in qcom,uniphy-pcie.
>
> Clocks and resets are different for IPQ5332. Update the
> bindings to support both IPQ5018 and IPQ5332.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> This patch depends on the below series which adds PCIe support in
> Qualcomm IPQ5018
> https://lore.kernel.org/all/[email protected]/
>
> .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++++++++++++++--
> 1 file changed, 58 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
> index 6b2574f9532e..205eaec2291e 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
> @@ -20,19 +20,20 @@ properties:
> maxItems: 1
>
> clocks:
> - maxItems: 1
> + minItems: 1
> + maxItems: 4
>
> clock-names:
> - items:
> - - const: pipe_clk
> + minItems: 1
> + maxItems: 4
>
> resets:
> - maxItems: 2
> + minItems: 2
> + maxItems: 3
>
> reset-names:
> - items:
> - - const: phy
> - - const: phy_phy
> + minItems: 2
> + maxItems: 3
>
> "#phy-cells":
> const: 0
> @@ -54,6 +55,56 @@ required:
> - "#clock-cells"
> - clock-output-names
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq5018-uniphy-pcie-gen2x1
> + - qcom,ipq5018-uniphy-pcie-gen2x2
> + then:
> + properties:
> + clocks:
> + minItems: 1
Drop
> + maxItems: 1
> + clock-names:
> + items:
> + - const: pipe_clk
> + resets:
> + minItems: 2
Drop
> + maxItems: 2
> + reset-name:
Typo
> + items:
> + - const: phy
> + - const: phy_phy
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq5332-uniphy-pcie-gen3x1
> + - qcom,ipq5332-uniphy-pcie-gen3x2
There are no such compatibles.
> + then:
> + properties:
> + clocks:
> + minItems: 4
> + maxItems: 4
> + clock-names:
> + items:
> + - const: pipe
> + - const: lane_m
> + - const: lane_s
> + - const: phy_ahb
> + resets:
> + minItems: 2
> + maxItems: 2
So where are three items?
> + reset-name:
Typo
This patch is so confusing, it looks like it does not make any sense.
Best regards,
Krzysztof
On 14/12/2023 07:28, Praveenkumar I wrote:
> Add support for the PCIe controller on the Qualcomm
> IPQ5332 SoC to the bindings.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index eadba38171e1..af5e67d2a984 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -21,6 +21,7 @@ properties:
> - qcom,pcie-apq8064
> - qcom,pcie-apq8084
> - qcom,pcie-ipq4019
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064-v2
> @@ -170,6 +171,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8074-gen3
> then:
> @@ -332,6 +334,39 @@ allOf:
> - const: ahb # AHB reset
> - const: phy_ahb # PHY AHB reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq5332
> + then:
> + properties:
> + clocks:
> + minItems: 6
> + maxItems: 6
> + clock-names:
> + items:
> + - const: ahb # AHB clock
> + - const: aux # Auxiliary clock
> + - const: axi_m # AXI Master clock
> + - const: axi_s # AXI Slave clock
> + - const: axi_bridge # AXI bridge clock
> + - const: rchng
> + resets:
> + minItems: 8
> + maxItems: 8
> + reset-names:
> + items:
> + - const: pipe # PIPE reset
No sleep reset? Otherwise it looks like some existing entry, so you
should use the same order of resets.
Best regards,
Krzysztof
On 14/12/2023 07:28, Praveenkumar I wrote:
> Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 189 +++++++++++++++++++++++++-
> 1 file changed, 187 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index f0d92effb783..367641ab4938 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -166,6 +166,58 @@ usbphy0: phy@7b000 {
> status = "disabled";
> };
>
> + pcie0_phy: phy@4b0000{
Nodes look like put in random place.
Best regards,
Krzysztof
On Fri, 15 Dec 2023 at 07:44, Praveenkumar I <[email protected]> wrote:
>
>
>
> On 12/14/2023 12:39 PM, Dmitry Baryshkov wrote:
> > On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <[email protected]> wrote:
> >> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
> >> interface (PCIe/USB) can use this combo PHY and the PHY drivers are
> >> different for PCIe and USB. Hence separate the PCIe and USB pipe clock
> >> source from DT, and individual driver node can be used as a clock source
> >> separately in the gcc. Add separate enum for PCIe and USB pipe clock and
> >> change the parent in corresponding structures.
> >>
> >> Signed-off-by: Praveenkumar I <[email protected]>
> > Please use your full name for the git authorship and or the S-o-B
> > tags. This applies to the whole series.
> My full name is "Praveenkumar I". In my region, we used to have only the
> initial letter of surname.
Oh, excuse me please then. I saw several of your colleagues using a
single letter instead of their surname and I supposed that it's a case
for you too.
--
With best wishes
Dmitry
On Thu, Dec 14, 2023 at 11:58:37AM +0530, Praveenkumar I wrote:
> Patch series adds support for enabling the PCIe controller and
> UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
> PCIe1 is Gen3 X2 are added.
>
> UNIPHY changes depends on
> https://lore.kernel.org/all/[email protected]/
> PCIe driver change depends on
> https://lore.kernel.org/all/[email protected]/
>
Any plan on this series and the dependencies?
- Mani
> Praveenkumar I (10):
> dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY
> clk: qcom: ipq5332: Add separate clocks for PCIe and USB for Combo PHY
> arm64: dts: qcom: ipq5332: Add separate entry for USB pipe clock
> phy: qcom: Add support for Pipe clock rate from device data
> dt-bindings: phy: qcom,uniphy-pcie: Add ipq5332 bindings
> phy: qcom: ipq5332: Add support for g3x1 and g3x2 PCIe PHYs
> dt-bindings: PCI: qcom: Add IPQ5332 SoC
> pci: qcom: Add support for IPQ5332
> arm64: dts: qcom: ipq5332: Add PCIe related nodes
> arm64: dts: qcom: ipq5332: Enable PCIe phys and controllers
>
> .../bindings/clock/qcom,ipq5332-gcc.yaml | 6 +-
> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 ++++
> .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++-
> arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++
> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 188 +++++++++++++++++-
> drivers/clk/qcom/gcc-ipq5332.c | 7 +-
> drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 49 ++++-
> 8 files changed, 412 insertions(+), 14 deletions(-)
>
> --
> 2.34.1
>
>
--
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