Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
sound card and PMIC functions.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. The module is mounted onto Qualcomm AIoT
carrier board to support verification, evaluation and development. It
integrates QCS8550 SoC, UFS and PMIC chip etc.
Signed-off-by: Tengfei Fan <[email protected]>
---
v3 -> v4:
- use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version
of qcm8550, another board with qcm8550 will be added later
- add AIM300 AIoT board string in qcom.yaml file
- add sm8550 and qcm8550 fallback compatible
- add qcm8550 SoC id
- add reserved memory map codes in qcm8550.dtsi
- pm8010 and pmr73d are splited into carrier board DTS file. Because
the regulators which in pm8550, pm8550ve and pm8550vs are present
on the SoM. The regulators which in pm8010 and pmr73d are present
on the carrier board.
- stay VPH_PWR at qcs8550-aim300.dtsi file
+----------------------------------------+
|AIM300 SoM |
| |
| +-----+ |
| |--->| UFS | |
| | +-----+ |
| | |
| | |
3.7v | +-----------------+ | +---------+ |
---------->| PMIC |----->| QCS8550 | |
| +-----------------+ +---------+ |
| | |
| | |
| | +-----+ |
| |--->| ... | |
| +-----+ |
| |
+----------------------------------------+
VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage
with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300
SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file.
v2 -> v3:
- introduce qcs8550.dtsi
- separate fix dtc W=1 warning patch to another patch series
v1 -> v2:
- merge the splited dts patches into one patch
- update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts
- drop PCIe1 dts node due to it is not enabled
- update display node name for drop sde characters
previous discussion here:
[1] v3: https://lore.kernel.org/linux-arm-msm/[email protected]
[2] v2: https://lore.kernel.org/linux-arm-msm/[email protected]
[3] v1: https://lore.kernel.org/linux-arm-msm/[email protected]
Tengfei Fan (6):
dt-bindings: arm: qcom: Document QCM8550, QCS8550 SoC and board
dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550
soc: qcom: socinfo: add SoC Info support for QCM8550 and QCS8550
platform
arm64: dts: qcom: qcm8550: introduce qcm8550 dtsi
arm64: dts: qcom: add base AIM300 dtsi
arm64: dts: qcom: aim300: add AIM300 AIoT
.../devicetree/bindings/arm/qcom.yaml | 11 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcm8550.dtsi | 170 +++++
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 600 ++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 368 +++++++++++
drivers/soc/qcom/socinfo.c | 2 +
include/dt-bindings/arm/qcom,ids.h | 2 +
7 files changed, 1154 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcm8550.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
base-commit: ad5c60d66016e544c51ed98635a74073f761f45d
--
2.17.1
Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
QCS8550 and QCM8550 processor combines powerful computing, extreme edge
AI processing, Wi-Fi 7, and robust video and graphics for a wide range
of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. The module is mounted onto Qualcomm AIoT
carrier board to support verification, evaluation and development. It
integrates QCS8550 SoC, UFS and PMIC chip etc.
AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 1a5fb889a444..9cee874a8eae 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -49,8 +49,10 @@ description: |
msm8996
msm8998
qcs404
+ qcs8550
qcm2290
qcm6490
+ qcm8550
qdu1000
qrb2210
qrb4210
@@ -93,6 +95,7 @@ description: |
The 'board' element must be one of the following strings:
adp
+ aim300-aiot
cdp
dragonboard
idp
@@ -904,6 +907,14 @@ properties:
- const: qcom,qcs404-evb
- const: qcom,qcs404
+ - items:
+ - enum:
+ - qcom,qcs8550-aim300-aiot
+ - const: qcom,qcs8550-aim300
+ - const: qcom,qcs8550
+ - const: qcom,qcm8550
+ - const: qcom,sm8550
+
- items:
- enum:
- qcom,sa8155p-adp
--
2.17.1
Add the ID for the Qualcomm QCM8550 and QCS8550 SoC, QCS8550 is a QCS
version of QCM8550.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
include/dt-bindings/arm/qcom,ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 51e0f6059410..dc7ba87b50d7 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -265,6 +265,8 @@
#define QCOM_ID_IPQ5322 593
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
+#define QCOM_ID_QCS8550 603
+#define QCOM_ID_QCM8550 604
#define QCOM_ID_IPQ5300 624
/*
--
2.17.1
Add SoC Info support for QCM8550 and QCS8550 platform.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
drivers/soc/qcom/socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 6349a0debeb5..321b39b48b80 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -437,6 +437,8 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(IPQ5322) },
{ qcom_board_id(IPQ5312) },
{ qcom_board_id(IPQ5302) },
+ { qcom_board_id(QCS8550) },
+ { qcom_board_id(QCM8550) },
{ qcom_board_id(IPQ5300) },
};
--
2.17.1
QCM8550 is derived from SM8550, it is mainly used in IoT scenarions.
QCM8550 and QCS8550 have same memory map and it's different to SM8550.
There are 3 types of reserved memory regions here:
1. Firmware related regions.
This will be described as: reserved-region@address. Current
reserved-region may have reserved area which was not yet used, release
note of the firmware can have such kind of information.
2. Firmware related which shared with kernel access.
Each region will have a specific node with specific label name for
later phandle reference from other driver dt node. May overlapping with
above type regions.
3. PIL regions.
PIL regions are allocated by kernel and assigned to subsystem
firmware later.
Here is a map for this platform:
0x100000000 +------------------+
| |
| Firmware Related |
| |
0xd4d00000 +------------------+
| |
| Kernel Available |
| |
0xA7000000 +------------------+
| |
| PIL Region |
| |
0x8A800000 +------------------+
| |
| Firmware Related |
| |
0x80000000 +------------------+
Note that:
1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not suggest
for other usage.
2. Kernel start address was start at 0xA8000000.
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/qcm8550.dtsi | 170 ++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcm8550.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcm8550.dtsi b/arch/arm64/boot/dts/qcom/qcm8550.dtsi
new file mode 100644
index 000000000000..62d9c0df0523
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcm8550.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023~2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sm8550.dtsi"
+
+/delete-node/ &reserved_memory;
+
+/ {
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * There are 3 types of reserved memory regions here:
+ * 1. Firmware related regions.
+ * This will be described as: reserved-region@address. Current
+ * reserved-region may have reserved area which was not yet used,
+ * release note of the firmware can have such kind of information.
+ * 2. Firmware related which shared with kernel access.
+ * Each region will have a specific node with specific label
+ * name for later phandle reference from other driver dt node. May
+ * overlapping with above type regions.
+ * 3. PIL regions.
+ * PIL regions are allocated by kernel and assigned to subsystem
+ * firmware later.
+ * Here is a map for this platform:
+ * 0x100000000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0xd4d00000 +------------------+
+ * | |
+ * | Kernel Available |
+ * | |
+ * 0xA7000000 +------------------+
+ * | |
+ * | PIL Region |
+ * | |
+ * 0x8A800000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0x80000000 +------------------+
+ * Note that:
+ * 1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not
+ * suggest for other usage.
+ * 2. Kernel start address was start at 0xA8000000.
+ */
+
+ /* Firmware related regions */
+ reserved-region@80000000 {
+ reg = <0x0 0x80000000 0x0 0xa800000>;
+ no-map;
+ };
+
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ no-map;
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ /* PIL region */
+ mpss_mem: mpss-region@8a800000 {
+ reg = <0x0 0x8a800000 0x0 0x10800000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9b080000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9b090000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@9b100000 {
+ reg = <0x0 0x9b100000 0x0 0x180000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
+ reg = <0x0 0x9b280000 0x0 0x80000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9b300000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@9c200000 {
+ reg = <0x0 0x9c200000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9c900000 {
+ reg = <0x0 0x9c900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
+ reg = <0x0 0x9e900000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
+ reg = <0x0 0x9e980000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x4080000>;
+ no-map;
+ };
+
+ /* Firmware related regions */
+ mpss_dsm_mem: mpss_dsm_region@d4d00000 {
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+
+ reserved-region@d8000000 {
+ reg = <0x0 0xd8000000 0x0 0x28000000>;
+ no-map;
+ };
+
+ };
+};
--
2.17.1
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. The module is mounted onto Qualcomm AIoT
carrier board to support verification, evaluation and development. It
integrates QCS8550 SoC, UFS and PMIC chip etc.
Here is a diagram of AIM300 SoM
+----------------------------------------+
|AIM300 SoM |
| |
| +-----+ |
| |--->| UFS | |
| | +-----+ |
| | |
| | |
3.7v | +-----------------+ | +---------+ |
---------->| PMIC |----->| QCS8550 | |
| +-----------------+ +---------+ |
| | |
| | |
| | +-----+ |
| |--->| ... | |
| +-----+ |
| |
+----------------------------------------+
Co-developed-by: Fenglin Wu <[email protected]>
Signed-off-by: Fenglin Wu <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 368 +++++++++++++++++++
1 file changed, 368 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
new file mode 100644
index 000000000000..8132aa52f97e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023~2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcm8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/ {
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1408000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1272000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p2: ldo2 {
+ regulator-name = "vreg_l2g_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
--
2.17.1
Add AIM300 AIoT board DTS support, including usb, serial, PCIe, mpss,
adsp, cdsp and sound card functions support.
Co-developed-by: Qiang Yu <[email protected]>
Signed-off-by: Qiang Yu <[email protected]>
Co-developed-by: Ziyue Zhang <[email protected]>
Signed-off-by: Ziyue Zhang <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 600 ++++++++++++++++++
2 files changed, 601 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 39889d5f8e12..6fdde64d7540 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -92,6 +92,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
new file mode 100644
index 000000000000..20a3c971cbb9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "qcs8550-aim300.dtsi"
+#include "pm8010.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
+ compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
+ "qcom,qcm8550", "qcom,sm8550";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcd_default>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
+ 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+
+ #sound-dai-cells = <1>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ model = "AIM300-AIOT";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS1",
+ "VA DMIC1", "MIC BIAS1",
+ "VA DMIC2", "MIC BIAS3",
+ "TX DMIC0", "MIC BIAS1",
+ "TX DMIC1", "MIC BIAS2",
+ "TX DMIC2", "MIC BIAS3",
+ "TX SWR_ADC1", "ADC2_OUTPUT";
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&north_spkr>, <&south_spkr>,
+ <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ typec-retimer@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ orientation-switch;
+ retimer-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_ss_in: endpoint {
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&gcc {
+ clocks = <&bi_tcxo_div2>, <&sleep_clk>,
+ <0>,
+ <&pcie1_phy>,
+ <0>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+};
+
+&lpass_tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ pinctrl-0 = <&dsi_active>, <&te_active>;
+ pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pm8550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/adsp.mbn",
+ "qcom/sm8550/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/cdsp.mbn",
+ "qcom/sm8550/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8550/modem.mbn",
+ "qcom/sm8550/modem_dtb.mbn";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker North */
+ north_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3g_1p2>;
+ };
+
+ /* WSA8845, Speaker South */
+ south_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3g_1p2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9385 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9385 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <1 1 2 3>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ dsi_active: dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_suspend: dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_active: te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_suspend: te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio108";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ phys = <&pm8550b_eusb2_repeater>;
+
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.17.1
On Fri, 19 Jan 2024 18:06:15 +0800, Tengfei Fan wrote:
> Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
> sound card and PMIC functions.
> AIM300 Series is a highly optimized family of modules designed to
> support AIoT applications. The module is mounted onto Qualcomm AIoT
> carrier board to support verification, evaluation and development. It
> integrates QCS8550 SoC, UFS and PMIC chip etc.
>
> [...]
Applied, thanks!
[2/6] dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550
commit: 3019d8f7eacdd2d14502f0fa5c3e4267da8409a3
[3/6] soc: qcom: socinfo: add SoC Info support for QCM8550 and QCS8550 platform
commit: d7f3a3691e3c133c637fa381cdc91e7d1af9c5d7
Best regards,
--
Bjorn Andersson <[email protected]>
On 19/01/2024 11:06, Tengfei Fan wrote:
> Add AIM300 AIoT board DTS support, including usb, serial, PCIe, mpss,
> adsp, cdsp and sound card functions support.
>
..
> +
> + sound {
> + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
> + model = "AIM300-AIOT";
> + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
> + "SpkrRight IN", "WSA_SPK2 OUT",
> + "IN1_HPHL", "HPHL_OUT",
> + "IN2_HPHR", "HPHR_OUT",
> + "AMIC2", "MIC BIAS2",
> + "VA DMIC0", "MIC BIAS1",
> + "VA DMIC1", "MIC BIAS1",
> + "VA DMIC2", "MIC BIAS3",
> + "TX DMIC0", "MIC BIAS1",
> + "TX DMIC1", "MIC BIAS2",
> + "TX DMIC2", "MIC BIAS3",
> + "TX SWR_ADC1", "ADC2_OUTPUT";
This should be probably TX SWR_INPUT1.
Best regards,
Krzysztof
On 1/29/2024 4:09 PM, Krzysztof Kozlowski wrote:
> On 19/01/2024 11:06, Tengfei Fan wrote:
>> Add AIM300 AIoT board DTS support, including usb, serial, PCIe, mpss,
>> adsp, cdsp and sound card functions support.
>>
>
> ...
>
>> +
>> + sound {
>> + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
>> + model = "AIM300-AIOT";
>> + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
>> + "SpkrRight IN", "WSA_SPK2 OUT",
>> + "IN1_HPHL", "HPHL_OUT",
>> + "IN2_HPHR", "HPHR_OUT",
>> + "AMIC2", "MIC BIAS2",
>> + "VA DMIC0", "MIC BIAS1",
>> + "VA DMIC1", "MIC BIAS1",
>> + "VA DMIC2", "MIC BIAS3",
>> + "TX DMIC0", "MIC BIAS1",
>> + "TX DMIC1", "MIC BIAS2",
>> + "TX DMIC2", "MIC BIAS3",
>> + "TX SWR_ADC1", "ADC2_OUTPUT";
>
> This should be probably TX SWR_INPUT1.
>
> Best regards,
> Krzysztof
>
I will double check this with related team and I will update this.
--
Thx and BRs,
Tengfei Fan
On 1/29/2024 4:18 PM, Tengfei Fan wrote:
>
>
> On 1/29/2024 4:09 PM, Krzysztof Kozlowski wrote:
>> On 19/01/2024 11:06, Tengfei Fan wrote:
>>> Add AIM300 AIoT board DTS support, including usb, serial, PCIe, mpss,
>>> adsp, cdsp and sound card functions support.
>>>
>>
>> ...
>>
>>> +
>>> +Â Â Â sound {
>>> +Â Â Â Â Â Â Â compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
>>> +Â Â Â Â Â Â Â model = "AIM300-AIOT";
>>> +Â Â Â Â Â Â Â audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "SpkrRight IN", "WSA_SPK2 OUT",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "IN1_HPHL", "HPHL_OUT",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "IN2_HPHR", "HPHR_OUT",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "AMIC2", "MIC BIAS2",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VA DMIC0", "MIC BIAS1",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VA DMIC1", "MIC BIAS1",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VA DMIC2", "MIC BIAS3",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX DMIC0", "MIC BIAS1",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX DMIC1", "MIC BIAS2",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX DMIC2", "MIC BIAS3",
>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX SWR_ADC1", "ADC2_OUTPUT";
>>
>> This should be probably TX SWR_INPUT1.
>>
>> Best regards,
>> Krzysztof
>>
>
> I will double check this with related team and I will update this.
>
I will apply "TX SWR_INPUT1" on audio-routing node in the next patch
series.
--
Thx and BRs,
Tengfei Fan
On 1/30/2024 3:25 PM, Tengfei Fan wrote:
>
>
> On 1/29/2024 4:18 PM, Tengfei Fan wrote:
>>
>>
>> On 1/29/2024 4:09 PM, Krzysztof Kozlowski wrote:
>>> On 19/01/2024 11:06, Tengfei Fan wrote:
>>>> Add AIM300 AIoT board DTS support, including usb, serial, PCIe, mpss,
>>>> adsp, cdsp and sound card functions support.
>>>>
>>>
>>> ...
>>>
>>>> +
>>>> +Â Â Â sound {
>>>> +Â Â Â Â Â Â Â compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
>>>> +Â Â Â Â Â Â Â model = "AIM300-AIOT";
>>>> +Â Â Â Â Â Â Â audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "SpkrRight IN", "WSA_SPK2 OUT",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "IN1_HPHL", "HPHL_OUT",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "IN2_HPHR", "HPHR_OUT",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "AMIC2", "MIC BIAS2",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VA DMIC0", "MIC BIAS1",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VA DMIC1", "MIC BIAS1",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "VA DMIC2", "MIC BIAS3",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX DMIC0", "MIC BIAS1",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX DMIC1", "MIC BIAS2",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX DMIC2", "MIC BIAS3",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "TX SWR_ADC1", "ADC2_OUTPUT";
>>>
>>> This should be probably TX SWR_INPUT1.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> I will double check this with related team and I will update this.
>>
>
> I will apply "TX SWR_INPUT1" on audio-routing node in the next patch
> series.
>
This patch series has been sent for nearly two weeks. do you think it is
better to modify the patch series acording to the current comments and
submit a new patch series, or continue to wait for your review comments
on the current path series?
--
Thx and BRs,
Tengfei Fan
On 01/02/2024 12:49, Tengfei Fan wrote:
>>>> This should be probably TX SWR_INPUT1.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> I will double check this with related team and I will update this.
>>>
>>
>> I will apply "TX SWR_INPUT1" on audio-routing node in the next patch
>> series.
>>
>
> This patch series has been sent for nearly two weeks. do you think it is
> better to modify the patch series acording to the current comments and
> submit a new patch series, or continue to wait for your review comments
> on the current path series?
Hi,
Whom do you ask?
Best regards,
Krzysztof
On 2/1/2024 8:03 PM, Krzysztof Kozlowski wrote:
> On 01/02/2024 12:49, Tengfei Fan wrote:
>>>>> This should be probably TX SWR_INPUT1.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> I will double check this with related team and I will update this.
>>>>
>>>
>>> I will apply "TX SWR_INPUT1" on audio-routing node in the next patch
>>> series.
>>>
>>
>> This patch series has been sent for nearly two weeks. do you think it is
>> better to modify the patch series acording to the current comments and
>> submit a new patch series, or continue to wait for your review comments
>> on the current path series?
>
> Hi,
>
> Whom do you ask?
>
> Best regards,
> Krzysztof
>
Sorry Krzysztof, can you give sone guidance on whether I should update
patch and submit a new patch series, or do you need time to review
current patch series?
--
Thx and BRs,
Tengfei Fan
On 01/02/2024 13:16, Tengfei Fan wrote:
>
>
> On 2/1/2024 8:03 PM, Krzysztof Kozlowski wrote:
>> On 01/02/2024 12:49, Tengfei Fan wrote:
>>>>>> This should be probably TX SWR_INPUT1.
>>>>>>
>>>>>> Best regards,
>>>>>> Krzysztof
>>>>>>
>>>>>
>>>>> I will double check this with related team and I will update this.
>>>>>
>>>>
>>>> I will apply "TX SWR_INPUT1" on audio-routing node in the next patch
>>>> series.
>>>>
>>>
>>> This patch series has been sent for nearly two weeks. do you think it is
>>> better to modify the patch series acording to the current comments and
>>> submit a new patch series, or continue to wait for your review comments
>>> on the current path series?
>>
>> Hi,
>>
>> Whom do you ask?
>>
>> Best regards,
>> Krzysztof
>>
>
> Sorry Krzysztof, can you give sone guidance on whether I should update
> patch and submit a new patch series, or do you need time to review
> current patch series?
Up to you, I do not plan to provide more reviews on this. I just
commented about this thing here, because I was doing similar work for QRD.
Best regards,
Krzysztof
On 2/1/2024 8:20 PM, Krzysztof Kozlowski wrote:
> On 01/02/2024 13:16, Tengfei Fan wrote:
>>
>>
>> On 2/1/2024 8:03 PM, Krzysztof Kozlowski wrote:
>>> On 01/02/2024 12:49, Tengfei Fan wrote:
>>>>>>> This should be probably TX SWR_INPUT1.
>>>>>>>
>>>>>>> Best regards,
>>>>>>> Krzysztof
>>>>>>>
>>>>>>
>>>>>> I will double check this with related team and I will update this.
>>>>>>
>>>>>
>>>>> I will apply "TX SWR_INPUT1" on audio-routing node in the next patch
>>>>> series.
>>>>>
>>>>
>>>> This patch series has been sent for nearly two weeks. do you think it is
>>>> better to modify the patch series acording to the current comments and
>>>> submit a new patch series, or continue to wait for your review comments
>>>> on the current path series?
>>>
>>> Hi,
>>>
>>> Whom do you ask?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Sorry Krzysztof, can you give sone guidance on whether I should update
>> patch and submit a new patch series, or do you need time to review
>> current patch series?
>
> Up to you, I do not plan to provide more reviews on this. I just
> commented about this thing here, because I was doing similar work for QRD.
>
> Best regards,
> Krzysztof
>
Thank youfor clarification.
Next I will update patches according to the current comments and submit
a new path series.
--
Thx and BRs,
Tengfei Fan
On 19/01/2024 11:06, Tengfei Fan wrote:
> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
> AIM300 Series is a highly optimized family of modules designed to
> support AIoT applications. The module is mounted onto Qualcomm AIoT
> carrier board to support verification, evaluation and development. It
> integrates QCS8550 SoC, UFS and PMIC chip etc.
> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
I want to unreview it.
Please fix your commit msg to drop marketing and instead describe the
SoC. I don't see for example any explanation why there is qcm8550 and
sm8550. Aren't they the same?
Best regards,
Krzysztof
On 2/2/2024 10:34 PM, Krzysztof Kozlowski wrote:
> On 19/01/2024 11:06, Tengfei Fan wrote:
>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>> AIM300 Series is a highly optimized family of modules designed to
>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>> carrier board to support verification, evaluation and development. It
>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>
> I want to unreview it.
>
> Please fix your commit msg to drop marketing and instead describe the
> SoC. I don't see for example any explanation why there is qcm8550 and
> sm8550. Aren't they the same?
>
>
>
> Best regards,
> Krzysztof
>
qcm8550 and sm8550 are different, they have different firmware release,
qcm8550 related board dts will be pushed to upstream once it is ready later.
I will update commit message to introduce the different between qcm8550
and sm8550.
qcm8550 introduce link:
https://www.qualcomm.com/products/technology/processors/qcm8550
--
Thx and BRs,
Tengfei Fan
On Fri, 2 Feb 2024 at 15:34, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 19/01/2024 11:06, Tengfei Fan wrote:
> > Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
> > QCS8550 and QCM8550 processor combines powerful computing, extreme edge
> > AI processing, Wi-Fi 7, and robust video and graphics for a wide range
> > of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
> > for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
> > AIM300 Series is a highly optimized family of modules designed to
> > support AIoT applications. The module is mounted onto Qualcomm AIoT
> > carrier board to support verification, evaluation and development. It
> > integrates QCS8550 SoC, UFS and PMIC chip etc.
> > AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
> >
> > Reviewed-by: Krzysztof Kozlowski <[email protected]>
>
> I want to unreview it.
Well, you asked Tengei to drop this trailer in response to v3. But
surprisingly got ignored.
>
> Please fix your commit msg to drop marketing and instead describe the
> SoC. I don't see for example any explanation why there is qcm8550 and
> sm8550. Aren't they the same?
>
>
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
>
> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
> AIM300 Series is a highly optimized family of modules designed to
> support AIoT applications. The module is mounted onto Qualcomm AIoT
> carrier board to support verification, evaluation and development. It
> integrates QCS8550 SoC, UFS and PMIC chip etc.
> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Tengfei Fan <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 1a5fb889a444..9cee874a8eae 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -49,8 +49,10 @@ description: |
> msm8996
> msm8998
> qcs404
> + qcs8550
> qcm2290
> qcm6490
> + qcm8550
Drop
> qdu1000
> qrb2210
> qrb4210
> @@ -93,6 +95,7 @@ description: |
> The 'board' element must be one of the following strings:
>
> adp
> + aim300-aiot
We probably need to drop this list, it doesn't surve its purposes.
> cdp
> dragonboard
> idp
> @@ -904,6 +907,14 @@ properties:
> - const: qcom,qcs404-evb
> - const: qcom,qcs404
>
> + - items:
> + - enum:
> + - qcom,qcs8550-aim300-aiot
> + - const: qcom,qcs8550-aim300
> + - const: qcom,qcs8550
> + - const: qcom,qcm8550
In the review comments for v3 you have been asked to add qcom,sm8550.
But not the qcom,qcm8550. I don't think that there is any need to
mention qcm8550 here.
> + - const: qcom,sm8550
> +
> - items:
> - enum:
> - qcom,sa8155p-adp
> --
> 2.17.1
>
--
With best wishes
Dmitry
On 04/02/2024 17:25, Dmitry Baryshkov wrote:
> On Fri, 2 Feb 2024 at 15:34, Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> On 19/01/2024 11:06, Tengfei Fan wrote:
>>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>>> AIM300 Series is a highly optimized family of modules designed to
>>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>>> carrier board to support verification, evaluation and development. It
>>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>>
>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>
>> I want to unreview it.
>
> Well, you asked Tengei to drop this trailer in response to v3. But
> surprisingly got ignored.
>
Indeed.
https://lore.kernel.org/all/[email protected]/
This is just annoying.
Best regards,
Krzysztof
On 19/01/2024 11:06, Tengfei Fan wrote:
> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
> AIM300 Series is a highly optimized family of modules designed to
> support AIoT applications. The module is mounted onto Qualcomm AIoT
> carrier board to support verification, evaluation and development. It
> integrates QCS8550 SoC, UFS and PMIC chip etc.
> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Tengfei Fan <[email protected]>
To be clear, because you keep ignoring my comments:
NAK
Best regards,
Krzysztof
On 19/01/2024 11:06, Tengfei Fan wrote:
> Add SoC Info support for QCM8550 and QCS8550 platform.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Tengfei Fan <[email protected]>
NAK.
Drop my tag.
Best regards,
Krzysztof
On 2/5/2024 4:03 PM, Krzysztof Kozlowski wrote:
> On 19/01/2024 11:06, Tengfei Fan wrote:
>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>> AIM300 Series is a highly optimized family of modules designed to
>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>> carrier board to support verification, evaluation and development. It
>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> Signed-off-by: Tengfei Fan <[email protected]>
>
> To be clear, because you keep ignoring my comments:
>
> NAK
>
> Best regards,
> Krzysztof
>
Yes, I will drop your "Reviewed-by" tag, I had some misunderstand for
your related comments in V3 patch series.
--
Thx and BRs,
Tengfei Fan
On 2/5/2024 4:04 PM, Krzysztof Kozlowski wrote:
> On 19/01/2024 11:06, Tengfei Fan wrote:
>> Add SoC Info support for QCM8550 and QCS8550 platform.
>>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> Signed-off-by: Tengfei Fan <[email protected]>
>
> NAK.
>
> Drop my tag.
>
> Best regards,
> Krzysztof
>
This patch has been applied by Bjorn.
Should I remove your tag only, or do I need to do other processing?
--
Thx and BRs,
Tengfei Fan
On 2/5/2024 12:29 AM, Dmitry Baryshkov wrote:
> On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
>>
>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>> AIM300 Series is a highly optimized family of modules designed to
>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>> carrier board to support verification, evaluation and development. It
>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> Signed-off-by: Tengfei Fan <[email protected]>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 1a5fb889a444..9cee874a8eae 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -49,8 +49,10 @@ description: |
>> msm8996
>> msm8998
>> qcs404
>> + qcs8550
>> qcm2290
>> qcm6490
>> + qcm8550
>
> Drop
we want to introduce qcm8550 here.
qcm8550.dtsi has been introduced and qcs8550-aim300.dtsi include
qcm8550.dtsi directly.
qcs8550 is a QCS version for qcm8550. qcs8550 is a sub-series of
qcm8550. qcm8550 will be a firmware release series from qualcomm.
here is the qcm8550/qcs8550 detailed spec:
https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
here is the sm8550 detailed spec:
https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_C_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
>
>> qdu1000
>> qrb2210
>> qrb4210
>> @@ -93,6 +95,7 @@ description: |
>> The 'board' element must be one of the following strings:
>>
>> adp
>> + aim300-aiot
>
> We probably need to drop this list, it doesn't surve its purposes.
I am a little confused, do you expect to just remove this "aim300-aiot"
or do you want to introduce a new patch and remove the whole list?
>
>> cdp
>> dragonboard
>> idp
>> @@ -904,6 +907,14 @@ properties:
>> - const: qcom,qcs404-evb
>> - const: qcom,qcs404
>>
>> + - items:
>> + - enum:
>> + - qcom,qcs8550-aim300-aiot
>> + - const: qcom,qcs8550-aim300
>> + - const: qcom,qcs8550
>> + - const: qcom,qcm8550
>
> In the review comments for v3 you have been asked to add qcom,sm8550.
> But not the qcom,qcm8550. I don't think that there is any need to
> mention qcm8550 here.
qcm8550 and sm8550 are different, they have different firmware release.
AIM300 AIoT board depend on qcs8550, qcs8550 is a QCS version for
qcm8550. Modem RF only in qcm8550 but not in qcs8550.
>
>> + - const: qcom,sm8550
>> +
>> - items:
>> - enum:
>> - qcom,sa8155p-adp
>> --
>> 2.17.1
>>
>
>
--
Thx and BRs,
Tengfei Fan
On 05/02/2024 11:20, Tengfei Fan wrote:
>
>
> On 2/5/2024 12:29 AM, Dmitry Baryshkov wrote:
>> On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
>>>
>>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>>> AIM300 Series is a highly optimized family of modules designed to
>>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>>> carrier board to support verification, evaluation and development. It
>>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>>
>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>> Signed-off-by: Tengfei Fan <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
>>> 1 file changed, 11 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> index 1a5fb889a444..9cee874a8eae 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> @@ -49,8 +49,10 @@ description: |
>>> msm8996
>>> msm8998
>>> qcs404
>>> + qcs8550
>>> qcm2290
>>> qcm6490
>>> + qcm8550
>>
>> Drop
>
> we want to introduce qcm8550 here.
>
> qcm8550.dtsi has been introduced and qcs8550-aim300.dtsi include
> qcm8550.dtsi directly.
>
> qcs8550 is a QCS version for qcm8550. qcs8550 is a sub-series of
> qcm8550. qcm8550 will be a firmware release series from qualcomm.
>
> here is the qcm8550/qcs8550 detailed spec:
> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>
> here is the sm8550 detailed spec:
> https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_C_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
That's 8 gen 3, so SM8650, not SM8550.
Best regards,
Krzysztof
On 05/02/2024 11:10, Tengfei Fan wrote:
>
>
> On 2/5/2024 4:04 PM, Krzysztof Kozlowski wrote:
>> On 19/01/2024 11:06, Tengfei Fan wrote:
>>> Add SoC Info support for QCM8550 and QCS8550 platform.
>>>
>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>> Signed-off-by: Tengfei Fan <[email protected]>
>>
>> NAK.
>>
>> Drop my tag.
>>
>> Best regards,
>> Krzysztof
>>
>
> This patch has been applied by Bjorn.
>
> Should I remove your tag only, or do I need to do other processing?
Nothing to do in such case.
Best regards,
Krzysztof
On Mon, 5 Feb 2024 at 12:21, Tengfei Fan <[email protected]> wrote:
>
>
>
> On 2/5/2024 12:29 AM, Dmitry Baryshkov wrote:
> > On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
> >>
> >> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
> >> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
> >> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
> >> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
> >> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
> >> AIM300 Series is a highly optimized family of modules designed to
> >> support AIoT applications. The module is mounted onto Qualcomm AIoT
> >> carrier board to support verification, evaluation and development. It
> >> integrates QCS8550 SoC, UFS and PMIC chip etc.
> >> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
> >>
> >> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> >> Signed-off-by: Tengfei Fan <[email protected]>
> >> ---
> >> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
> >> 1 file changed, 11 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> index 1a5fb889a444..9cee874a8eae 100644
> >> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> >> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> @@ -49,8 +49,10 @@ description: |
> >> msm8996
> >> msm8998
> >> qcs404
> >> + qcs8550
> >> qcm2290
> >> qcm6490
> >> + qcm8550
> >
> > Drop
>
> we want to introduce qcm8550 here.
What for. It either had to be introduced beforehand, or it should be
introduced when one adds support for an actual qcm8550 device.
> qcm8550.dtsi has been introduced and qcs8550-aim300.dtsi include
> qcm8550.dtsi directly.
>
> qcs8550 is a QCS version for qcm8550. qcs8550 is a sub-series of
> qcm8550. qcm8550 will be a firmware release series from qualcomm.
All three names refer to the different kinds of the same platform. The
base chip name is sm8550, so it is the last one. Other than that,
there is no need to include any SoC compatibles other than the actual
SoC name. See existing qrb devices for an inspiration.
>
> here is the qcm8550/qcs8550 detailed spec:
> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>
> here is the sm8550 detailed spec:
> https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_C_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
Can you please summarise the _actual_ difference between qcm8550,
qcs8550 and sm8550? Are they fully soft compatible? Soft compatible
except the modem? Pin compatible?
>
> >
> >> qdu1000
> >> qrb2210
> >> qrb4210
> >> @@ -93,6 +95,7 @@ description: |
> >> The 'board' element must be one of the following strings:
> >>
> >> adp
> >> + aim300-aiot
> >
> > We probably need to drop this list, it doesn't surve its purposes.
>
> I am a little confused, do you expect to just remove this "aim300-aiot"
> or do you want to introduce a new patch and remove the whole list?
If you were following the list, you would have seen the patch
reworking the bindings.
>
> >
> >> cdp
> >> dragonboard
> >> idp
> >> @@ -904,6 +907,14 @@ properties:
> >> - const: qcom,qcs404-evb
> >> - const: qcom,qcs404
> >>
> >> + - items:
> >> + - enum:
> >> + - qcom,qcs8550-aim300-aiot
> >> + - const: qcom,qcs8550-aim300
> >> + - const: qcom,qcs8550
> >> + - const: qcom,qcm8550
> >
> > In the review comments for v3 you have been asked to add qcom,sm8550.
> > But not the qcom,qcm8550. I don't think that there is any need to
> > mention qcm8550 here.
>
> qcm8550 and sm8550 are different, they have different firmware release.
>
> AIM300 AIoT board depend on qcs8550, qcs8550 is a QCS version for
> qcm8550. Modem RF only in qcm8550 but not in qcs8550.
There are no 'dependecies' here. The thing is about declaring compatibility.
In my opinion, the qcm8550 is an unnecesary part of the equation. You
declare compatibility with the board itself, with the SoM, with the
actual SoC and with the base of the series. Anybody caring for the
difference between QCM, QCS and SM will have to check for both
qcom,qcs8550 and qcom,qcm8550 anyway, as there are differences on the
modem side.
> >> + - const: qcom,sm8550
> >> +
> >> - items:
> >> - enum:
> >> - qcom,sa8155p-adp
> >> --
--
With best wishes
Dmitry
On 2/5/2024 9:48 PM, Dmitry Baryshkov wrote:
> On Mon, 5 Feb 2024 at 12:21, Tengfei Fan <[email protected]> wrote:
>>
>>
>>
>> On 2/5/2024 12:29 AM, Dmitry Baryshkov wrote:
>>> On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
>>>>
>>>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>>>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>>>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>>>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>>>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>>>> AIM300 Series is a highly optimized family of modules designed to
>>>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>>>> carrier board to support verification, evaluation and development. It
>>>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>>>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>>>
>>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>>> Signed-off-by: Tengfei Fan <[email protected]>
>>>> ---
>>>> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
>>>> 1 file changed, 11 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> index 1a5fb889a444..9cee874a8eae 100644
>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> @@ -49,8 +49,10 @@ description: |
>>>> msm8996
>>>> msm8998
>>>> qcs404
>>>> + qcs8550
>>>> qcm2290
>>>> qcm6490
>>>> + qcm8550
>>>
>>> Drop
>>
>> we want to introduce qcm8550 here.
>
> What for. It either had to be introduced beforehand, or it should be
> introduced when one adds support for an actual qcm8550 device.
>
>> qcm8550.dtsi has been introduced and qcs8550-aim300.dtsi include
>> qcm8550.dtsi directly.
>>
>> qcs8550 is a QCS version for qcm8550. qcs8550 is a sub-series of
>> qcm8550. qcm8550 will be a firmware release series from qualcomm.
>
> All three names refer to the different kinds of the same platform. The
> base chip name is sm8550, so it is the last one. Other than that,
> there is no need to include any SoC compatibles other than the actual
> SoC name. See existing qrb devices for an inspiration.
>
>>
>> here is the qcm8550/qcs8550 detailed spec:
>> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>>
>> here is the sm8550 detailed spec:
>> https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_C_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
>
> Can you please summarise the _actual_ difference between qcm8550,
> qcs8550 and sm8550? Are they fully soft compatible? Soft compatible
> except the modem? Pin compatible?
we can remove the qcm8550 compatible for now, and rename current dtsi
back for qcs8550.dtsi, and only introduce qcm8550 later when there is
qcm8550 board public-ed.
From software point of view, currently it is single firmware image
release for both qcm8550 and qcs8550, and the firmware is not grantee
for sm8550 software compatible.
From hardware point of view, qcm8550, qcs8550, sm8550 are different
hardware socs, qcm8550, qcs8550 is derived from sm8550. We can only
share the public document about those soc descriptions [1]. For soc
itself, it is all similar difference for QCS and QCM version.
Currently(in current development stage) there is not notable software
difference needed other than memory map in kernel side needed to be
differentiate from qcm8550 qcs8550 to sm8550.
[1]
https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>
>>
>>>
>>>> qdu1000
>>>> qrb2210
>>>> qrb4210
>>>> @@ -93,6 +95,7 @@ description: |
>>>> The 'board' element must be one of the following strings:
>>>>
>>>> adp
>>>> + aim300-aiot
>>>
>>> We probably need to drop this list, it doesn't surve its purposes.
>>
>> I am a little confused, do you expect to just remove this "aim300-aiot"
>> or do you want to introduce a new patch and remove the whole list?
>
> If you were following the list, you would have seen the patch
> reworking the bindings.
>
>>
>>>
>>>> cdp
>>>> dragonboard
>>>> idp
>>>> @@ -904,6 +907,14 @@ properties:
>>>> - const: qcom,qcs404-evb
>>>> - const: qcom,qcs404
>>>>
>>>> + - items:
>>>> + - enum:
>>>> + - qcom,qcs8550-aim300-aiot
>>>> + - const: qcom,qcs8550-aim300
>>>> + - const: qcom,qcs8550
>>>> + - const: qcom,qcm8550
>>>
>>> In the review comments for v3 you have been asked to add qcom,sm8550.
>>> But not the qcom,qcm8550. I don't think that there is any need to
>>> mention qcm8550 here.
>>
>> qcm8550 and sm8550 are different, they have different firmware release.
>>
>> AIM300 AIoT board depend on qcs8550, qcs8550 is a QCS version for
>> qcm8550. Modem RF only in qcm8550 but not in qcs8550.
>
> There are no 'dependecies' here. The thing is about declaring compatibility.
> In my opinion, the qcm8550 is an unnecesary part of the equation. You
> declare compatibility with the board itself, with the SoM, with the
> actual SoC and with the base of the series. Anybody caring for the
> difference between QCM, QCS and SM will have to check for both
> qcom,qcs8550 and qcom,qcm8550 anyway, as there are differences on the
> modem side.
>
>>>> + - const: qcom,sm8550
>>>> +
>>>> - items:
>>>> - enum:
>>>> - qcom,sa8155p-adp
>>>> --
>
--
Thx and BRs,
Aiqun(Maria) Yu
On Tue, 20 Feb 2024 at 11:09, Aiqun Yu (Maria) <[email protected]> wrote:
>
>
>
> On 2/5/2024 9:48 PM, Dmitry Baryshkov wrote:
> > On Mon, 5 Feb 2024 at 12:21, Tengfei Fan <[email protected]> wrote:
> >>
> >>
> >>
> >> On 2/5/2024 12:29 AM, Dmitry Baryshkov wrote:
> >>> On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
> >>>>
> >>>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
> >>>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
> >>>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
> >>>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
> >>>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
> >>>> AIM300 Series is a highly optimized family of modules designed to
> >>>> support AIoT applications. The module is mounted onto Qualcomm AIoT
> >>>> carrier board to support verification, evaluation and development. It
> >>>> integrates QCS8550 SoC, UFS and PMIC chip etc.
> >>>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
> >>>>
> >>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> >>>> Signed-off-by: Tengfei Fan <[email protected]>
> >>>> ---
> >>>> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
> >>>> 1 file changed, 11 insertions(+)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> >>>> index 1a5fb889a444..9cee874a8eae 100644
> >>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> >>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> >>>> @@ -49,8 +49,10 @@ description: |
> >>>> msm8996
> >>>> msm8998
> >>>> qcs404
> >>>> + qcs8550
> >>>> qcm2290
> >>>> qcm6490
> >>>> + qcm8550
> >>>
> >>> Drop
> >>
> >> we want to introduce qcm8550 here.
> >
> > What for. It either had to be introduced beforehand, or it should be
> > introduced when one adds support for an actual qcm8550 device.
> >
> >> qcm8550.dtsi has been introduced and qcs8550-aim300.dtsi include
> >> qcm8550.dtsi directly.
> >>
> >> qcs8550 is a QCS version for qcm8550. qcs8550 is a sub-series of
> >> qcm8550. qcm8550 will be a firmware release series from qualcomm.
> >
> > All three names refer to the different kinds of the same platform. The
> > base chip name is sm8550, so it is the last one. Other than that,
> > there is no need to include any SoC compatibles other than the actual
> > SoC name. See existing qrb devices for an inspiration.
> >
> >>
> >> here is the qcm8550/qcs8550 detailed spec:
> >> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
> >>
> >> here is the sm8550 detailed spec:
> >> https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_C_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
> >
> > Can you please summarise the _actual_ difference between qcm8550,
> > qcs8550 and sm8550? Are they fully soft compatible? Soft compatible
> > except the modem? Pin compatible?
>
> we can remove the qcm8550 compatible for now, and rename current dtsi
> back for qcs8550.dtsi, and only introduce qcm8550 later when there is
> qcm8550 board public-ed.
Yes, please.
>
> From software point of view, currently it is single firmware image
> release for both qcm8550 and qcs8550, and the firmware is not grantee
> for sm8550 software compatible.
I assume that modem.mbn is different for qcm and qcs devices. Or does
qcs completely miss the modem DSP?
>
> From hardware point of view, qcm8550, qcs8550, sm8550 are different
> hardware socs, qcm8550, qcs8550 is derived from sm8550. We can only
> share the public document about those soc descriptions [1]. For soc
> itself, it is all similar difference for QCS and QCM version.
> Currently(in current development stage) there is not notable software
> difference needed other than memory map in kernel side needed to be
> differentiate from qcm8550 qcs8550 to sm8550.
>
> [1]
> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>
> >
> >>
> >>>
> >>>> qdu1000
> >>>> qrb2210
> >>>> qrb4210
> >>>> @@ -93,6 +95,7 @@ description: |
> >>>> The 'board' element must be one of the following strings:
> >>>>
> >>>> adp
> >>>> + aim300-aiot
> >>>
> >>> We probably need to drop this list, it doesn't surve its purposes.
> >>
> >> I am a little confused, do you expect to just remove this "aim300-aiot"
> >> or do you want to introduce a new patch and remove the whole list?
> >
> > If you were following the list, you would have seen the patch
> > reworking the bindings.
> >
> >>
> >>>
> >>>> cdp
> >>>> dragonboard
> >>>> idp
> >>>> @@ -904,6 +907,14 @@ properties:
> >>>> - const: qcom,qcs404-evb
> >>>> - const: qcom,qcs404
> >>>>
> >>>> + - items:
> >>>> + - enum:
> >>>> + - qcom,qcs8550-aim300-aiot
> >>>> + - const: qcom,qcs8550-aim300
> >>>> + - const: qcom,qcs8550
> >>>> + - const: qcom,qcm8550
> >>>
> >>> In the review comments for v3 you have been asked to add qcom,sm8550.
> >>> But not the qcom,qcm8550. I don't think that there is any need to
> >>> mention qcm8550 here.
> >>
> >> qcm8550 and sm8550 are different, they have different firmware release.
> >>
> >> AIM300 AIoT board depend on qcs8550, qcs8550 is a QCS version for
> >> qcm8550. Modem RF only in qcm8550 but not in qcs8550.
> >
> > There are no 'dependecies' here. The thing is about declaring compatibility.
> > In my opinion, the qcm8550 is an unnecesary part of the equation. You
> > declare compatibility with the board itself, with the SoM, with the
> > actual SoC and with the base of the series. Anybody caring for the
> > difference between QCM, QCS and SM will have to check for both
> > qcom,qcs8550 and qcom,qcm8550 anyway, as there are differences on the
> > modem side.
> >
> >>>> + - const: qcom,sm8550
> >>>> +
> >>>> - items:
> >>>> - enum:
> >>>> - qcom,sa8155p-adp
> >>>> --
> >
>
> --
> Thx and BRs,
> Aiqun(Maria) Yu
--
With best wishes
Dmitry
On 2/20/2024 5:15 PM, Dmitry Baryshkov wrote:
> On Tue, 20 Feb 2024 at 11:09, Aiqun Yu (Maria) <[email protected]> wrote:
>>
>>
>>
>> On 2/5/2024 9:48 PM, Dmitry Baryshkov wrote:
>>> On Mon, 5 Feb 2024 at 12:21, Tengfei Fan <[email protected]> wrote:
>>>>
>>>>
>>>>
>>>> On 2/5/2024 12:29 AM, Dmitry Baryshkov wrote:
>>>>> On Fri, 19 Jan 2024 at 11:07, Tengfei Fan <[email protected]> wrote:
>>>>>>
>>>>>> Document QCM8550, QCS8550 SoC and the AIM300 AIoT board bindings.
>>>>>> QCS8550 and QCM8550 processor combines powerful computing, extreme edge
>>>>>> AI processing, Wi-Fi 7, and robust video and graphics for a wide range
>>>>>> of use cases for the Internet of Things (IoT). QCS8550 is a QCS version
>>>>>> for QCM8550. Modem RF only in QCM8550 but not in QCS8550.
>>>>>> AIM300 Series is a highly optimized family of modules designed to
>>>>>> support AIoT applications. The module is mounted onto Qualcomm AIoT
>>>>>> carrier board to support verification, evaluation and development. It
>>>>>> integrates QCS8550 SoC, UFS and PMIC chip etc.
>>>>>> AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
>>>>>>
>>>>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>>>>> Signed-off-by: Tengfei Fan <[email protected]>
>>>>>> ---
>>>>>> Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++
>>>>>> 1 file changed, 11 insertions(+)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>>>> index 1a5fb889a444..9cee874a8eae 100644
>>>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>>>> @@ -49,8 +49,10 @@ description: |
>>>>>> msm8996
>>>>>> msm8998
>>>>>> qcs404
>>>>>> + qcs8550
>>>>>> qcm2290
>>>>>> qcm6490
>>>>>> + qcm8550
>>>>>
>>>>> Drop
>>>>
>>>> we want to introduce qcm8550 here.
>>>
>>> What for. It either had to be introduced beforehand, or it should be
>>> introduced when one adds support for an actual qcm8550 device.
>>>
>>>> qcm8550.dtsi has been introduced and qcs8550-aim300.dtsi include
>>>> qcm8550.dtsi directly.
>>>>
>>>> qcs8550 is a QCS version for qcm8550. qcs8550 is a sub-series of
>>>> qcm8550. qcm8550 will be a firmware release series from qualcomm.
>>>
>>> All three names refer to the different kinds of the same platform. The
>>> base chip name is sm8550, so it is the last one. Other than that,
>>> there is no need to include any SoC compatibles other than the actual
>>> SoC name. See existing qrb devices for an inspiration.
>>>
>>>>
>>>> here is the qcm8550/qcs8550 detailed spec:
>>>> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>>>>
>>>> here is the sm8550 detailed spec:
>>>> https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_C_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
>>>
>>> Can you please summarise the _actual_ difference between qcm8550,
>>> qcs8550 and sm8550? Are they fully soft compatible? Soft compatible
>>> except the modem? Pin compatible?
>>
>> we can remove the qcm8550 compatible for now, and rename current dtsi
>> back for qcs8550.dtsi, and only introduce qcm8550 later when there is
>> qcm8550 board public-ed.
>
> Yes, please.
>
>>
>> From software point of view, currently it is single firmware image
>> release for both qcm8550 and qcs8550, and the firmware is not grantee
>> for sm8550 software compatible.
>
> I assume that modem.mbn is different for qcm and qcs devices. Or does
> qcs completely miss the modem DSP?
You are right, modem.mbn part is different. QCS have a gps only modem image.
>
>>
>> From hardware point of view, qcm8550, qcs8550, sm8550 are different
>> hardware socs, qcm8550, qcs8550 is derived from sm8550. We can only
>> share the public document about those soc descriptions [1]. For soc
>> itself, it is all similar difference for QCS and QCM version.
>> Currently(in current development stage) there is not notable software
>> difference needed other than memory map in kernel side needed to be
>> differentiate from qcm8550 qcs8550 to sm8550.
>>
>> [1]
>> https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
>>
>>>
>>>>
>>>>>
>>>>>> qdu1000
>>>>>> qrb2210
>>>>>> qrb4210
>>>>>> @@ -93,6 +95,7 @@ description: |
>>>>>> The 'board' element must be one of the following strings:
>>>>>>
>>>>>> adp
>>>>>> + aim300-aiot
>>>>>
>>>>> We probably need to drop this list, it doesn't surve its purposes.
>>>>
>>>> I am a little confused, do you expect to just remove this "aim300-aiot"
>>>> or do you want to introduce a new patch and remove the whole list?
>>>
>>> If you were following the list, you would have seen the patch
>>> reworking the bindings.
>>>
>>>>
>>>>>
>>>>>> cdp
>>>>>> dragonboard
>>>>>> idp
>>>>>> @@ -904,6 +907,14 @@ properties:
>>>>>> - const: qcom,qcs404-evb
>>>>>> - const: qcom,qcs404
>>>>>>
>>>>>> + - items:
>>>>>> + - enum:
>>>>>> + - qcom,qcs8550-aim300-aiot
>>>>>> + - const: qcom,qcs8550-aim300
>>>>>> + - const: qcom,qcs8550
>>>>>> + - const: qcom,qcm8550
>>>>>
>>>>> In the review comments for v3 you have been asked to add qcom,sm8550.
>>>>> But not the qcom,qcm8550. I don't think that there is any need to
>>>>> mention qcm8550 here.
>>>>
>>>> qcm8550 and sm8550 are different, they have different firmware release.
>>>>
>>>> AIM300 AIoT board depend on qcs8550, qcs8550 is a QCS version for
>>>> qcm8550. Modem RF only in qcm8550 but not in qcs8550.
>>>
>>> There are no 'dependecies' here. The thing is about declaring compatibility.
>>> In my opinion, the qcm8550 is an unnecesary part of the equation. You
>>> declare compatibility with the board itself, with the SoM, with the
>>> actual SoC and with the base of the series. Anybody caring for the
>>> difference between QCM, QCS and SM will have to check for both
>>> qcom,qcs8550 and qcom,qcm8550 anyway, as there are differences on the
>>> modem side.
>>>
>>>>>> + - const: qcom,sm8550
>>>>>> +
>>>>>> - items:
>>>>>> - enum:
>>>>>> - qcom,sa8155p-adp
>>>>>> --
>>>
>>
>> --
>> Thx and BRs,
>> Aiqun(Maria) Yu
>
>
>
--
Thx and BRs,
Aiqun(Maria) Yu