This series are based on 5.8-rc1 and provide 7 patch
to support mediatek SOC MT8183
Change since v6
- move ddp component define into mtk_mmsys.h
- add mmsys private data to support different ic path connection
- add mt8183-mmsys.c to support 8183 path connection
- fix reviewed issue in v6
Change since v5
- fix reviewed issue in v5
base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219
Change since v4
- fix reviewed issue in v4
Change since v3
- fix reviewed issue in v3
- fix type error in v3
- fix conflict with iommu patch
Change since v2
- fix reviewed issue in v2
- add mutex node into dts file
Changes since v1:
- fix reviewed issue in v1
- add dts for mt8183 display nodes
- adjust display clock control flow in patch 22
- add vmap support for mediatek drm in patch 23
- fix page offset issue for mmap function in patch 24
- enable allow_fb_modifiers for mediatek drm in patch 25
Yongqiang Niu (7):
dt-bindings: mediatek: add rdma_fifo_size description for mt8183
display
drm/mediatek: move ddp component define into mtk_mmsys.h
mtk-mmsys: add mmsys private data
mtk-mmsys: add mt8183 mmsys support
drm/mediatek: add fifo_size into rdma private data
drm/mediatek: add support for mediatek SOC MT8183
arm64: dts: add display nodes for mt8183
.../bindings/display/mediatek/mediatek,disp.txt | 14 ++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +--
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 ++++
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mmsys/Makefile | 3 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 154 ++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 276 ++++-----------------
include/linux/soc/mediatek/mtk-mmsys.h | 48 ++++
13 files changed, 749 insertions(+), 262 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
--
1.8.1.1.dirty
This patch add support for mediatek SOC MT8183
1. add ovl private data
2. add rdma private data
3. add mutes private data
4. add main and external path module for crtc create
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++
4 files changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 28651bc..8cf9f3b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+};
+
+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = &mt8173_ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = &mt8183_ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = &mt8183_ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 794acc5..51f2a0c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
.fifo_size = SZ_8K,
};
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = &mt8173_rdma_driver_data},
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = &mt8183_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 014c1bb..60788c1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -15,6 +15,8 @@
#define MT2701_DISP_MUTEX0_MOD0 0x2c
#define MT2701_DISP_MUTEX0_SOF0 0x30
+#define MT8183_DISP_MUTEX0_MOD0 0x30
+#define MT8183_DISP_MUTEX0_SOF0 0x2c
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
@@ -25,6 +27,18 @@
#define INT_MUTEX BIT(1)
+#define MT8183_MUTEX_MOD_DISP_RDMA0 0
+#define MT8183_MUTEX_MOD_DISP_RDMA1 1
+#define MT8183_MUTEX_MOD_DISP_OVL0 9
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
+#define MT8183_MUTEX_MOD_DISP_WDMA0 12
+#define MT8183_MUTEX_MOD_DISP_COLOR0 13
+#define MT8183_MUTEX_MOD_DISP_CCORR0 14
+#define MT8183_MUTEX_MOD_DISP_AAL0 15
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
+#define MT8183_MUTEX_MOD_DISP_DITHER0 17
+
#define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA0 13
@@ -74,6 +88,10 @@
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
+#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6)
+#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+
struct mtk_disp_mutex {
int id;
@@ -153,6 +171,20 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
+ [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
+};
+
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -163,6 +195,12 @@ struct mtk_ddp {
[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
+ [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
+ [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
+};
+
static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -184,6 +222,13 @@ struct mtk_ddp {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
+static const struct mtk_ddp_data mt8183_ddp_driver_data = {
+ .mutex_mod = mt8183_mutex_mod,
+ .mutex_sof = mt8183_mutex_sof,
+ .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
{
struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
.data = &mt2712_ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = &mt8173_ddp_driver_data},
+ { .compatible = "mediatek,mt8183-disp-mutex",
+ .data = &mt8183_ddp_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6bd3694..267e91e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -119,6 +119,24 @@
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -143,6 +161,13 @@
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+ .main_path = mt8183_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
+ .ext_path = mt8183_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt8183-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
@@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8183-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8183-dsi",
+ .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt2701-dpi",
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8173-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8183-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8183-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev)
.data = &mt2712_mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
{ }
};
--
1.8.1.1.dirty
rdma fifo size may be different even in same SOC, add this
property to the corresponding rdma
Change-Id: I67635ec7f3f59cf4cbc7737285e5e28ff0ab71c9
Signed-off-by: Yongqiang Niu <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index b91e709..e6bbe32 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -66,6 +66,11 @@ Required properties (DMA function blocks):
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
+Optional properties (RDMA function blocks):
+- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this
+ property to the corresponding rdma
+ the value is the Max value which defined in hardware data sheet.
+
Examples:
mmsys: clock-controller@14000000 {
@@ -207,3 +212,12 @@ od@14023000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OD>;
};
+
+rdma1: rdma@1400c000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ mediatek,rdma_fifo_size = <2048>;
+};
--
1.8.1.1.dirty
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2020年8月8日 週六 上午11:05寫道：
>
> This patch add support for mediatek SOC MT8183
> 1. add ovl private data
> 2. add rdma private data
> 3. add mutes private data
> 4. add main and external path module for crtc create
>
> Signed-off-by: Yongqiang Niu <[email protected]>
[snip]
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = &mt2701_ovl_driver_data},
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = &mt8173_ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl",
"mediatek,mt8183-disp-ovl" is not defined in binding document [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt?h=v5.8
> + .data = &mt8183_ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
Ditto.
> + .data = &mt8183_ovl_2l_driver_data},
> {},
> };
[snip]
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = &mt8173_rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma",
Ditto.
> + .data = &mt8183_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
[snip]
> +
> struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
> {
> struct mtk_ddp *ddp = dev_get_drvdata(dev);
> @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
> .data = &mt2712_ddp_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = &mt8173_ddp_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
Ditto.
Regards,
Chun-Kuang.
> + .data = &mt8183_ddp_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
Hi, Yongqiang:
This series is 'v8', not 'RESEND v7'
Yongqiang Niu <[email protected]> 於 2020年8月8日 週六 上午10:56寫道：
>
> This series are based on 5.8-rc1 and provide 7 patch
> to support mediatek SOC MT8183
>
> Change since v6
> - move ddp component define into mtk_mmsys.h
> - add mmsys private data to support different ic path connection
> - add mt8183-mmsys.c to support 8183 path connection
> - fix reviewed issue in v6
>
> Change since v5
> - fix reviewed issue in v5
> base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219
>
> Change since v4
> - fix reviewed issue in v4
>
> Change since v3
> - fix reviewed issue in v3
> - fix type error in v3
> - fix conflict with iommu patch
>
> Change since v2
> - fix reviewed issue in v2
> - add mutex node into dts file
>
> Changes since v1:
> - fix reviewed issue in v1
> - add dts for mt8183 display nodes
> - adjust display clock control flow in patch 22
> - add vmap support for mediatek drm in patch 23
> - fix page offset issue for mmap function in patch 24
> - enable allow_fb_modifiers for mediatek drm in patch 25
>
> Yongqiang Niu (7):
> dt-bindings: mediatek: add rdma_fifo_size description for mt8183
> display
> drm/mediatek: move ddp component define into mtk_mmsys.h
> mtk-mmsys: add mmsys private data
> mtk-mmsys: add mt8183 mmsys support
> drm/mediatek: add fifo_size into rdma private data
> drm/mediatek: add support for mediatek SOC MT8183
> arm64: dts: add display nodes for mt8183
>
> .../bindings/display/mediatek/mediatek,disp.txt | 14 ++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 ++++
> drivers/soc/mediatek/Makefile | 1 +
> drivers/soc/mediatek/mmsys/Makefile | 3 +
> drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++
> drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 154 ++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 276 ++++-----------------
> include/linux/soc/mediatek/mtk-mmsys.h | 48 ++++
> 13 files changed, 749 insertions(+), 262 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2020年8月8日 週六 上午11:04寫道：
>
> rdma fifo size may be different even in same SOC, add this
> property to the corresponding rdma
>
> Change-Id: I67635ec7f3f59cf4cbc7737285e5e28ff0ab71c9
Remove change-id.
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index b91e709..e6bbe32 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -66,6 +66,11 @@ Required properties (DMA function blocks):
> argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> for details.
>
> +Optional properties (RDMA function blocks):
> +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this
> + property to the corresponding rdma
> + the value is the Max value which defined in hardware data sheet.
> +
> Examples:
>
> mmsys: clock-controller@14000000 {
> @@ -207,3 +212,12 @@ od@14023000 {
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_OD>;
> };
> +
> +rdma1: rdma@1400c000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + mediatek,rdma_fifo_size = <2048>;
> +};
I would like you to show rdma0 as well so that could prove two rdma
have different fifo size in the same SoC.
Regards,
Chun-Kuang.
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Chun-Kuang Hu <[email protected]> 於 2020年8月9日 週日 上午8:56寫道：
>
> Hi, Yongqiang:
>
> Yongqiang Niu <[email protected]> 於 2020年8月8日 週六 上午11:04寫道：
> >
> > rdma fifo size may be different even in same SOC, add this
> > property to the corresponding rdma
> >
> > Change-Id: I67635ec7f3f59cf4cbc7737285e5e28ff0ab71c9
>
> Remove change-id.
>
> > Signed-off-by: Yongqiang Niu <[email protected]>
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > index b91e709..e6bbe32 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > @@ -66,6 +66,11 @@ Required properties (DMA function blocks):
> > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> > for details.
> >
> > +Optional properties (RDMA function blocks):
> > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this
> > + property to the corresponding rdma
> > + the value is the Max value which defined in hardware data sheet.
> > +
> > Examples:
> >
> > mmsys: clock-controller@14000000 {
> > @@ -207,3 +212,12 @@ od@14023000 {
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > clocks = <&mmsys CLK_MM_DISP_OD>;
> > };
> > +
> > +rdma1: rdma@1400c000 {
> > + compatible = "mediatek,mt8183-disp-rdma";
> > + reg = <0 0x1400c000 0 0x1000>;
> > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > + mediatek,rdma_fifo_size = <2048>;
> > +};
>
> I would like you to show rdma0 as well so that could prove two rdma
> have different fifo size in the same SoC.
Sorry, rdma0 is already define in this file. Just ignore this comment.
Regards,
Chun-Kuang.
>
> Regards,
> Chun-Kuang.
>
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Sat, Aug 08, 2020 at 10:53:45AM +0800, Yongqiang Niu wrote:
> rdma fifo size may be different even in same SOC, add this
> property to the corresponding rdma
>
> Change-Id: I67635ec7f3f59cf4cbc7737285e5e28ff0ab71c9
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index b91e709..e6bbe32 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -66,6 +66,11 @@ Required properties (DMA function blocks):
> argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> for details.
>
> +Optional properties (RDMA function blocks):
> +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this
mediatek,rdma-fifo-size
What's the range/set of valid values?
> + property to the corresponding rdma
> + the value is the Max value which defined in hardware data sheet.
> +
> Examples:
>
> mmsys: clock-controller@14000000 {
> @@ -207,3 +212,12 @@ od@14023000 {
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_OD>;
> };
> +
> +rdma1: rdma@1400c000 {
Does a new property really need a whole new example?
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + mediatek,rdma_fifo_size = <2048>;
> +};
> --
> 1.8.1.1.dirty