Hi, Jason:
jason-jh.lin <[email protected]> 於 2021年6月30日 週三 下午1:18寫道：
>
> add gce node on dts file.
>
> Change-Id: I805455cb7c645cb5a24ce1c87fe891a807069123
> Signed-off-by: jason-jh.lin <[email protected]>
> ---
> This patch is based on [1]
> [1] Add Mediatek SoC MT8195 and evaluation board dts and Makefile
> - https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index c146a91c6272..38054196eea4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -6,6 +6,7 @@
>
> /dts-v1/;
> #include <dt-bindings/clock/mt8195-clk.h>
> +#include <dt-bindings/gce/mt8195-gce.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/power/mt8195-power.h>
> @@ -717,6 +718,26 @@
> #clock-cells = <1>;
> };
>
> + gce0: mdp_mailbox@10320000 {
> + compatible = "mediatek,mt8195-gce";
> + reg = <0 0x10320000 0 0x4000>;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
> + #mbox-cells = <3>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> + <&infracfg_ao CLK_INFRA_AO_GCE2>;
> + clock-names = "gce", "gce1";
> + };
> +
> + gce1: disp_mailbox@10330000 {
> + compatible = "mediatek,mt8195-gce";
> + reg = <0 0x10330000 0 0x4000>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
> + #mbox-cells = <3>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> + <&infracfg_ao CLK_INFRA_AO_GCE2>;
> + clock-names = "gce", "gce1";
I think each gce could be broken into two function block, the core
function block and event processing block.
Each block has independent clock source and "gce" is for core function
block and "gce1" is for event processing block, is it?
If so, the core function of gce0 and gce1 has common clock source
(<&infracfg_ao CLK_INFRA_AO_GCE>), right?
Regards,
Chun-Kuang.
> + };
> +
> uart0: serial@11001100 {
> compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
> reg = <0 0x11001100 0 0x100>;
> --
> 2.18.0
>
On Thu, 2021-07-01 at 07:21 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <[email protected]> 於 2021年6月30日 週三 下午1:18寫道：
> >
> > add gce node on dts file.
> >
> > Change-Id: I805455cb7c645cb5a24ce1c87fe891a807069123
> > Signed-off-by: jason-jh.lin <[email protected]>
> > ---
> > This patch is based on [1]
> > [1] Add Mediatek SoC MT8195 and evaluation board dts and Makefile
> > -
> > https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21
> > +++++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index c146a91c6272..38054196eea4 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -6,6 +6,7 @@
> >
> > /dts-v1/;
> > #include <dt-bindings/clock/mt8195-clk.h>
> > +#include <dt-bindings/gce/mt8195-gce.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/power/mt8195-power.h>
> > @@ -717,6 +718,26 @@
> > #clock-cells = <1>;
> > };
> >
> > + gce0: mdp_mailbox@10320000 {
> > + compatible = "mediatek,mt8195-gce";
> > + reg = <0 0x10320000 0 0x4000>;
> > + interrupts = <GIC_SPI 226
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + #mbox-cells = <3>;
> > + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> > + <&infracfg_ao CLK_INFRA_AO_GCE2>;
> > + clock-names = "gce", "gce1";
> > + };
> > +
> > + gce1: disp_mailbox@10330000 {
> > + compatible = "mediatek,mt8195-gce";
> > + reg = <0 0x10330000 0 0x4000>;
> > + interrupts = <GIC_SPI 228
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + #mbox-cells = <3>;
> > + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> > + <&infracfg_ao CLK_INFRA_AO_GCE2>;
> > + clock-names = "gce", "gce1";
>
> I think each gce could be broken into two function block, the core
> function block and event processing block.
> Each block has independent clock source and "gce" is for core
> function
> block and "gce1" is for event processing block, is it?
> If so, the core function of gce0 and gce1 has common clock source
> (<&infracfg_ao CLK_INFRA_AO_GCE>), right?
>
> Regards,
> Chun-Kuang.
>
> > + };
> > +
> > uart0: serial@11001100 {
> > compatible = "mediatek,mt8195-uart",
> > "mediatek,mt6577-uart";
> > reg = <0 0x11001100 0 0x100>;
> > --
> > 2.18.0
> >
gce0 and gce1 are two duplicate hardware node each of them have thier
own core function block and event proccessing block.
The clocks: <&infracfg_ao CLK_INFRA_AO_GCE> is for gce0,
<&infracfg_ao CLK_INFRA_AO_GCE2> is for gce1.
For the design of GCE hardware event signal transportation, each cmdq
mailbox should enable or disable the other gce clk at the same time.
I put two clock source in one gce node so that I can get both of them
easier when each cmdq driver probe.
But I think take out the other gce clk for each gce node is fine.
I will modify it at the next patch version.
Regards,
Jason-JH.Lin.
--
Jason-JH Lin <[email protected]>