2022-01-25 09:11:00

by Anup Patel

Subject: [PATCH 0/6] RISC-V IPI Improvements

This series aims to improve IPI support in Linux RISC-V in following ways:
1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V
specific hooks. This also makes Linux RISC-V IPI support aligned with
other architectures.
2) Remote TLB flushes and icache flushes should prefer local IPIs instead
of SBI calls whenever we have specialized hardware (such as RISC-V AIA
IMSIC and RISC-V ACLINT) which allows S-mode software to directly inject
IPIs without any assistance from M-mode runtime firmware.

These patches were already part of the "Linux RISC-V ACLINT Support" series
but this now a separate series so that it can be merged independently of
the "Linux RISC-V ACLINT Support" series.
(Refer, https://lore.kernel.org/lkml/[email protected]/)

These patches are also a preparatory patches for the up-coming:
1) Linux RISC-V ACLINT support
2) Linux RISC-V AIA support
3) KVM RISC-V TLB flush improvements

These patches can also be found in riscv_ipi_imp_v1 branch at:
https://github.com/avpatel/linux.git

Anup Patel (6):
RISC-V: Clear SIP bit only when using SBI IPI operations
irqchip/riscv-intc: Set intc domain as the default host
RISC-V: Treat IPIs as normal Linux IRQs
RISC-V: Allow marking IPIs as suitable for remote FENCEs
RISC-V: Use IPIs for remote TLB flush when possible
RISC-V: Use IPIs for remote icache flush when possible

arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/ipi-mux.h | 45 +++++++
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/include/asm/smp.h | 49 +++++--
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/cpu-hotplug.c | 3 +-
arch/riscv/kernel/ipi-mux.c | 217 ++++++++++++++++++++++++++++++
arch/riscv/kernel/irq.c | 3 +-
arch/riscv/kernel/sbi.c | 18 ++-
arch/riscv/kernel/smp.c | 164 +++++++++++-----------
arch/riscv/kernel/smpboot.c | 5 +-
arch/riscv/mm/cacheflush.c | 5 +-
arch/riscv/mm/tlbflush.c | 93 ++++++++++---
drivers/clocksource/timer-clint.c | 8 +-
drivers/clocksource/timer-riscv.c | 17 +--
drivers/irqchip/irq-riscv-intc.c | 62 ++++-----
16 files changed, 521 insertions(+), 172 deletions(-)
create mode 100644 arch/riscv/include/asm/ipi-mux.h
create mode 100644 arch/riscv/kernel/ipi-mux.c

--
2.25.1

2022-01-25 09:11:12

by Anup Patel

Subject: [PATCH 5/6] RISC-V: Use IPIs for remote TLB flush when possible

If IPI calls are injected using SBI IPI calls then remote TLB flush
using SBI RFENCE calls is much faster because using IPIs for remote
TLB flush would still endup as SBI IPI calls with extra processing
on kernel side.

It is now possible to have specialized hardware (such as RISC-V AIA
and RISC-V ACLINT) which allows S-mode software to directly inject
IPIs without any assistance from M-mode runtime firmware.

This patch extends remote TLB flush functions to use IPIs whenever
underlying IPI operations are suitable for remote FENCEs.

Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++-------
1 file changed, 78 insertions(+), 15 deletions(-)

diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 37ed760d007c..27a7db8eb2c4 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
: "memory");
}

+static inline void local_flush_tlb_range(unsigned long start,
+ unsigned long size, unsigned long stride)
+{
+ if (size <= stride)
+ local_flush_tlb_page(start);
+ else
+ local_flush_tlb_all();
+}
+
+static inline void local_flush_tlb_range_asid(unsigned long start,
+ unsigned long size, unsigned long stride, unsigned long asid)
+{
+ if (size <= stride)
+ local_flush_tlb_page_asid(start, asid);
+ else
+ local_flush_tlb_all_asid(asid);
+}
+
+static void __ipi_flush_tlb_all(void *info)
+{
+ local_flush_tlb_all();
+}
+
void flush_tlb_all(void)
{
- sbi_remote_sfence_vma(NULL, 0, -1);
+ if (riscv_use_ipi_for_rfence())
+ on_each_cpu(__ipi_flush_tlb_all, NULL, 1);
+ else
+ sbi_remote_sfence_vma(NULL, 0, -1);
+}
+
+struct flush_tlb_range_data {
+ unsigned long asid;
+ unsigned long start;
+ unsigned long size;
+ unsigned long stride;
+};
+
+static void __ipi_flush_tlb_range_asid(void *info)
+{
+ struct flush_tlb_range_data *d = info;
+
+ local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
+}
+
+static void __ipi_flush_tlb_range(void *info)
+{
+ struct flush_tlb_range_data *d = info;
+
+ local_flush_tlb_range(d->start, d->size, d->stride);
}

-static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
- unsigned long size, unsigned long stride)
+static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
+ unsigned long size, unsigned long stride)
{
+ struct flush_tlb_range_data ftd;
struct cpumask *cmask = mm_cpumask(mm);
unsigned int cpuid;
bool broadcast;
@@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
unsigned long asid = atomic_long_read(&mm->context.id);

if (broadcast) {
- sbi_remote_sfence_vma_asid(cmask, start, size, asid);
- } else if (size <= stride) {
- local_flush_tlb_page_asid(start, asid);
+ if (riscv_use_ipi_for_rfence()) {
+ ftd.asid = asid;
+ ftd.start = start;
+ ftd.size = size;
+ ftd.stride = stride;
+ on_each_cpu_mask(cmask,
+ __ipi_flush_tlb_range_asid,
+ &ftd, 1);
+ } else
+ sbi_remote_sfence_vma_asid(cmask,
+ start, size, asid);
} else {
- local_flush_tlb_all_asid(asid);
+ local_flush_tlb_range_asid(start, size, stride, asid);
}
} else {
if (broadcast) {
- sbi_remote_sfence_vma(cmask, start, size);
- } else if (size <= stride) {
- local_flush_tlb_page(start);
+ if (riscv_use_ipi_for_rfence()) {
+ ftd.asid = 0;
+ ftd.start = start;
+ ftd.size = size;
+ ftd.stride = stride;
+ on_each_cpu_mask(cmask,
+ __ipi_flush_tlb_range,
+ &ftd, 1);
+ } else
+ sbi_remote_sfence_vma(cmask, start, size);
} else {
- local_flush_tlb_all();
+ local_flush_tlb_range(start, size, stride);
}
}

@@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,

void flush_tlb_mm(struct mm_struct *mm)
{
- __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE);
+ __flush_tlb_range(mm, 0, -1, PAGE_SIZE);
}

void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
- __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
+ __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
}

void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
- __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE);
+ __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE);
}
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
- __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE);
+ __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE);
}
#endif
--
2.25.1

2022-01-25 09:11:13

by Anup Patel

Subject: [PATCH 6/6] RISC-V: Use IPIs for remote icache flush when possible

If IPI calls are injected using SBI IPI calls then remote icache flush
using SBI RFENCE calls is much faster because using IPIs for remote
icache flush would still endup as SBI IPI calls with extra processing
on the kernel side.

It is now possible to have specialized hardware (such as RISC-V AIA
and RISC-V ACLINT) which allows S-mode software to directly inject
IPIs without any assistance from M-mode runtime firmware.

This patch extends remote icache flush functions to use IPIs whenever
underlying IPI operations are suitable for remote FENCEs.

Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/mm/cacheflush.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..7c7e44aaf791 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -18,7 +18,7 @@ void flush_icache_all(void)
{
local_flush_icache_all();

- if (IS_ENABLED(CONFIG_RISCV_SBI))
+ if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence())
sbi_remote_fence_i(NULL);
else
on_each_cpu(ipi_remote_fence_i, NULL, 1);
@@ -66,7 +66,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local)
* with flush_icache_deferred().
*/
smp_mb();
- } else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
+ } else if (IS_ENABLED(CONFIG_RISCV_SBI) &&
+ !riscv_use_ipi_for_rfence()) {
sbi_remote_fence_i(&others);
} else {
on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
--
2.25.1

2022-01-25 09:11:40

by Anup Patel

Subject: [PATCH 3/6] RISC-V: Treat IPIs as normal Linux IRQs

Currently, the RISC-V kernel provides arch specific hooks (i.e.
struct riscv_ipi_ops) to register IPI handling methods. The stats
gathering of IPIs is also arch specific in the RISC-V kernel.

Other architectures (such as ARM, ARM64, and MIPS) have moved away
from custom arch specific IPI handling methods. Currently, these
architectures have Linux irqchip drivers providing a range of Linux
IRQ numbers to be used as IPIs and IPI triggering is done using
generic IPI APIs. This approach allows architectures to treat IPIs
as normal Linux IRQs and IPI stats gathering is done by the generic
Linux IRQ subsystem.

We extend the RISC-V IPI handling as-per above approach so that
arch specific IPI handling methods (struct riscv_ipi_ops) can be
removed and the IPI handling is totally contained within Linux
irqchip drivers.

Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/ipi-mux.h | 43 ++++++
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/include/asm/smp.h | 35 +++--
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/cpu-hotplug.c | 3 +-
arch/riscv/kernel/ipi-mux.c | 216 ++++++++++++++++++++++++++++++
arch/riscv/kernel/irq.c | 3 +-
arch/riscv/kernel/sbi.c | 13 +-
arch/riscv/kernel/smp.c | 153 +++++++++++----------
arch/riscv/kernel/smpboot.c | 5 +-
drivers/clocksource/timer-clint.c | 8 +-
drivers/irqchip/irq-riscv-intc.c | 55 ++++----
13 files changed, 399 insertions(+), 139 deletions(-)
create mode 100644 arch/riscv/include/asm/ipi-mux.h
create mode 100644 arch/riscv/kernel/ipi-mux.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 5adcbd9b5e88..167681d6d3f8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -54,6 +54,7 @@ config RISCV
select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO
select GENERIC_IDLE_POLL_SETUP
select GENERIC_IOREMAP if MMU
+ select GENERIC_IRQ_IPI
select GENERIC_IRQ_MULTI_HANDLER
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-mux.h
new file mode 100644
index 000000000000..988e2bba372a
--- /dev/null
+++ b/arch/riscv/include/asm/ipi-mux.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#ifndef _ASM_RISCV_IPI_MUX_H
+#define _ASM_RISCV_IPI_MUX_H
+
+struct cpumask;
+
+#ifdef CONFIG_SMP
+
+/* Handle muxed IPIs */
+void riscv_ipi_mux_handle_irq(void);
+
+/* Create irq_domain for muxed IPIs */
+struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq,
+ void (*clear_ipi)(void),
+ void (*send_ipi)(const struct cpumask *mask));
+
+/* Destroy irq_domain for muxed IPIs */
+void riscv_ipi_mux_destroy(struct irq_domain *d);
+
+#else
+
+static inline void riscv_ipi_mux_handle_irq(void)
+{
+}
+
+static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq,
+ void (*clear_ipi)(void),
+ void (*send_ipi)(const struct cpumask *mask))
+{
+ return NULL;
+}
+
+static inline void riscv_ipi_mux_destroy(struct irq_domain *d)
+{
+}
+
+#endif
+
+#endif /* _ASM_RISCV_IPI_MUX_H */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index d1c37479d828..1e9aa7941960 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -116,6 +116,7 @@ struct sbiret {
};

void sbi_init(void);
+void sbi_ipi_init(void);
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4,
@@ -185,6 +186,7 @@ static inline unsigned long sbi_mk_version(unsigned long major,
int sbi_err_map_linux_errno(int err);
#else /* CONFIG_RISCV_SBI */
static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
+static inline void sbi_ipi_init(void) { }
static inline void sbi_init(void) {}
#endif /* CONFIG_RISCV_SBI */
#endif /* _ASM_RISCV_SBI_H */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 23170c933d73..178fe4ada592 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -15,11 +15,6 @@
struct seq_file;
extern unsigned long boot_cpu_hartid;

-struct riscv_ipi_ops {
- void (*ipi_inject)(const struct cpumask *target);
- void (*ipi_clear)(void);
-};
-
#ifdef CONFIG_SMP
/*
* Mapping between linux logical cpu index and hartid.
@@ -33,9 +28,6 @@ void show_ipi_stats(struct seq_file *p, int prec);
/* SMP initialization hook for setup_arch */
void __init setup_smp(void);

-/* Called from C code, this handles an IPI. */
-void handle_IPI(struct pt_regs *regs);
-
/* Hook for the generic smp_call_function_many() routine. */
void arch_send_call_function_ipi_mask(struct cpumask *mask);

@@ -44,11 +36,17 @@ void arch_send_call_function_single_ipi(int cpu);

int riscv_hartid_to_cpuid(int hartid);

-/* Set custom IPI operations */
-void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops);
+/* Enable IPI for CPU hotplug */
+void riscv_ipi_enable(void);
+
+/* Disable IPI for CPU hotplug */
+void riscv_ipi_disable(void);

-/* Clear IPI for current CPU */
-void riscv_clear_ipi(void);
+/* Check if IPI interrupt numbers are available */
+bool riscv_ipi_have_virq_range(void);
+
+/* Set the IPI interrupt numbers for arch (called by irqchip drivers) */
+void riscv_ipi_set_virq_range(int virq, int nr_irqs);

/* Secondary hart entry */
asmlinkage void smp_callin(void);
@@ -82,11 +80,20 @@ static inline unsigned long cpuid_to_hartid_map(int cpu)
return boot_cpu_hartid;
}

-static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
+static inline void riscv_ipi_enable(void)
{
}

-static inline void riscv_clear_ipi(void)
+static inline void riscv_ipi_disable(void)
+{
+}
+
+static inline bool riscv_ipi_have_virq_range(void)
+{
+ return false;
+}
+
+static inline void riscv_ipi_set_virq_range(int virq, int nr)
{
}

diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 612556faa527..e3cd63a8709a 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
obj-$(CONFIG_FPU) += fpu.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SMP) += ipi-mux.o
obj-$(CONFIG_SMP) += cpu_ops.o

obj-$(CONFIG_RISCV_BOOT_SPINWAIT) += cpu_ops_spinwait.o
diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplug.c
index be7f05b542bb..d375bfeb08df 100644
--- a/arch/riscv/kernel/cpu-hotplug.c
+++ b/arch/riscv/kernel/cpu-hotplug.c
@@ -12,7 +12,7 @@
#include <linux/sched/hotplug.h>
#include <asm/irq.h>
#include <asm/cpu_ops.h>
-#include <asm/sbi.h>
+#include <asm/smp.h>

bool cpu_has_hotplug(unsigned int cpu)
{
@@ -41,6 +41,7 @@ int __cpu_disable(void)

remove_cpu_topology(cpu);
set_cpu_online(cpu, false);
+ riscv_ipi_disable();
irq_migrate_all_off_this_cpu();

return ret;
diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c
new file mode 100644
index 000000000000..e24bdeded489
--- /dev/null
+++ b/arch/riscv/kernel/ipi-mux.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Multiplex several IPIs over a single HW IPI.
+ *
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#define pr_fmt(fmt) "riscv-ipi-mux: " fmt
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/smp.h>
+#include <asm/ipi-mux.h>
+
+struct ipi_mux {
+ struct irq_domain *domain;
+ int parent_virq;
+ void (*clear_ipi)(void);
+ void (*send_ipi)(const struct cpumask *mask);
+};
+
+static struct ipi_mux ipi_mux_priv;
+static DEFINE_PER_CPU(unsigned long, ipi_mux_bits);
+
+static void ipi_mux_dummy(struct irq_data *d)
+{
+}
+
+static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *mask)
+{
+ int cpu;
+
+ /* Barrier before doing atomic bit update to IPI bits */
+ smp_mb__before_atomic();
+
+ for_each_cpu(cpu, mask)
+ set_bit(d->hwirq, per_cpu_ptr(&ipi_mux_bits, cpu));
+
+ /* Barrier after doing atomic bit update to IPI bits */
+ smp_mb__after_atomic();
+
+ if (ipi_mux_priv.send_ipi)
+ ipi_mux_priv.send_ipi(mask);
+}
+
+static struct irq_chip ipi_mux_chip = {
+ .name = "RISC-V IPI Mux",
+ .irq_mask = ipi_mux_dummy,
+ .irq_unmask = ipi_mux_dummy,
+ .ipi_send_mask = ipi_mux_send_mask,
+};
+
+static int ipi_mux_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_percpu_devid(irq);
+ irq_domain_set_info(d, irq, hwirq, &ipi_mux_chip, d->host_data,
+ handle_percpu_devid_irq, NULL, NULL);
+
+ return 0;
+}
+
+static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq;
+ unsigned int type = IRQ_TYPE_NONE;
+ struct irq_fwspec *fwspec = arg;
+
+ ret = irq_domain_translate_onecell(d, fwspec, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ ret = ipi_mux_domain_map(d, virq + i, hwirq + i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops ipi_mux_domain_ops = {
+ .translate = irq_domain_translate_onecell,
+ .alloc = ipi_mux_domain_alloc,
+ .free = irq_domain_free_irqs_top,
+};
+
+void riscv_ipi_mux_handle_irq(void)
+{
+ int err;
+ unsigned long irqs, *bits = this_cpu_ptr(&ipi_mux_bits);
+ irq_hw_number_t hwirq;
+
+ while (true) {
+ /* Order bit clearing and data access. */
+ mb();
+
+ irqs = xchg(bits, 0);
+ if (!irqs)
+ break;
+
+ for_each_set_bit(hwirq, &irqs, BITS_PER_LONG) {
+ err = generic_handle_domain_irq(ipi_mux_priv.domain,
+ hwirq);
+ if (unlikely(err))
+ pr_warn_ratelimited(
+ "can't find mapping for hwirq %lu\n",
+ hwirq);
+ }
+ }
+}
+
+static void ipi_mux_handle_irq(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ chained_irq_enter(chip, desc);
+
+ if (ipi_mux_priv.clear_ipi)
+ ipi_mux_priv.clear_ipi();
+ riscv_ipi_mux_handle_irq();
+
+ chained_irq_exit(chip, desc);
+}
+
+static int ipi_mux_dying_cpu(unsigned int cpu)
+{
+ if (ipi_mux_priv.parent_virq)
+ disable_percpu_irq(ipi_mux_priv.parent_virq);
+ return 0;
+}
+
+static int ipi_mux_starting_cpu(unsigned int cpu)
+{
+ if (ipi_mux_priv.parent_virq)
+ enable_percpu_irq(ipi_mux_priv.parent_virq,
+ irq_get_trigger_type(ipi_mux_priv.parent_virq));
+ return 0;
+}
+
+struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq,
+ void (*clear_ipi)(void),
+ void (*send_ipi)(const struct cpumask *mask))
+{
+ int virq, parent_virq = 0;
+ struct irq_domain *domain;
+ struct irq_fwspec ipi;
+
+ if (ipi_mux_priv.domain || riscv_ipi_have_virq_range())
+ return NULL;
+
+ if (use_soft_irq) {
+ parent_virq = irq_create_mapping(NULL, RV_IRQ_SOFT);
+ if (!parent_virq) {
+ pr_err("unable to create INTC IRQ mapping\n");
+ return NULL;
+ }
+ }
+
+ domain = irq_domain_add_linear(NULL, BITS_PER_LONG,
+ &ipi_mux_domain_ops, NULL);
+ if (!domain) {
+ pr_err("unable to add IPI Mux domain\n");
+ goto fail_dispose_mapping;
+ }
+
+ ipi.fwnode = domain->fwnode;
+ ipi.param_count = 1;
+ ipi.param[0] = 0;
+ virq = __irq_domain_alloc_irqs(domain, -1, BITS_PER_LONG,
+ NUMA_NO_NODE, &ipi, false, NULL);
+ if (virq <= 0) {
+ pr_err("unable to alloc IRQs from IPI Mux domain\n");
+ goto fail_domain_remove;
+ }
+
+ ipi_mux_priv.domain = domain;
+ ipi_mux_priv.parent_virq = parent_virq;
+ ipi_mux_priv.clear_ipi = clear_ipi;
+ ipi_mux_priv.send_ipi = send_ipi;
+
+ if (parent_virq)
+ irq_set_chained_handler(parent_virq, ipi_mux_handle_irq);
+
+ cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+ "irqchip/riscv/ipi-mux:starting",
+ ipi_mux_starting_cpu, ipi_mux_dying_cpu);
+
+ riscv_ipi_set_virq_range(virq, BITS_PER_LONG);
+
+ return ipi_mux_priv.domain;
+
+fail_domain_remove:
+ irq_domain_remove(domain);
+fail_dispose_mapping:
+ if (parent_virq)
+ irq_dispose_mapping(parent_virq);
+ return NULL;
+}
+
+void riscv_ipi_mux_destroy(struct irq_domain *d)
+{
+ if (!d || ipi_mux_priv.domain != d)
+ return;
+
+ irq_domain_remove(ipi_mux_priv.domain);
+ if (ipi_mux_priv.parent_virq)
+ irq_dispose_mapping(ipi_mux_priv.parent_virq);
+ memset(&ipi_mux_priv, 0, sizeof(ipi_mux_priv));
+}
diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 7207fa08d78f..a179350d2208 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -8,7 +8,7 @@
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/seq_file.h>
-#include <asm/smp.h>
+#include <asm/sbi.h>

int arch_show_interrupts(struct seq_file *p, int prec)
{
@@ -21,4 +21,5 @@ void __init init_IRQ(void)
irqchip_init();
if (!handle_arch_irq)
panic("No interrupt controller found.");
+ sbi_ipi_init();
}
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 9786fc641436..fa3d92fce9f8 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -5,9 +5,11 @@
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*/

+#define pr_fmt(fmt) "riscv: " fmt
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/reboot.h>
+#include <asm/ipi-mux.h>
#include <asm/sbi.h>
#include <asm/smp.h>

@@ -626,10 +628,11 @@ static void sbi_ipi_clear(void)
csr_clear(CSR_IP, IE_SIE);
}

-static const struct riscv_ipi_ops sbi_ipi_ops = {
- .ipi_inject = sbi_send_cpumask_ipi,
- .ipi_clear = sbi_ipi_clear
-};
+void __init sbi_ipi_init(void)
+{
+ if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi))
+ pr_info("providing IPIs using SBI IPI extension\n");
+}

void __init sbi_init(void)
{
@@ -677,6 +680,4 @@ void __init sbi_init(void)
__sbi_send_ipi = __sbi_send_ipi_v01;
__sbi_rfence = __sbi_rfence_v01;
}
-
- riscv_set_ipi_ops(&sbi_ipi_ops);
}
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 6fd8b3cbec1b..a9f1aca38358 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -17,9 +17,9 @@
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <linux/delay.h>
+#include <linux/irq.h>
#include <linux/irq_work.h>

-#include <asm/sbi.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>

@@ -41,11 +41,9 @@ void __init smp_setup_processor_id(void)
cpuid_to_hartid_map(0) = boot_cpu_hartid;
}

-/* A collection of single bit ipi messages. */
-static struct {
- unsigned long stats[IPI_MAX] ____cacheline_aligned;
- unsigned long bits ____cacheline_aligned;
-} ipi_data[NR_CPUS] __cacheline_aligned;
+static int ipi_virq_base __ro_after_init;
+static int nr_ipi __ro_after_init = IPI_MAX;
+static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly;

int riscv_hartid_to_cpuid(int hartid)
{
@@ -77,46 +75,14 @@ static void ipi_stop(void)
wait_for_interrupt();
}

-static const struct riscv_ipi_ops *ipi_ops __ro_after_init;
-
-void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
-{
- ipi_ops = ops;
-}
-EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
-
-void riscv_clear_ipi(void)
-{
- if (ipi_ops && ipi_ops->ipi_clear)
- ipi_ops->ipi_clear();
-}
-EXPORT_SYMBOL_GPL(riscv_clear_ipi);
-
static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
{
- int cpu;
-
- smp_mb__before_atomic();
- for_each_cpu(cpu, mask)
- set_bit(op, &ipi_data[cpu].bits);
- smp_mb__after_atomic();
-
- if (ipi_ops && ipi_ops->ipi_inject)
- ipi_ops->ipi_inject(mask);
- else
- pr_warn("SMP: IPI inject method not available\n");
+ __ipi_send_mask(ipi_desc[op], mask);
}

static void send_ipi_single(int cpu, enum ipi_message_type op)
{
- smp_mb__before_atomic();
- set_bit(op, &ipi_data[cpu].bits);
- smp_mb__after_atomic();
-
- if (ipi_ops && ipi_ops->ipi_inject)
- ipi_ops->ipi_inject(cpumask_of(cpu));
- else
- pr_warn("SMP: IPI inject method not available\n");
+ __ipi_send_mask(ipi_desc[op], cpumask_of(cpu));
}

#ifdef CONFIG_IRQ_WORK
@@ -126,55 +92,88 @@ void arch_irq_work_raise(void)
}
#endif

-void handle_IPI(struct pt_regs *regs)
+static irqreturn_t handle_IPI(int irq, void *data)
+{
+ int ipi = irq - ipi_virq_base;
+
+ switch (ipi) {
+ case IPI_RESCHEDULE:
+ scheduler_ipi();
+ break;
+ case IPI_CALL_FUNC:
+ generic_smp_call_function_interrupt();
+ break;
+ case IPI_CPU_STOP:
+ ipi_stop();
+ break;
+ case IPI_IRQ_WORK:
+ irq_work_run();
+ break;
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+ case IPI_TIMER:
+ tick_receive_broadcast();
+ break;
+#endif
+ default:
+ pr_warn("CPU%d: unhandled IPI%d\n", smp_processor_id(), ipi);
+ break;
+ };
+
+ return IRQ_HANDLED;
+}
+
+void riscv_ipi_enable(void)
{
- unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
- unsigned long *stats = ipi_data[smp_processor_id()].stats;
+ int i;

- riscv_clear_ipi();
+ if (WARN_ON_ONCE(!ipi_virq_base))
+ return;

- while (true) {
- unsigned long ops;
+ for (i = 0; i < nr_ipi; i++)
+ enable_percpu_irq(ipi_virq_base + i, 0);
+}

- /* Order bit clearing and data access. */
- mb();
+void riscv_ipi_disable(void)
+{
+ int i;

- ops = xchg(pending_ipis, 0);
- if (ops == 0)
- return;
+ if (WARN_ON_ONCE(!ipi_virq_base))
+ return;

- if (ops & (1 << IPI_RESCHEDULE)) {
- stats[IPI_RESCHEDULE]++;
- scheduler_ipi();
- }
+ for (i = 0; i < nr_ipi; i++)
+ disable_percpu_irq(ipi_virq_base + i);
+}

- if (ops & (1 << IPI_CALL_FUNC)) {
- stats[IPI_CALL_FUNC]++;
- generic_smp_call_function_interrupt();
- }
+bool riscv_ipi_have_virq_range(void)
+{
+ return (ipi_virq_base) ? true : false;
+}

- if (ops & (1 << IPI_CPU_STOP)) {
- stats[IPI_CPU_STOP]++;
- ipi_stop();
- }
+void riscv_ipi_set_virq_range(int virq, int nr)
+{
+ int i, err;

- if (ops & (1 << IPI_IRQ_WORK)) {
- stats[IPI_IRQ_WORK]++;
- irq_work_run();
- }
+ if (WARN_ON(ipi_virq_base))
+ return;

-#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
- if (ops & (1 << IPI_TIMER)) {
- stats[IPI_TIMER]++;
- tick_receive_broadcast();
- }
-#endif
- BUG_ON((ops >> IPI_MAX) != 0);
+ WARN_ON(nr < IPI_MAX);
+ nr_ipi = min(nr, IPI_MAX);
+ ipi_virq_base = virq;
+
+ /* Request IPIs */
+ for (i = 0; i < nr_ipi; i++) {
+ err = request_percpu_irq(ipi_virq_base + i, handle_IPI,
+ "IPI", &ipi_virq_base);
+ WARN_ON(err);

- /* Order data access and bit testing. */
- mb();
+ ipi_desc[i] = irq_to_desc(ipi_virq_base + i);
+ irq_set_status_flags(ipi_virq_base + i, IRQ_HIDDEN);
}
+
+ /* Enabled IPIs for boot CPU immediately */
+ riscv_ipi_enable();
}
+EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range);

static const char * const ipi_names[] = {
[IPI_RESCHEDULE] = "Rescheduling interrupts",
@@ -192,7 +191,7 @@ void show_ipi_stats(struct seq_file *p, int prec)
seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
prec >= 4 ? " " : "");
for_each_online_cpu(cpu)
- seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]);
+ seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu));
seq_printf(p, " %s\n", ipi_names[i]);
}
}
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 622f226454d5..e37036e779bb 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -30,7 +30,6 @@
#include <asm/numa.h>
#include <asm/tlbflush.h>
#include <asm/sections.h>
-#include <asm/sbi.h>
#include <asm/smp.h>
#include <asm/alternative.h>

@@ -159,12 +158,12 @@ asmlinkage __visible void smp_callin(void)
struct mm_struct *mm = &init_mm;
unsigned int curr_cpuid = smp_processor_id();

- riscv_clear_ipi();
-
/* All kernel threads share the same mm context. */
mmgrab(mm);
current->active_mm = mm;

+ riscv_ipi_enable();
+
notify_cpu_starting(curr_cpuid);
numa_add_cpu(curr_cpuid);
update_siblings_masks(curr_cpuid);
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 6cfe2ab73eb0..b05a9e946633 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -20,6 +20,7 @@
#include <linux/of_irq.h>
#include <linux/smp.h>
#include <linux/timex.h>
+#include <asm/ipi-mux.h>

#ifndef CONFIG_RISCV_M_MODE
#include <asm/clint.h>
@@ -54,11 +55,6 @@ static void clint_clear_ipi(void)
writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
}

-static struct riscv_ipi_ops clint_ipi_ops = {
- .ipi_inject = clint_send_ipi,
- .ipi_clear = clint_clear_ipi,
-};
-
#ifdef CONFIG_64BIT
#define clint_get_cycles() readq_relaxed(clint_timer_val)
#else
@@ -228,7 +224,7 @@ static int __init clint_timer_init_dt(struct device_node *np)
goto fail_free_irq;
}

- riscv_set_ipi_ops(&clint_ipi_ops);
+ riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi);
clint_clear_ipi();

return 0;
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 9f0a7a8a5c4d..2c737e388479 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -26,20 +26,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
if (unlikely(cause >= BITS_PER_LONG))
panic("unexpected interrupt cause");

- switch (cause) {
-#ifdef CONFIG_SMP
- case RV_IRQ_SOFT:
- /*
- * We only use software interrupts to pass IPIs, so if a
- * non-SMP system gets one, then we don't know what to do.
- */
- handle_IPI(regs);
- break;
-#endif
- default:
- generic_handle_domain_irq(intc_domain, cause);
- break;
- }
+ generic_handle_domain_irq(intc_domain, cause);
}

/*
@@ -59,18 +46,6 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}

-static int riscv_intc_cpu_starting(unsigned int cpu)
-{
- csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
- return 0;
-}
-
-static int riscv_intc_cpu_dying(unsigned int cpu)
-{
- csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
- return 0;
-}
-
static struct irq_chip riscv_intc_chip = {
.name = "RISC-V INTC",
.irq_mask = riscv_intc_irq_mask,
@@ -87,9 +62,32 @@ static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
return 0;
}

+static int riscv_intc_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs,
+ void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq;
+ unsigned int type = IRQ_TYPE_NONE;
+ struct irq_fwspec *fwspec = arg;
+
+ ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static const struct irq_domain_ops riscv_intc_domain_ops = {
.map = riscv_intc_domain_map,
.xlate = irq_domain_xlate_onecell,
+ .alloc = riscv_intc_domain_alloc
};

static int __init riscv_intc_init(struct device_node *node,
@@ -134,11 +132,6 @@ static int __init riscv_intc_init(struct device_node *node,
*/
irq_set_default_host(intc_domain);

- cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
- "irqchip/riscv/intc:starting",
- riscv_intc_cpu_starting,
- riscv_intc_cpu_dying);
-
pr_info("%d local interrupts mapped\n", BITS_PER_LONG);

return 0;
--
2.25.1

2022-01-25 09:12:17

by Anup Patel

Subject: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
dedicated DT/ACPI fwnode. This patch makes intc domain as the default
host so that these drivers can directly create local interrupt mapping
using standardized local interrupt numbers

Signed-off-by: Anup Patel <[email protected]>
---
drivers/clocksource/timer-riscv.c | 17 +----------------
drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
2 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 1767f8bf2013..dd6916ae6365 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
static int __init riscv_timer_init_dt(struct device_node *n)
{
int cpuid, hartid, error;
- struct device_node *child;
- struct irq_domain *domain;

hartid = riscv_of_processor_hartid(n);
if (hartid < 0) {
@@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
if (cpuid != smp_processor_id())
return 0;

- domain = NULL;
- child = of_get_compatible_child(n, "riscv,cpu-intc");
- if (!child) {
- pr_err("Failed to find INTC node [%pOF]\n", n);
- return -ENODEV;
- }
- domain = irq_find_host(child);
- of_node_put(child);
- if (!domain) {
- pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
- return -ENODEV;
- }
-
- riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
+ riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
if (!riscv_clock_event_irq) {
pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
return -ENODEV;
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index b65bd8878d4f..9f0a7a8a5c4d 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
return rc;
}

+ /*
+ * Make INTC as the default domain which will allow drivers
+ * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
+ * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
+ * directly create local interrupt mapping using standardized
+ * local interrupt numbers.
+ */
+ irq_set_default_host(intc_domain);
+
cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
"irqchip/riscv/intc:starting",
riscv_intc_cpu_starting,
--
2.25.1

2022-01-26 03:26:39

by Marc Zyngier

Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

On Tue, 25 Jan 2022 05:42:13 +0000,
Anup Patel <[email protected]> wrote:
>
> We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
> RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
> dedicated DT/ACPI fwnode. This patch makes intc domain as the default
> host so that these drivers can directly create local interrupt mapping
> using standardized local interrupt numbers
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> drivers/clocksource/timer-riscv.c | 17 +----------------
> drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
> 2 files changed, 10 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 1767f8bf2013..dd6916ae6365 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> static int __init riscv_timer_init_dt(struct device_node *n)
> {
> int cpuid, hartid, error;
> - struct device_node *child;
> - struct irq_domain *domain;
>
> hartid = riscv_of_processor_hartid(n);
> if (hartid < 0) {
> @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (cpuid != smp_processor_id())
> return 0;
>
> - domain = NULL;
> - child = of_get_compatible_child(n, "riscv,cpu-intc");
> - if (!child) {
> - pr_err("Failed to find INTC node [%pOF]\n", n);
> - return -ENODEV;
> - }
> - domain = irq_find_host(child);
> - of_node_put(child);
> - if (!domain) {
> - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> - return -ENODEV;
> - }
> -
> - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
> if (!riscv_clock_event_irq) {
> pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> return -ENODEV;
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index b65bd8878d4f..9f0a7a8a5c4d 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
> return rc;
> }
>
> + /*
> + * Make INTC as the default domain which will allow drivers
> + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
> + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
> + * directly create local interrupt mapping using standardized
> + * local interrupt numbers.
> + */
> + irq_set_default_host(intc_domain);

No, please. This really is a bad idea. This sort of catch-all have
constantly proven to be a nuisance, because they discard all the
topology information. Eventually, you realise that you need to know
where this is coming from, but it really is too late.

I'd rather you *synthesise* a fwnode (like ACPI does) rather then do
this.

M.

--
Without deviation from the norm, progress is not possible.

2022-01-26 17:15:51

by Anup Patel

Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

On Tue, Jan 25, 2022 at 11:47 PM Marc Zyngier <[email protected]> wrote:
>
> On Tue, 25 Jan 2022 05:42:13 +0000,
> Anup Patel <[email protected]> wrote:
> >
> > We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
> > RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
> > dedicated DT/ACPI fwnode. This patch makes intc domain as the default
> > host so that these drivers can directly create local interrupt mapping
> > using standardized local interrupt numbers
> >
> > Signed-off-by: Anup Patel <[email protected]>
> > ---
> > drivers/clocksource/timer-riscv.c | 17 +----------------
> > drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
> > 2 files changed, 10 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > index 1767f8bf2013..dd6916ae6365 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> > static int __init riscv_timer_init_dt(struct device_node *n)
> > {
> > int cpuid, hartid, error;
> > - struct device_node *child;
> > - struct irq_domain *domain;
> >
> > hartid = riscv_of_processor_hartid(n);
> > if (hartid < 0) {
> > @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > if (cpuid != smp_processor_id())
> > return 0;
> >
> > - domain = NULL;
> > - child = of_get_compatible_child(n, "riscv,cpu-intc");
> > - if (!child) {
> > - pr_err("Failed to find INTC node [%pOF]\n", n);
> > - return -ENODEV;
> > - }
> > - domain = irq_find_host(child);
> > - of_node_put(child);
> > - if (!domain) {
> > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> > - return -ENODEV;
> > - }
> > -
> > - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> > + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
> > if (!riscv_clock_event_irq) {
> > pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> > return -ENODEV;
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index b65bd8878d4f..9f0a7a8a5c4d 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
> > return rc;
> > }
> >
> > + /*
> > + * Make INTC as the default domain which will allow drivers
> > + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
> > + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
> > + * directly create local interrupt mapping using standardized
> > + * local interrupt numbers.
> > + */
> > + irq_set_default_host(intc_domain);
>
> No, please. This really is a bad idea. This sort of catch-all have
> constantly proven to be a nuisance, because they discard all the
> topology information. Eventually, you realise that you need to know
> where this is coming from, but it really is too late.
>
> I'd rather you *synthesise* a fwnode (like ACPI does) rather then do
> this.

In absence of INTC as the default domain, currently we have various
drivers looking up INTC irq_domain from DT (or ACPI). This is quite a
bit of duplicate code across various drivers.

How about having a irq_domain lookup routine (riscv_intc_find_irq_domain())
exported by the RISC-V INTC driver or arch/riscv ?
OR
Do you have an alternative suggestion ?

Regards,
Anup

>
> M.
>
> --
> Without deviation from the norm, progress is not possible.

2022-01-26 20:37:39

by Marc Zyngier

Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

On Wed, 26 Jan 2022 03:16:55 +0000,
Anup Patel <[email protected]> wrote:
>
> On Tue, Jan 25, 2022 at 11:47 PM Marc Zyngier <[email protected]> wrote:
> >
> > On Tue, 25 Jan 2022 05:42:13 +0000,
> > Anup Patel <[email protected]> wrote:
> > >
> > > We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
> > > RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
> > > dedicated DT/ACPI fwnode. This patch makes intc domain as the default
> > > host so that these drivers can directly create local interrupt mapping
> > > using standardized local interrupt numbers
> > >
> > > Signed-off-by: Anup Patel <[email protected]>
> > > ---
> > > drivers/clocksource/timer-riscv.c | 17 +----------------
> > > drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
> > > 2 files changed, 10 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > > index 1767f8bf2013..dd6916ae6365 100644
> > > --- a/drivers/clocksource/timer-riscv.c
> > > +++ b/drivers/clocksource/timer-riscv.c
> > > @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> > > static int __init riscv_timer_init_dt(struct device_node *n)
> > > {
> > > int cpuid, hartid, error;
> > > - struct device_node *child;
> > > - struct irq_domain *domain;
> > >
> > > hartid = riscv_of_processor_hartid(n);
> > > if (hartid < 0) {
> > > @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > > if (cpuid != smp_processor_id())
> > > return 0;
> > >
> > > - domain = NULL;
> > > - child = of_get_compatible_child(n, "riscv,cpu-intc");
> > > - if (!child) {
> > > - pr_err("Failed to find INTC node [%pOF]\n", n);
> > > - return -ENODEV;
> > > - }
> > > - domain = irq_find_host(child);
> > > - of_node_put(child);
> > > - if (!domain) {
> > > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> > > - return -ENODEV;
> > > - }
> > > -
> > > - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> > > + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
> > > if (!riscv_clock_event_irq) {
> > > pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> > > return -ENODEV;
> > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > > index b65bd8878d4f..9f0a7a8a5c4d 100644
> > > --- a/drivers/irqchip/irq-riscv-intc.c
> > > +++ b/drivers/irqchip/irq-riscv-intc.c
> > > @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
> > > return rc;
> > > }
> > >
> > > + /*
> > > + * Make INTC as the default domain which will allow drivers
> > > + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
> > > + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
> > > + * directly create local interrupt mapping using standardized
> > > + * local interrupt numbers.
> > > + */
> > > + irq_set_default_host(intc_domain);
> >
> > No, please. This really is a bad idea. This sort of catch-all have
> > constantly proven to be a nuisance, because they discard all the
> > topology information. Eventually, you realise that you need to know
> > where this is coming from, but it really is too late.
> >
> > I'd rather you *synthesise* a fwnode (like ACPI does) rather then do
> > this.
>
> In absence of INTC as the default domain, currently we have various
> drivers looking up INTC irq_domain from DT (or ACPI). This is quite a
> bit of duplicate code across various drivers.
>
> How about having a irq_domain lookup routine (riscv_intc_find_irq_domain())
> exported by the RISC-V INTC driver or arch/riscv ?
> OR
> Do you have an alternative suggestion ?

But *why* don't you provide an interrupt controller node for DT? I
really don't think that's outlandish to require.

For ACPI, we already have an interface that allows a fwnode to be
registered (acpi_set_irq_model) and interrupts mapped
(acpi_register_gsi).

You should already have all the required tools you need.

M.

--
Without deviation from the norm, progress is not possible.

2022-01-26 20:58:23

by Anup Patel

Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

On Wed, Jan 26, 2022 at 2:31 PM Marc Zyngier <[email protected]> wrote:
>
> On Wed, 26 Jan 2022 03:16:55 +0000,
> Anup Patel <[email protected]> wrote:
> >
> > On Tue, Jan 25, 2022 at 11:47 PM Marc Zyngier <[email protected]> wrote:
> > >
> > > On Tue, 25 Jan 2022 05:42:13 +0000,
> > > Anup Patel <[email protected]> wrote:
> > > >
> > > > We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
> > > > RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
> > > > dedicated DT/ACPI fwnode. This patch makes intc domain as the default
> > > > host so that these drivers can directly create local interrupt mapping
> > > > using standardized local interrupt numbers
> > > >
> > > > Signed-off-by: Anup Patel <[email protected]>
> > > > ---
> > > > drivers/clocksource/timer-riscv.c | 17 +----------------
> > > > drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
> > > > 2 files changed, 10 insertions(+), 16 deletions(-)
> > > >
> > > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > > > index 1767f8bf2013..dd6916ae6365 100644
> > > > --- a/drivers/clocksource/timer-riscv.c
> > > > +++ b/drivers/clocksource/timer-riscv.c
> > > > @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> > > > static int __init riscv_timer_init_dt(struct device_node *n)
> > > > {
> > > > int cpuid, hartid, error;
> > > > - struct device_node *child;
> > > > - struct irq_domain *domain;
> > > >
> > > > hartid = riscv_of_processor_hartid(n);
> > > > if (hartid < 0) {
> > > > @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > > > if (cpuid != smp_processor_id())
> > > > return 0;
> > > >
> > > > - domain = NULL;
> > > > - child = of_get_compatible_child(n, "riscv,cpu-intc");
> > > > - if (!child) {
> > > > - pr_err("Failed to find INTC node [%pOF]\n", n);
> > > > - return -ENODEV;
> > > > - }
> > > > - domain = irq_find_host(child);
> > > > - of_node_put(child);
> > > > - if (!domain) {
> > > > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> > > > - return -ENODEV;
> > > > - }
> > > > -
> > > > - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> > > > + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
> > > > if (!riscv_clock_event_irq) {
> > > > pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> > > > return -ENODEV;
> > > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > > > index b65bd8878d4f..9f0a7a8a5c4d 100644
> > > > --- a/drivers/irqchip/irq-riscv-intc.c
> > > > +++ b/drivers/irqchip/irq-riscv-intc.c
> > > > @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
> > > > return rc;
> > > > }
> > > >
> > > > + /*
> > > > + * Make INTC as the default domain which will allow drivers
> > > > + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
> > > > + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
> > > > + * directly create local interrupt mapping using standardized
> > > > + * local interrupt numbers.
> > > > + */
> > > > + irq_set_default_host(intc_domain);
> > >
> > > No, please. This really is a bad idea. This sort of catch-all have
> > > constantly proven to be a nuisance, because they discard all the
> > > topology information. Eventually, you realise that you need to know
> > > where this is coming from, but it really is too late.
> > >
> > > I'd rather you *synthesise* a fwnode (like ACPI does) rather then do
> > > this.
> >
> > In absence of INTC as the default domain, currently we have various
> > drivers looking up INTC irq_domain from DT (or ACPI). This is quite a
> > bit of duplicate code across various drivers.
> >
> > How about having a irq_domain lookup routine (riscv_intc_find_irq_domain())
> > exported by the RISC-V INTC driver or arch/riscv ?
> > OR
> > Do you have an alternative suggestion ?
>
> But *why* don't you provide an interrupt controller node for DT? I
> really don't think that's outlandish to require.

Historically, all RISC-V SBI related drivers never had any DT/ACPI
node because we can always query/discover the SBI functionality
at runtime.

The mechanism to query/discover SBI IPI, Timer and PMU is
through SBI base functions. Also, local interrupts used by these
drivers are specified by the RISC-V specification. This means having
a DT/ACPI node for these drivers doesn't provide any info.

We will be having KVM RISC-V AIA support in future which will not
have a DT/ACPI node as well because this can be discovered as a
CPU capability and the local interrupt to be used is specified by the
RISC-V hypervisor specification.

>
> For ACPI, we already have an interface that allows a fwnode to be
> registered (acpi_set_irq_model) and interrupts mapped
> (acpi_register_gsi).

The ACPI specification being proposed for RISC-V does not have
any details for SBI IPI, Timer, and PMU for the same reasons
mentioned above.

>
> You should already have all the required tools you need.

Are you okay if arch/riscv exports riscv_intc_find_irq_domain() ?
OR
Maybe export riscv_intc_find_irq_domain() from INTC driver ?

Regards,
Anup


>
> M.
>
> --
> Without deviation from the norm, progress is not possible.

2022-01-26 21:05:14

by Marc Zyngier

Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

On Wed, 26 Jan 2022 10:12:25 +0000,
Anup Patel <[email protected]> wrote:
>
> On Wed, Jan 26, 2022 at 2:31 PM Marc Zyngier <[email protected]> wrote:
> >
> > On Wed, 26 Jan 2022 03:16:55 +0000,
> > Anup Patel <[email protected]> wrote:
> > >
> > > On Tue, Jan 25, 2022 at 11:47 PM Marc Zyngier <[email protected]> wrote:
> > > >
> > > > On Tue, 25 Jan 2022 05:42:13 +0000,
> > > > Anup Patel <[email protected]> wrote:
> > > > >
> > > > > We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
> > > > > RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
> > > > > dedicated DT/ACPI fwnode. This patch makes intc domain as the default
> > > > > host so that these drivers can directly create local interrupt mapping
> > > > > using standardized local interrupt numbers
> > > > >
> > > > > Signed-off-by: Anup Patel <[email protected]>
> > > > > ---
> > > > > drivers/clocksource/timer-riscv.c | 17 +----------------
> > > > > drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
> > > > > 2 files changed, 10 insertions(+), 16 deletions(-)
> > > > >
> > > > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > > > > index 1767f8bf2013..dd6916ae6365 100644
> > > > > --- a/drivers/clocksource/timer-riscv.c
> > > > > +++ b/drivers/clocksource/timer-riscv.c
> > > > > @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> > > > > static int __init riscv_timer_init_dt(struct device_node *n)
> > > > > {
> > > > > int cpuid, hartid, error;
> > > > > - struct device_node *child;
> > > > > - struct irq_domain *domain;
> > > > >
> > > > > hartid = riscv_of_processor_hartid(n);
> > > > > if (hartid < 0) {
> > > > > @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > > > > if (cpuid != smp_processor_id())
> > > > > return 0;
> > > > >
> > > > > - domain = NULL;
> > > > > - child = of_get_compatible_child(n, "riscv,cpu-intc");
> > > > > - if (!child) {
> > > > > - pr_err("Failed to find INTC node [%pOF]\n", n);
> > > > > - return -ENODEV;
> > > > > - }
> > > > > - domain = irq_find_host(child);
> > > > > - of_node_put(child);
> > > > > - if (!domain) {
> > > > > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> > > > > - return -ENODEV;
> > > > > - }
> > > > > -
> > > > > - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> > > > > + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
> > > > > if (!riscv_clock_event_irq) {
> > > > > pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> > > > > return -ENODEV;
> > > > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > > > > index b65bd8878d4f..9f0a7a8a5c4d 100644
> > > > > --- a/drivers/irqchip/irq-riscv-intc.c
> > > > > +++ b/drivers/irqchip/irq-riscv-intc.c
> > > > > @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
> > > > > return rc;
> > > > > }
> > > > >
> > > > > + /*
> > > > > + * Make INTC as the default domain which will allow drivers
> > > > > + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
> > > > > + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
> > > > > + * directly create local interrupt mapping using standardized
> > > > > + * local interrupt numbers.
> > > > > + */
> > > > > + irq_set_default_host(intc_domain);
> > > >
> > > > No, please. This really is a bad idea. This sort of catch-all have
> > > > constantly proven to be a nuisance, because they discard all the
> > > > topology information. Eventually, you realise that you need to know
> > > > where this is coming from, but it really is too late.
> > > >
> > > > I'd rather you *synthesise* a fwnode (like ACPI does) rather then do
> > > > this.
> > >
> > > In absence of INTC as the default domain, currently we have various
> > > drivers looking up INTC irq_domain from DT (or ACPI). This is quite a
> > > bit of duplicate code across various drivers.
> > >
> > > How about having a irq_domain lookup routine (riscv_intc_find_irq_domain())
> > > exported by the RISC-V INTC driver or arch/riscv ?
> > > OR
> > > Do you have an alternative suggestion ?
> >
> > But *why* don't you provide an interrupt controller node for DT? I
> > really don't think that's outlandish to require.
>
> Historically, all RISC-V SBI related drivers never had any DT/ACPI
> node because we can always query/discover the SBI functionality
> at runtime.
>
> The mechanism to query/discover SBI IPI, Timer and PMU is
> through SBI base functions. Also, local interrupts used by these
> drivers are specified by the RISC-V specification. This means having
> a DT/ACPI node for these drivers doesn't provide any info.
>
> We will be having KVM RISC-V AIA support in future which will not
> have a DT/ACPI node as well because this can be discovered as a
> CPU capability and the local interrupt to be used is specified by the
> RISC-V hypervisor specification.
>
> >
> > For ACPI, we already have an interface that allows a fwnode to be
> > registered (acpi_set_irq_model) and interrupts mapped
> > (acpi_register_gsi).
>
> The ACPI specification being proposed for RISC-V does not have
> any details for SBI IPI, Timer, and PMU for the same reasons
> mentioned above.

Neither does it on the other architectures.

And yet we are able to synthesise fwnodes and use the whole of the
infrastructure as intended without having to resort to this crap that
was only introduced to cope with 20 year old PPC board files.

Only dead architectures are using irq_set_default_host().

>
> >
> > You should already have all the required tools you need.
>
> Are you okay if arch/riscv exports riscv_intc_find_irq_domain() ?
> OR
> Maybe export riscv_intc_find_irq_domain() from INTC driver ?

Neither. That's just papering over the core problem.

Either you start creating fwnodes out of thin air, which is what we do
for both x86 and arm64 when using ACPI, or you add support for SBI (or
whatever new spec the RISC-V people come up with) as a provider of
fwnodes.

Anything else looks like a pretty bad regression.

Thanks,

M.

--
Without deviation from the norm, progress is not possible.

2022-01-26 22:08:42

by Anup Patel

Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host

On Wed, Jan 26, 2022 at 4:17 PM Marc Zyngier <[email protected]> wrote:
>
> On Wed, 26 Jan 2022 10:12:25 +0000,
> Anup Patel <[email protected]> wrote:
> >
> > On Wed, Jan 26, 2022 at 2:31 PM Marc Zyngier <[email protected]> wrote:
> > >
> > > On Wed, 26 Jan 2022 03:16:55 +0000,
> > > Anup Patel <[email protected]> wrote:
> > > >
> > > > On Tue, Jan 25, 2022 at 11:47 PM Marc Zyngier <[email protected]> wrote:
> > > > >
> > > > > On Tue, 25 Jan 2022 05:42:13 +0000,
> > > > > Anup Patel <[email protected]> wrote:
> > > > > >
> > > > > > We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver,
> > > > > > RISC-V timer driver, RISC-V PMU driver, etc) which do not have a
> > > > > > dedicated DT/ACPI fwnode. This patch makes intc domain as the default
> > > > > > host so that these drivers can directly create local interrupt mapping
> > > > > > using standardized local interrupt numbers
> > > > > >
> > > > > > Signed-off-by: Anup Patel <[email protected]>
> > > > > > ---
> > > > > > drivers/clocksource/timer-riscv.c | 17 +----------------
> > > > > > drivers/irqchip/irq-riscv-intc.c | 9 +++++++++
> > > > > > 2 files changed, 10 insertions(+), 16 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > > > > > index 1767f8bf2013..dd6916ae6365 100644
> > > > > > --- a/drivers/clocksource/timer-riscv.c
> > > > > > +++ b/drivers/clocksource/timer-riscv.c
> > > > > > @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> > > > > > static int __init riscv_timer_init_dt(struct device_node *n)
> > > > > > {
> > > > > > int cpuid, hartid, error;
> > > > > > - struct device_node *child;
> > > > > > - struct irq_domain *domain;
> > > > > >
> > > > > > hartid = riscv_of_processor_hartid(n);
> > > > > > if (hartid < 0) {
> > > > > > @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > > > > > if (cpuid != smp_processor_id())
> > > > > > return 0;
> > > > > >
> > > > > > - domain = NULL;
> > > > > > - child = of_get_compatible_child(n, "riscv,cpu-intc");
> > > > > > - if (!child) {
> > > > > > - pr_err("Failed to find INTC node [%pOF]\n", n);
> > > > > > - return -ENODEV;
> > > > > > - }
> > > > > > - domain = irq_find_host(child);
> > > > > > - of_node_put(child);
> > > > > > - if (!domain) {
> > > > > > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> > > > > > - return -ENODEV;
> > > > > > - }
> > > > > > -
> > > > > > - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> > > > > > + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER);
> > > > > > if (!riscv_clock_event_irq) {
> > > > > > pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> > > > > > return -ENODEV;
> > > > > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > > > > > index b65bd8878d4f..9f0a7a8a5c4d 100644
> > > > > > --- a/drivers/irqchip/irq-riscv-intc.c
> > > > > > +++ b/drivers/irqchip/irq-riscv-intc.c
> > > > > > @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node,
> > > > > > return rc;
> > > > > > }
> > > > > >
> > > > > > + /*
> > > > > > + * Make INTC as the default domain which will allow drivers
> > > > > > + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI
> > > > > > + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can
> > > > > > + * directly create local interrupt mapping using standardized
> > > > > > + * local interrupt numbers.
> > > > > > + */
> > > > > > + irq_set_default_host(intc_domain);
> > > > >
> > > > > No, please. This really is a bad idea. This sort of catch-all have
> > > > > constantly proven to be a nuisance, because they discard all the
> > > > > topology information. Eventually, you realise that you need to know
> > > > > where this is coming from, but it really is too late.
> > > > >
> > > > > I'd rather you *synthesise* a fwnode (like ACPI does) rather then do
> > > > > this.
> > > >
> > > > In absence of INTC as the default domain, currently we have various
> > > > drivers looking up INTC irq_domain from DT (or ACPI). This is quite a
> > > > bit of duplicate code across various drivers.
> > > >
> > > > How about having a irq_domain lookup routine (riscv_intc_find_irq_domain())
> > > > exported by the RISC-V INTC driver or arch/riscv ?
> > > > OR
> > > > Do you have an alternative suggestion ?
> > >
> > > But *why* don't you provide an interrupt controller node for DT? I
> > > really don't think that's outlandish to require.
> >
> > Historically, all RISC-V SBI related drivers never had any DT/ACPI
> > node because we can always query/discover the SBI functionality
> > at runtime.
> >
> > The mechanism to query/discover SBI IPI, Timer and PMU is
> > through SBI base functions. Also, local interrupts used by these
> > drivers are specified by the RISC-V specification. This means having
> > a DT/ACPI node for these drivers doesn't provide any info.
> >
> > We will be having KVM RISC-V AIA support in future which will not
> > have a DT/ACPI node as well because this can be discovered as a
> > CPU capability and the local interrupt to be used is specified by the
> > RISC-V hypervisor specification.
> >
> > >
> > > For ACPI, we already have an interface that allows a fwnode to be
> > > registered (acpi_set_irq_model) and interrupts mapped
> > > (acpi_register_gsi).
> >
> > The ACPI specification being proposed for RISC-V does not have
> > any details for SBI IPI, Timer, and PMU for the same reasons
> > mentioned above.
>
> Neither does it on the other architectures.
>
> And yet we are able to synthesise fwnodes and use the whole of the
> infrastructure as intended without having to resort to this crap that
> was only introduced to cope with 20 year old PPC board files.
>
> Only dead architectures are using irq_set_default_host().

Okay, I will drop the idea of using irq_set_default_host() in INTC driver.

>
> >
> > >
> > > You should already have all the required tools you need.
> >
> > Are you okay if arch/riscv exports riscv_intc_find_irq_domain() ?
> > OR
> > Maybe export riscv_intc_find_irq_domain() from INTC driver ?
>
> Neither. That's just papering over the core problem.
>
> Either you start creating fwnodes out of thin air, which is what we do
> for both x86 and arm64 when using ACPI, or you add support for SBI (or
> whatever new spec the RISC-V people come up with) as a provider of
> fwnodes.
>
> Anything else looks like a pretty bad regression.

Actually, SBI spec has been used for quite a few years in RISC-V now.
It can be compared with the ARM PSCI spec so it's not a HW description
format like DT or ACPI.

How about arch/riscv creating an exported riscv_intc_fwnode ?
(This riscv_intc_fwnode can be used by various drivers to obtain
the INTC irq_domain)

Regards,
Anup

>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.