2021-03-17 08:27:36

by Zihao Yu

Subject: [PATCH] riscv,entry: fix misaligned base for excp_vect_table

* In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <[email protected]>
---
arch/riscv/kernel/entry.S | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 744f3209c..76274a4a1 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -447,6 +447,7 @@ ENDPROC(__switch_to)
#endif

.section ".rodata"
+ .align LGREG
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned
--
2.20.1

2021-03-17 08:32:47

by Anup Patel

Subject: Re: [PATCH] riscv,entry: fix misaligned base for excp_vect_table

On Wed, Mar 17, 2021 at 1:48 PM Zihao Yu <[email protected]> wrote:
>
> * In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
> base of the table is not 8-byte aligned, loading an entry in the table
> will raise a misaligned exception. Although such exception will be
> handled by opensbi/bbl, this still causes performance degradation.
>
> Signed-off-by: Zihao Yu <[email protected]>

Looks good to me.

Reviewed-by: Anup Patel <[email protected]>

Regards,
Anup

> ---
> arch/riscv/kernel/entry.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 744f3209c..76274a4a1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -447,6 +447,7 @@ ENDPROC(__switch_to)
> #endif
>
> .section ".rodata"
> + .align LGREG
> /* Exception vector table */
> ENTRY(excp_vect_table)
> RISCV_PTR do_trap_insn_misaligned
> --
> 2.20.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

2021-03-30 05:56:02

by Palmer Dabbelt

Subject: Re: [PATCH] riscv,entry: fix misaligned base for excp_vect_table

On Wed, 17 Mar 2021 01:17:25 PDT (-0700), [email protected] wrote:
> * In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
> base of the table is not 8-byte aligned, loading an entry in the table
> will raise a misaligned exception. Although such exception will be
> handled by opensbi/bbl, this still causes performance degradation.
>
> Signed-off-by: Zihao Yu <[email protected]>
> ---
> arch/riscv/kernel/entry.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 744f3209c..76274a4a1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -447,6 +447,7 @@ ENDPROC(__switch_to)
> #endif
>
> .section ".rodata"
> + .align LGREG
> /* Exception vector table */
> ENTRY(excp_vect_table)
> RISCV_PTR do_trap_insn_misaligned

Thanks, this is on fixes.