From: Bartosz Golaszewski <[email protected]>
Update relevant DT bindings, add new config to the driver and add UFS
and PHY nodes to the .dtsi and enable them in the board .dts for
sa8775p-ride.
v1 -> v2:
- order new compatibles alphabetically
- rework the UFS PHY bindings to accomodate more clocks
- add a comment in the .dts regarding a non-standard clock used
by the UFS PHY
Bartosz Golaszewski (5):
dt-bindings: ufs: qcom: add compatible for sa8775p
dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
arm64: dts: qcom: sa8775p: add UFS nodes
arm64: dts: qcom: sa8775p-ride: enable UFS
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++-
.../devicetree/bindings/ufs/qcom,ufs.yaml | 2 +
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 ++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 ++++++++++++
5 files changed, 142 insertions(+), 1 deletion(-)
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add the compatible string for the UFS on sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index c5a06c048389..b1c00424c2b0 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,msm8994-ufshc
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
+ - qcom,sa8775p-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
@@ -105,6 +106,7 @@ allOf:
contains:
enum:
- qcom,msm8998-ufshc
+ - qcom,sa8775p-ufshc
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add a new compatible for the QMP UFS PHY found on sa8775p platforms and
update the clocks property to accommodate three clocks.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index cd0fbbd3593d..5bc93acccbad 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
+ - qcom,sa8775p-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sm6125-qmp-ufs-phy
- qcom,sm7150-qmp-ufs-phy
@@ -25,12 +26,15 @@ properties:
maxItems: 1
clocks:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
clock-names:
+ minItems: 2
items:
- const: ref
- const: ref_aux
+ - const: qref
power-domains:
maxItems: 1
@@ -52,6 +56,26 @@ properties:
"#phy-cells":
const: 0
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
+ else:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+
required:
- compatible
- reg
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add QMP PHY config for sa8775p and add support for the new compatible.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 +++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index d58822049211..5612282eb378 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -853,6 +853,41 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.no_pcs_sw_reset = true,
};
+
+static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets,
+
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sm8350_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .tx = sm8350_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
+ .rx = sm8350_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
+ .pcs = sm8350_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ },
+ .clk_list = sm8450_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = ufsphy_v5_regs_layout,
+};
+
static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
@@ -1600,6 +1635,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
}, {
.compatible = "qcom,msm8998-qmp-ufs-phy",
.data = &sdm845_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sa8775p-qmp-ufs-phy",
+ .data = &sa8775p_ufsphy_cfg,
}, {
.compatible = "qcom,sc8180x-qmp-ufs-phy",
.data = &sm8150_ufsphy_cfg,
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add nodes for the UFS and its PHY on sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 2343df7e0ea4..5de0fbbe9752 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -585,6 +585,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
};
};
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+ iommus = <&apps_smmu 0x100 0x0>;
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ freq-table-hz = <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sa8775p-qmp-ufs-phy";
+ reg = <0x0 0x01d87000 0x0 0xe10>;
+ /*
+ * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
+ * enables the CXO clock to eDP *and* UFS PHY.
+ */
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "ref", "ref_aux", "qref";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Enable the UFS and its PHY on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index f238a02a5448..2bb001a3ea55 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sa8775p.dtsi"
@@ -20,6 +21,7 @@ aliases {
serial2 = &uart17;
i2c18 = &i2c18;
spi16 = &spi16;
+ ufshc1 = &ufs_mem_hc;
};
chosen {
@@ -426,6 +428,23 @@ &uart17 {
status = "okay";
};
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l8a>;
+ vcc-max-microamp = <1100000>;
+ vccq-supply = <&vreg_l4c>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4a>;
+ vdda-pll-supply = <&vreg_l1c>;
+
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
--
2.37.2
On 6.04.2023 21:47, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add nodes for the UFS and its PHY on sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 2343df7e0ea4..5de0fbbe9752 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -585,6 +585,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>
> + ufs_mem_hc: ufs@1d84000 {
> + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> + power-domains = <&gcc UFS_PHY_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> + iommus = <&apps_smmu 0x100 0x0>;
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + freq-table-hz = <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> + status = "disabled";
> + };
> +
> + ufs_mem_phy: phy@1d87000 {
> + compatible = "qcom,sa8775p-qmp-ufs-phy";
> + reg = <0x0 0x01d87000 0x0 0xe10>;
> + /*
> + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
> + * enables the CXO clock to eDP *and* UFS PHY.
> + */
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&gcc GCC_EDP_REF_CLKREF_EN>;
> + clock-names = "ref", "ref_aux", "qref";
> + power-domains = <&gcc UFS_PHY_GDSC>;
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x20000>;
On 06/04/2023 21:46, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the compatible string for the UFS on sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 06/04/2023 21:47, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add a new compatible for the QMP UFS PHY found on sa8775p platforms and
> update the clocks property to accommodate three clocks.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> index cd0fbbd3593d..5bc93acccbad 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> @@ -16,6 +16,7 @@ description:
> properties:
> compatible:
> enum:
> + - qcom,sa8775p-qmp-ufs-phy
> - qcom,sc8280xp-qmp-ufs-phy
> - qcom,sm6125-qmp-ufs-phy
> - qcom,sm7150-qmp-ufs-phy
> @@ -25,12 +26,15 @@ properties:
> maxItems: 1
>
> clocks:
> - maxItems: 2
> + minItems: 2
> + maxItems: 3
>
> clock-names:
> + minItems: 2
> items:
> - const: ref
> - const: ref_aux
> + - const: qref
>
> power-domains:
> maxItems: 1
> @@ -52,6 +56,26 @@ properties:
> "#phy-cells":
> const: 0
>
> +allOf:
I should notice wrong different placement before.
allOf: blocks goes just like in example-schema, so after required:.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-qmp-ufs-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + maxItems: 3
> + else:
> + properties:
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> +
> required:
> - compatible
> - reg
Best regards,
Krzysztof
On Thu, Apr 06, 2023 at 09:47:00PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add a new compatible for the QMP UFS PHY found on sa8775p platforms and
> update the clocks property to accommodate three clocks.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> index cd0fbbd3593d..5bc93acccbad 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> @@ -16,6 +16,7 @@ description:
> properties:
> compatible:
> enum:
> + - qcom,sa8775p-qmp-ufs-phy
> - qcom,sc8280xp-qmp-ufs-phy
> - qcom,sm6125-qmp-ufs-phy
> - qcom,sm7150-qmp-ufs-phy
> @@ -25,12 +26,15 @@ properties:
> maxItems: 1
>
> clocks:
> - maxItems: 2
> + minItems: 2
> + maxItems: 3
>
> clock-names:
> + minItems: 2
> items:
> - const: ref
> - const: ref_aux
> + - const: qref
>
> power-domains:
> maxItems: 1
> @@ -52,6 +56,26 @@ properties:
> "#phy-cells":
> const: 0
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-qmp-ufs-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + maxItems: 3
The max is already 3. Did you mean 'minItems: 3' or 2 or 3 clocks are
valid?
> + else:
> + properties:
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> +
> required:
> - compatible
> - reg
> --
> 2.37.2
>
On Tue, 11 Apr 2023 at 15:17, Rob Herring <[email protected]> wrote:
>
> On Thu, Apr 06, 2023 at 09:47:00PM +0200, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <[email protected]>
> >
> > Add a new compatible for the QMP UFS PHY found on sa8775p platforms and
> > update the clocks property to accommodate three clocks.
> >
> > Signed-off-by: Bartosz Golaszewski <[email protected]>
> > ---
> > .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++++++++++++-
> > 1 file changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> > index cd0fbbd3593d..5bc93acccbad 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
> > @@ -16,6 +16,7 @@ description:
> > properties:
> > compatible:
> > enum:
> > + - qcom,sa8775p-qmp-ufs-phy
> > - qcom,sc8280xp-qmp-ufs-phy
> > - qcom,sm6125-qmp-ufs-phy
> > - qcom,sm7150-qmp-ufs-phy
> > @@ -25,12 +26,15 @@ properties:
> > maxItems: 1
> >
> > clocks:
> > - maxItems: 2
> > + minItems: 2
> > + maxItems: 3
> >
> > clock-names:
> > + minItems: 2
> > items:
> > - const: ref
> > - const: ref_aux
> > + - const: qref
> >
> > power-domains:
> > maxItems: 1
> > @@ -52,6 +56,26 @@ properties:
> > "#phy-cells":
> > const: 0
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sa8775p-qmp-ufs-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 3
> > + clock-names:
> > + maxItems: 3
>
> The max is already 3. Did you mean 'minItems: 3' or 2 or 3 clocks are
> valid?
>
For this compatible only 3 clocks are valid so it should have been
minItems indeed.
Bartosz
> > + else:
> > + properties:
> > + clocks:
> > + maxItems: 2
> > + clock-names:
> > + maxItems: 2
> > +
> > required:
> > - compatible
> > - reg
> > --
> > 2.37.2
> >