From: Balsam CHIHI <[email protected]>
On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
This is the original patch series proposed by Fabien Parent <[email protected]>.
"https://lore.kernel.org/linux-arm-kernel/[email protected]/"
Changelog:
Changes in v2 :
- Rebase on top of 6.1.0-rc1-next-20221020
- Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
- Add mt8365_set_clr_mode() callback
Changes in v1 :
- "https://lore.kernel.org/linux-arm-kernel/[email protected]/"
Balsam CHIHI (2):
pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for
broken SET/CLR modes
pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback
drivers/pinctrl/mediatek/pinctrl-mt8365.c | 18 ++++++++++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +++++++-
3 files changed, 40 insertions(+), 1 deletion(-)
--
2.34.1
Hi Balsam,
[email protected] writes:
> From: Balsam CHIHI <[email protected]>
>
> On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
>
> This is the original patch series proposed by Fabien Parent <[email protected]>.
> "https://lore.kernel.org/linux-arm-kernel/[email protected]/"
>
> Changelog:
> Changes in v2 :
> - Rebase on top of 6.1.0-rc1-next-20221020
> - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> - Add mt8365_set_clr_mode() callback
nit: subject of cover letter should also include "pinctrl: mediatek:"
prefix. Also note that you're missing the word "PATCH" in all of the
subjects.
Tip: If you use `git format-patch`, you can just pass `-v2` on the
cmdline and it will create the prefixes for you automatically.
Kevin
On Mon, Oct 31, 2022 at 5:40 PM Kevin Hilman <[email protected]> wrote:
>
> Hi Balsam,
>
>
> [email protected] writes:
>
> > From: Balsam CHIHI <[email protected]>
> >
> > On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> > To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> > This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
> >
> > This is the original patch series proposed by Fabien Parent <[email protected]>.
> > "https://lore.kernel.org/linux-arm-kernel/[email protected]/"
> >
> > Changelog:
> > Changes in v2 :
> > - Rebase on top of 6.1.0-rc1-next-20221020
> > - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> > - Add mt8365_set_clr_mode() callback
>
> nit: subject of cover letter should also include "pinctrl: mediatek:"
> prefix. Also note that you're missing the word "PATCH" in all of the
> subjects.
>
> Tip: If you use `git format-patch`, you can just pass `-v2` on the
> cmdline and it will create the prefixes for you automatically.
>
Hi Kevin,
Well received.
I will fix these issues in the next version/resend.
Thank you so much for the review!
Balsam.
> Kevin
On Fri, Oct 21, 2022 at 10:47 AM <[email protected]> wrote:
> From: Balsam CHIHI <[email protected]>
>
> On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
>
> This is the original patch series proposed by Fabien Parent <[email protected]>.
> "https://lore.kernel.org/linux-arm-kernel/[email protected]/"
>
> Changelog:
> Changes in v2 :
> - Rebase on top of 6.1.0-rc1-next-20221020
> - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> - Add mt8365_set_clr_mode() callback
Patches applied, no need to resend for small issues.
Sorry for taking so long, I wanted some feedback from the Mediatek
maintainers but haven't heard anything, so I just applied them.
Yours,
Linus Walleij
On Mon, Nov 7, 2022 at 3:44 PM Linus Walleij <[email protected]> wrote:
>
> On Fri, Oct 21, 2022 at 10:47 AM <[email protected]> wrote:
>
> > From: Balsam CHIHI <[email protected]>
> >
> > On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> > To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> > This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
> >
> > This is the original patch series proposed by Fabien Parent <[email protected]>.
> > "https://lore.kernel.org/linux-arm-kernel/[email protected]/"
> >
> > Changelog:
> > Changes in v2 :
> > - Rebase on top of 6.1.0-rc1-next-20221020
> > - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> > - Add mt8365_set_clr_mode() callback
>
> Patches applied, no need to resend for small issues.
>
> Sorry for taking so long, I wanted some feedback from the Mediatek
> maintainers but haven't heard anything, so I just applied them.
>
Hi Linus,
I'm sorry for the delay.
Thank you very much.
Best regards,
Balsam.
> Yours,
> Linus Walleij