Hello,
This is v4 of series which adds further support for A83T, mainly adds clock
support.Also adds R_PIO, PRCM related clocks, mmc, rsb support.
A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.
These patches are based on Maxime's sunxi/for-next branch.
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/
v3->v4 Changes:
1. Removed MODULE_DEVICE_TABLE, module.h and made A83T R_PIO as
builtin_platform_driver.
2. Corrected config to MACH_SUN8I in clk/sunxi/Kconfig.
3. Corrected style related errors.
v2->v3 Changes:
1. Corrected wrong configuration of uart0 and timer in dtsi.
2. corrected clock gate name of "spdif" in dtsi.
3. Added kconfig for sunxi clocks, added sun8i-apb0 and sun9i-cpus clocks to it.
v1->v2 Changes:
1. Patches for apb0 gates clock, bus gates, low speed oscillators are already
merged, so, not included again in this series.
1. sorted the R_PIO Kconfig options.
2. removed un-necessary a83t apb1 div table.
3. combined the three ahb reset registers into one reset node.
4. Changed the bus gates names to bus_spidf and bus_usb_otg.
5. removed un-necessary #address-cells and #size-cells from R_PIO node.
6. splited rsb pins and rsb controller nodes in different patches.
7. used PF6 as mmc0 CD reference design pin.
8. corrected the style related errors.
Patch 1: adds support for r_pio pin controller.
patch 2: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.
patch 3: adds apb1 clock support, apb1 has different dividers compared to a10
apb0 clock.
patch 4: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.
patch 5-6: adds mmc and it's clock nodes.
patch 7: adds A83T PRCM related clocks, clock resets.
patch 8: adds r_pio pin controller nodes to dtsi
patch 9: adds RSB controller nodes to dtsi
patch 10: adds common MMC CD detect pin as reference design pin
patch 11: enables mmc0 support for h8homlet board, tested by LABBE Corentin.
patch 12: This patch adds support for Sinovoip BPI-M3 A83T based board, it has
2GB LPDDR3, u-boot support is added recently for this board.
patch 13: Adds kconfig for clocks(sun8i-apb0 and sun9i-cpus).
Vishnu Patekar (13):
pinctrl: sunxi: Add A83T R_PIO controller
clk: sunxi: add ahb1 clock for A83T
clk: sunxi: Add APB1 clock for A83T
ARM: dts: sun8i-a83t: Add basic clocks and resets
ARM: dts: sun8i-a83t: add mmc clock nodes
ARM: dts: sun8i-a83t: Add mmc controller nodes
ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi
ARM: dts: sun8i-a83t: add mmc0 CD pin
ARM: dts: sun8i: enable mmc for H8Homlet Board.
ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board
ARM: sunxi: Add Kconfig for sunxi clocks
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +
...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} | 21 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 285 ++++++++++++++++++++-
drivers/clk/Kconfig | 1 +
drivers/clk/sunxi/Kconfig | 5 +
drivers/clk/sunxi/Makefile | 4 +-
drivers/clk/sunxi/clk-sunxi.c | 89 +++++++
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c | 117 +++++++++
13 files changed, 536 insertions(+), 7 deletions(-)
copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} (83%)
create mode 100644 drivers/clk/sunxi/Kconfig
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
--
1.9.1
AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 834436f..cba9fe55 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -30,6 +30,7 @@ Required properties:
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+ "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 91de0a0..a7aab65 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
req->rate >>= req->p;
}
+#define SUN8I_A83T_AHB1_PARENT_PLL6 2
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+ u8 div, calcp, calcm = 1;
+
+ /*
+ * clock can only divide, so we will never be able to achieve
+ * frequencies higher than the parent frequency
+ */
+ if (req->parent_rate && req->rate > req->parent_rate)
+ req->rate = req->parent_rate;
+
+ div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+ /* calculate pre-divider if parent is pll6 */
+ if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+ if (div < 4)
+ calcp = 0;
+ else if (div / 2 < 4)
+ calcp = 1;
+ else if (div / 4 < 4)
+ calcp = 2;
+ else
+ calcp = 3;
+
+ calcm = DIV_ROUND_UP(div, 1 << calcp);
+ } else {
+ calcp = __roundup_pow_of_two(div);
+ calcp = calcp > 3 ? 3 : calcp;
+ }
+
+ req->rate = (req->parent_rate / calcm) >> calcp;
+ req->p = calcp;
+ req->m = calcm - 1;
+}
+
+/**
+* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+* parent index
+*/
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+ req->rate = req->parent_rate;
+
+/* apply pre-divider first if parent is pll6 */
+ if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+ req->rate /= req->m + 1;
+
+ /* clk divider */
+ req->rate >>= req->p;
+}
+
/**
* sun4i_get_apb1_factors() - calculates m, p factors for APB1
* APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data __initconst = {
.recalc = sun6i_ahb1_recalc,
};
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+ .mux = 12,
+ .muxmask = BIT(1) | BIT(0),
+ .table = &sun6i_ahb1_config,
+ .getter = sun8i_a83t_get_ahb1_factors,
+ .recalc = sun8i_a83t_ahb1_recalc,
+};
+
static const struct factors_data sun4i_apb1_data __initconst = {
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -627,6 +696,13 @@ static void __init sun6i_ahb1_clk_setup(struct device_node *node)
CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
sun6i_ahb1_clk_setup);
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+ sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+ sun8i_a83t_ahb1_clk_setup);
+
static void __init sun4i_apb1_clk_setup(struct device_node *node)
{
sunxi_factors_clk_setup(node, &sun4i_apb1_data);
--
1.9.1
APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
This adds support for apb1 on A83T.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index cba9fe55..291d366 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -51,6 +51,7 @@ Required properties:
"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
++ "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index a7aab65..171282d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -872,6 +872,12 @@ static const struct div_data sun4i_apb0_data __initconst = {
.table = sun4i_apb0_table,
};
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+ .shift = 8,
+ .pow = 0,
+ .width = 2,
+};
+
static void __init sunxi_divider_clk_setup(struct device_node *node,
const struct div_data *data)
{
@@ -938,6 +944,13 @@ static void __init sun4i_apb0_clk_setup(struct device_node *node)
CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
sun4i_apb0_clk_setup);
+static void __init sun8i_a83t_apb1_clk_setup(struct device_node *node)
+{
+ sunxi_divider_clk_setup(node, &sun8i_a83t_apb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_apb1, "allwinner,sun8i-a83t-apb1-clk",
+ sun8i_a83t_apb1_clk_setup);
+
static void __init sun4i_axi_clk_setup(struct device_node *node)
{
sunxi_divider_clk_setup(node, &sun4i_axi_data);
--
1.9.1
This adds A83T system bus clocks, bus gates, and clock resets.
Three ahb reset registers are combined into one node.
Signed-off-by: Vishnu Patekar <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 114 +++++++++++++++++++++++++++++++++++++-
1 file changed, 112 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d3473f8..2689af4 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -146,6 +146,97 @@
clocks = <&osc16M>;
clock-output-names = "osc16M-d512";
};
+
+ pll6: clk@01c20028 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-pll4-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6";
+ };
+
+ pll6d2: pll6d2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll6>;
+ clock-output-names = "pll6d2";
+ };
+
+ ahb1: clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+ clock-output-names = "ahb1";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-apb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb2: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+ clock-output-names = "apb2";
+ };
+
+ ahb2: clk@01c2005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&ahb1>, <&pll6d2>;
+ clock-output-names = "ahb2";
+ };
+
+ bus_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a83t-bus-gates-clk";
+ reg = <0x01c20060 0x10>;
+ clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+ clock-names = "ahb1", "ahb2", "apb1", "apb2";
+ clock-indices = <1>, <5>, <6>,
+ <8>, <9>, <10>,
+ <13>, <14>, <17>,
+ <19>, <20>,
+ <21>, <24>,
+ <26>, <27>,
+ <29>, <32>,
+ <36>, <37>,
+ <40>, <43>,
+ <44>, <52>, <53>,
+ <54>, <65>,
+ <69>, <76>, <77>,
+ <78>, <79>, <96>,
+ <97>, <98>,
+ <112>, <113>,
+ <114>, <115>,
+ <116>;
+ clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
+ "bus_mmc0", "bus_mmc1", "bus_mmc2",
+ "bus_nand", "bus_sdram", "bus_emac",
+ "bus_hstimer", "bus_spi0",
+ "bus_spi1", "bus_usb_otg",
+ "bus_ehci0", "bus_ehci1",
+ "bus_ohci0", "bus_ve",
+ "bus_lcd0", "bus_lcd1",
+ "bus_csi", "bus_hdmi",
+ "bus_de", "bus_gpu", "bus_msgbox",
+ "bus_spinlock", "bus_spdif",
+ "bus_pio", "bus_i2s0", "bus_i2s1",
+ "bus_i2s2", "bus_tdm", "bus_i2c0",
+ "bus_i2c1", "bus_i2c2",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_uart4";
+ };
};
soc {
@@ -160,7 +251,7 @@
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c20800 0x400>;
- clocks = <&osc24M>;
+ clocks = <&bus_gates 69>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -189,6 +280,24 @@
};
};
+ ahb_reset: reset@01c202c0 {
+ reg = <0x01c202c0 0xc>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
+ apb1_reset: reset@01c202d0 {
+ reg = <0x01c202d0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
+ apb2_reset: reset@01c202d8 {
+ reg = <0x01c202d8 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
@@ -210,7 +319,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&bus_gates 112>;
+ resets = <&apb2_reset 16>;
status = "disabled";
};
--
1.9.1
A83T mmc is compatible with earliers sunxi socs.
This adds mmc0, mmc1, and mmc2 controller nodes for A83T.
Signed-off-by: Vishnu Patekar <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 943d8a8..a44d4dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -275,6 +275,63 @@
#size-cells = <1>;
ranges;
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&bus_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_reset 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&bus_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_reset 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&bus_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_reset 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
--
1.9.1
mmc clocks are compatible with that of earlier sun8i socs.
This adds mmc0, mmc1, and mmc2 clock nodes for A83T.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 2689af4..943d8a8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -237,6 +237,36 @@
"bus_uart2", "bus_uart3",
"bus_uart4";
};
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
};
soc {
--
1.9.1
Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.
Signed-off-by: Vishnu Patekar <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 691bbf1..5d240b9 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -465,5 +465,17 @@
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-a83t-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_reset 0>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #gpio-cells = <3>;
+ };
};
};
--
1.9.1
This adds A83T PRCM related clocks, clock resets.
As a83t apb0 gates clock support is added earlier, this enables it.
Apart from apb0 gates, other added clocks are compatible with
earlier sun8i socs.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a44d4dc..691bbf1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -267,6 +267,44 @@
"mmc2_output",
"mmc2_sample";
};
+
+ cpus_clk: clk@01f01400 {
+ compatible = "allwinner,sun9i-a80-cpus-clk";
+ reg = <0x01f01400 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
+ clock-output-names = "cpus";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&cpus_clk>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: clk@01f0140c {
+ compatible = "allwinner,sun8i-a23-apb0-clk";
+ reg = <0x01f0140c 0x4>;
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01f01428 {
+ compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <6>, <7>;
+ clock-output-names = "apb0_pio", "apb0_ir",
+ "apb0_timer", "apb0_rsb",
+ "apb0_uart", "apb0_i2c0", "apb0_twd";
+ };
};
soc {
@@ -421,5 +459,11 @@
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ apb0_reset: reset@01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
};
};
--
1.9.1
This enables mmc0.
Signed-off-by: Vishnu Patekar <[email protected]>
Tested-by: LABBE Corentin <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..3269f39 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
/ {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,16 @@
};
};
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v0>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ bus-width = <4>;
+ cd-inverted;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
--
1.9.1
This patch adds support for Sinovoip BPI-M3 A83T based board.
It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.
Signed-off-by: Vishnu Patekar <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 79 ++++++++++++++++++++++++
2 files changed, 80 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 309cce5..64ad31f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -695,6 +695,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
+ sun8i-a83t-sinovoip-bpi-m3.dtb \
sun8i-h3-orangepi-plus.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
new file mode 100644
index 0000000..7744b63
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2016 Vishnu Patekar
+ * Vishnu Patekar <[email protected]>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "Sinovoip BananaPi M3 v1.2";
+ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v0>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ bus-width = <4>;
+ cd-inverted;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
--
1.9.1
This patch adds Kconfig for sunxi clocks.
Currently, only sun8i-apb0 and sun9i-cpus clocks are added.
It'll help to use common clocks across different SOCs.
We can switch to kconfig for other clocks in future.
Signed-off-by: Vishnu Patekar <[email protected]>
---
drivers/clk/Kconfig | 1 +
drivers/clk/sunxi/Kconfig | 5 +++++
drivers/clk/sunxi/Makefile | 4 ++--
3 files changed, 8 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/sunxi/Kconfig
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eca8e01..f9f42e6 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -210,3 +210,4 @@ source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/samsung/Kconfig"
source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/sunxi/Kconfig"
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
new file mode 100644
index 0000000..3e8ede4
--- /dev/null
+++ b/drivers/clk/sunxi/Kconfig
@@ -0,0 +1,5 @@
+config CLK_SUN8I_APB0
+ def_bool MACH_SUN9I || MACH_SUN8I
+
+config CLK_SUN9I_CPUS
+ def_bool MACH_SUN9I || MACH_SUN8I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3fd7901..38dfca8 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -17,8 +17,8 @@ obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
obj-y += clk-usb.o
-obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
-obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
+obj-$(CONFIG_CLK_SUN8I_APB0) += clk-sun8i-apb0.o
+obj-$(CONFIG_CLK_SUN9I_CPUS) += clk-sun9i-cpus.o
obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
--
1.9.1
A83T Boards BPI-m3 and Allwinner H8Homletv2 boards use PF6 as
Card Detect pin., so use PF6 as reference design CD pin in dtsi.
Signed-off-by: Vishnu Patekar <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7b02d85..c64d8d6 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -390,6 +390,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
--
1.9.1
This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A83T dtsi.
Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.
Signed-off-by: Vishnu Patekar <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5d240b9..7b02d85 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -476,6 +476,27 @@
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+
+ r_rsb_pins: r_rsb {
+ allwinner,pins = "PL0", "PL1";
+ allwinner,function = "s_rsb";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+ };
+
+ r_rsb: i2c@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <3000000>;
+ resets = <&apb0_reset 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
--
1.9.1
The A83T has R_PIO pin controller, it's same as A23, execpt A83T
interrupt bit is 6th and A83T has one extra pin PL12.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c | 117 +++++++++++++++++++++
4 files changed, 124 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..f9ff10b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,6 +20,7 @@ Required properties:
"allwinner,sun9i-a80-pinctrl"
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
+ "allwinner,sun8i-a83t-r-pinctrl"
"allwinner,sun8i-h3-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..eeab50b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -51,6 +51,11 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
+config PINCTRL_SUN8I_A83T_R
+ def_bool MACH_SUN8I
+ depends on RESET_CONTROLLER
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..bfd4fa0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
new file mode 100644
index 0000000..5b88921
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -0,0 +1,117 @@
+/*
+ * Allwinner A83T SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2016 Vishnu Patekar
+ * Vishnu Patekar <[email protected]>
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai <[email protected]>
+ * Copyright (C) 2014 Maxime Ripard <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_pwm"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_cir"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT12 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_data = {
+ .pins = sun8i_a83t_r_pins,
+ .npins = ARRAY_SIZE(sun8i_a83t_r_pins),
+ .pin_base = PL_BASE,
+ .irq_banks = 1,
+};
+
+static int sun8i_a83t_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev, &sun8i_a83t_r_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun8i-a83t-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun8i_a83t_r_pinctrl_driver = {
+ .probe = sun8i_a83t_r_pinctrl_probe,
+ .driver = {
+ .name = "sun8i-a83t-r-pinctrl",
+ .of_match_table = sun8i_a83t_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun8i_a83t_r_pinctrl_driver);
--
1.9.1
On Thu, 2016-03-17 at 00:04 +0800, Vishnu Patekar wrote:
> This patch adds Kconfig for sunxi clocks.
> Currently, only sun8i-apb0 and sun9i-cpus clocks are added.
> It'll help to use common clocks across different SOCs.
> We can switch to kconfig for other clocks in future.
>
> Signed-off-by: Vishnu Patekar <[email protected]>
> ---
> drivers/clk/Kconfig | 1 +
> drivers/clk/sunxi/Kconfig | 5 +++++
> drivers/clk/sunxi/Makefile | 4 ++--
> 3 files changed, 8 insertions(+), 2 deletions(-)
> create mode 100644 drivers/clk/sunxi/Kconfig
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index eca8e01..f9f42e6 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -210,3 +210,4 @@ source "drivers/clk/mvebu/Kconfig"
>
> source "drivers/clk/samsung/Kconfig"
> source "drivers/clk/tegra/Kconfig"
> +source "drivers/clk/sunxi/Kconfig"
Should be in alphabetic order?
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> new file mode 100644
> index 0000000..3e8ede4
> --- /dev/null
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -0,0 +1,5 @@
> +config CLK_SUN8I_APB0
> + def_bool MACH_SUN9I || MACH_SUN8I
> +
> +config CLK_SUN9I_CPUS
> + def_bool MACH_SUN9I || MACH_SUN8I
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 3fd7901..38dfca8 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -17,8 +17,8 @@ obj-y += clk-sun9i-core.o
> obj-y += clk-sun9i-mmc.o
> obj-y += clk-usb.o
>
> -obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
> -obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
> +obj-$(CONFIG_CLK_SUN8I_APB0) += clk-sun8i-apb0.o
> +obj-$(CONFIG_CLK_SUN9I_CPUS) += clk-sun9i-cpus.o
>
> obj-$(CONFIG_MFD_SUN6I_PRCM) += \
> clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
> --
> 1.9.1
>
On Thu, Mar 17, 2016 at 12:04:25AM +0800, Vishnu Patekar wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
>
> Signed-off-by: Vishnu Patekar <[email protected]>
> Acked-by: Chen-Yu Tsai <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++
> 2 files changed, 77 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 834436f..cba9fe55 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -30,6 +30,7 @@ Required properties:
> "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
> "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
> "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
> "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
> "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
> "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 91de0a0..a7aab65 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
> req->rate >>= req->p;
> }
>
> +#define SUN8I_A83T_AHB1_PARENT_PLL6 2
> +/**
> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
> + * AHB rate is calculated as follows
> + * rate = parent_rate >> p
> + *
> + * if parent is pll6, then
> + * parent_rate = pll6 rate / (m + 1)
> + */
> +
> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
> +{
> + u8 div, calcp, calcm = 1;
> +
> + /*
> + * clock can only divide, so we will never be able to achieve
> + * frequencies higher than the parent frequency
> + */
> + if (req->parent_rate && req->rate > req->parent_rate)
> + req->rate = req->parent_rate;
> +
> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
> +
> + /* calculate pre-divider if parent is pll6 */
> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
> + if (div < 4)
> + calcp = 0;
> + else if (div / 2 < 4)
> + calcp = 1;
> + else if (div / 4 < 4)
> + calcp = 2;
> + else
> + calcp = 3;
> +
> + calcm = DIV_ROUND_UP(div, 1 << calcp);
> + } else {
> + calcp = __roundup_pow_of_two(div);
> + calcp = calcp > 3 ? 3 : calcp;
> + }
> +
> + req->rate = (req->parent_rate / calcm) >> calcp;
> + req->p = calcp;
> + req->m = calcm - 1;
> +}
> +
> +/**
> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
> +* parent index
> +*/
> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
> +{
> + req->rate = req->parent_rate;
> +
> +/* apply pre-divider first if parent is pll6 */
The comment indentation is wrong
> + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
And this is not the right define you're using.
I still believe that duplicating the same logic just because of
different dividers is not the way to go.
You could solve that easily by adding a table for the muxes, and
associate it with parents and dividers, that you could store in
clk_factors.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Thu, Mar 17, 2016 at 12:04:26AM +0800, Vishnu Patekar wrote:
> APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
>
> This adds support for apb1 on A83T.
>
> Signed-off-by: Vishnu Patekar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/clk-sunxi.c | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index cba9fe55..291d366 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -51,6 +51,7 @@ Required properties:
> "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
> "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
> "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
> ++ "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
There's one '+' too many
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Mar 16, 2016 at 5:04 PM, Vishnu Patekar
<[email protected]> wrote:
> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> interrupt bit is 6th and A83T has one extra pin PL12.
>
> Signed-off-by: Vishnu Patekar <[email protected]>
> Acked-by: Chen-Yu Tsai <[email protected]>
> Acked-by: Rob Herring <[email protected]>
I think I already merged this?
Yours,
Linus Walleij
Hello Linus,
On Thu, Mar 17, 2016 at 10:51 PM, Linus Walleij
<[email protected]> wrote:
> On Wed, Mar 16, 2016 at 5:04 PM, Vishnu Patekar
> <[email protected]> wrote:
>
>> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
>> interrupt bit is 6th and A83T has one extra pin PL12.
>>
>> Signed-off-by: Vishnu Patekar <[email protected]>
>> Acked-by: Chen-Yu Tsai <[email protected]>
>> Acked-by: Rob Herring <[email protected]>
>
> I think I already merged this?
AFAIK, this one is not yet merged. At least, you did not say it's merged. :)
>
> Yours,
> Linus Walleij
On Thu, Mar 17, 2016 at 4:34 PM, Vishnu Patekar
<[email protected]> wrote:
> On Thu, Mar 17, 2016 at 10:51 PM, Linus Walleij
>> I think I already merged this?
>
> AFAIK, this one is not yet merged. At least, you did not say it's merged. :)
Sorry, confused it with the plain A83T controller...
Yours,
Linus Walleij
On Tue, Mar 22, 2016 at 2:12 PM, Linus Walleij <[email protected]> wrote:
> On Thu, Mar 17, 2016 at 4:34 PM, Vishnu Patekar
> <[email protected]> wrote:
>> On Thu, Mar 17, 2016 at 10:51 PM, Linus Walleij
>
>>> I think I already merged this?
>>
>> AFAIK, this one is not yet merged. At least, you did not say it's merged. :)
>
> Sorry, confused it with the plain A83T controller...
Sadly it does not apply so please rebase and resend this patch
after v4.6-rc1 is out.
Yours,
Linus Walleij
Hello Maxime,
On Thu, Mar 17, 2016 at 6:40 PM, Maxime Ripard
<[email protected]> wrote:
> On Thu, Mar 17, 2016 at 12:04:25AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar <[email protected]>
>> Acked-by: Chen-Yu Tsai <[email protected]>
>> Acked-by: Rob Herring <[email protected]>
>> ---
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++
>> 2 files changed, 77 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index 834436f..cba9fe55 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -30,6 +30,7 @@ Required properties:
>> "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>> "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
>> "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
>> "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>> "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>> "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 91de0a0..a7aab65 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
>> req->rate >>= req->p;
>> }
>>
>> +#define SUN8I_A83T_AHB1_PARENT_PLL6 2
>> +/**
>> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
>> + * AHB rate is calculated as follows
>> + * rate = parent_rate >> p
>> + *
>> + * if parent is pll6, then
>> + * parent_rate = pll6 rate / (m + 1)
>> + */
>> +
>> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
>> +{
>> + u8 div, calcp, calcm = 1;
>> +
>> + /*
>> + * clock can only divide, so we will never be able to achieve
>> + * frequencies higher than the parent frequency
>> + */
>> + if (req->parent_rate && req->rate > req->parent_rate)
>> + req->rate = req->parent_rate;
>> +
>> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
>> +
>> + /* calculate pre-divider if parent is pll6 */
>> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
>> + if (div < 4)
>> + calcp = 0;
>> + else if (div / 2 < 4)
>> + calcp = 1;
>> + else if (div / 4 < 4)
>> + calcp = 2;
>> + else
>> + calcp = 3;
>> +
>> + calcm = DIV_ROUND_UP(div, 1 << calcp);
>> + } else {
>> + calcp = __roundup_pow_of_two(div);
>> + calcp = calcp > 3 ? 3 : calcp;
>> + }
>> +
>> + req->rate = (req->parent_rate / calcm) >> calcp;
>> + req->p = calcp;
>> + req->m = calcm - 1;
>> +}
>> +
>> +/**
>> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
>> +* parent index
>> +*/
>> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
>> +{
>> + req->rate = req->parent_rate;
>> +
>> +/* apply pre-divider first if parent is pll6 */
>
> The comment indentation is wrong
>
>> + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
>
> And this is not the right define you're using.
>
> I still believe that duplicating the same logic just because of
> different dividers is not the way to go.
>
> You could solve that easily by adding a table for the muxes, and
> associate it with parents and dividers, that you could store in
> clk_factors.
I've similar solution (please ignore a83 specific functions those will
be common for a31 and a83t).
https://github.com/vishnupatekar/linux/commit/f7de5b48d886a672b1f6db112fbfd5d2c9849afa
is it aligned to what you're saying?
Or do you mean we can use mux clock with div clock as composite clock?
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
On Mon, Apr 04, 2016 at 11:07:29AM +0800, Vishnu Patekar wrote:
> Hello Maxime,
>
> On Thu, Mar 17, 2016 at 6:40 PM, Maxime Ripard
> <[email protected]> wrote:
> > On Thu, Mar 17, 2016 at 12:04:25AM +0800, Vishnu Patekar wrote:
> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> >> clock index 0b1x is PLL6.
> >>
> >> Signed-off-by: Vishnu Patekar <[email protected]>
> >> Acked-by: Chen-Yu Tsai <[email protected]>
> >> Acked-by: Rob Herring <[email protected]>
> >> ---
> >> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> >> drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++
> >> 2 files changed, 77 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> index 834436f..cba9fe55 100644
> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> @@ -30,6 +30,7 @@ Required properties:
> >> "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
> >> "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
> >> "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> >> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
> >> "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
> >> "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
> >> "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> >> index 91de0a0..a7aab65 100644
> >> --- a/drivers/clk/sunxi/clk-sunxi.c
> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
> >> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
> >> req->rate >>= req->p;
> >> }
> >>
> >> +#define SUN8I_A83T_AHB1_PARENT_PLL6 2
> >> +/**
> >> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
> >> + * AHB rate is calculated as follows
> >> + * rate = parent_rate >> p
> >> + *
> >> + * if parent is pll6, then
> >> + * parent_rate = pll6 rate / (m + 1)
> >> + */
> >> +
> >> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
> >> +{
> >> + u8 div, calcp, calcm = 1;
> >> +
> >> + /*
> >> + * clock can only divide, so we will never be able to achieve
> >> + * frequencies higher than the parent frequency
> >> + */
> >> + if (req->parent_rate && req->rate > req->parent_rate)
> >> + req->rate = req->parent_rate;
> >> +
> >> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
> >> +
> >> + /* calculate pre-divider if parent is pll6 */
> >> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
> >> + if (div < 4)
> >> + calcp = 0;
> >> + else if (div / 2 < 4)
> >> + calcp = 1;
> >> + else if (div / 4 < 4)
> >> + calcp = 2;
> >> + else
> >> + calcp = 3;
> >> +
> >> + calcm = DIV_ROUND_UP(div, 1 << calcp);
> >> + } else {
> >> + calcp = __roundup_pow_of_two(div);
> >> + calcp = calcp > 3 ? 3 : calcp;
> >> + }
> >> +
> >> + req->rate = (req->parent_rate / calcm) >> calcp;
> >> + req->p = calcp;
> >> + req->m = calcm - 1;
> >> +}
> >> +
> >> +/**
> >> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
> >> +* parent index
> >> +*/
> >> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
> >> +{
> >> + req->rate = req->parent_rate;
> >> +
> >> +/* apply pre-divider first if parent is pll6 */
> >
> > The comment indentation is wrong
> >
> >> + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
> >
> > And this is not the right define you're using.
> >
> > I still believe that duplicating the same logic just because of
> > different dividers is not the way to go.
> >
> > You could solve that easily by adding a table for the muxes, and
> > associate it with parents and dividers, that you could store in
> > clk_factors.
>
> I've similar solution (please ignore a83 specific functions those will
> be common for a31 and a83t).
> https://github.com/vishnupatekar/linux/commit/f7de5b48d886a672b1f6db112fbfd5d2c9849afa
>
> is it aligned to what you're saying?
Yep. I'd even go a step further, and allow to have directly the core
deal with the pre-divider.
I guess in your prediv table you could have the index, and either the
offset and width of the divider (if it's a variable one), or its fixed
value.
The generic function would then be able to deal with the rate
adjustments, and you wouldn't need to be able to have anything related
to the parent index in the clock specific functions anymore.
Does that make sense?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hello Maxime,
On Fri, Apr 15, 2016 at 1:28 AM, Maxime Ripard
<[email protected]> wrote:
> On Mon, Apr 04, 2016 at 11:07:29AM +0800, Vishnu Patekar wrote:
>> Hello Maxime,
>>
>> On Thu, Mar 17, 2016 at 6:40 PM, Maxime Ripard
>> <[email protected]> wrote:
>> > On Thu, Mar 17, 2016 at 12:04:25AM +0800, Vishnu Patekar wrote:
>> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> >> clock index 0b1x is PLL6.
>> >>
>> >> Signed-off-by: Vishnu Patekar <[email protected]>
>> >> Acked-by: Chen-Yu Tsai <[email protected]>
>> >> Acked-by: Rob Herring <[email protected]>
>> >> ---
>> >> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> >> drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++
>> >> 2 files changed, 77 insertions(+)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> index 834436f..cba9fe55 100644
>> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> @@ -30,6 +30,7 @@ Required properties:
>> >> "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>> >> "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
>> >> "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> >> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
>> >> "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>> >> "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>> >> "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> >> index 91de0a0..a7aab65 100644
>> >> --- a/drivers/clk/sunxi/clk-sunxi.c
>> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> >> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
>> >> req->rate >>= req->p;
>> >> }
>> >>
>> >> +#define SUN8I_A83T_AHB1_PARENT_PLL6 2
>> >> +/**
>> >> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
>> >> + * AHB rate is calculated as follows
>> >> + * rate = parent_rate >> p
>> >> + *
>> >> + * if parent is pll6, then
>> >> + * parent_rate = pll6 rate / (m + 1)
>> >> + */
>> >> +
>> >> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
>> >> +{
>> >> + u8 div, calcp, calcm = 1;
>> >> +
>> >> + /*
>> >> + * clock can only divide, so we will never be able to achieve
>> >> + * frequencies higher than the parent frequency
>> >> + */
>> >> + if (req->parent_rate && req->rate > req->parent_rate)
>> >> + req->rate = req->parent_rate;
>> >> +
>> >> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
>> >> +
>> >> + /* calculate pre-divider if parent is pll6 */
>> >> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
>> >> + if (div < 4)
>> >> + calcp = 0;
>> >> + else if (div / 2 < 4)
>> >> + calcp = 1;
>> >> + else if (div / 4 < 4)
>> >> + calcp = 2;
>> >> + else
>> >> + calcp = 3;
>> >> +
>> >> + calcm = DIV_ROUND_UP(div, 1 << calcp);
>> >> + } else {
>> >> + calcp = __roundup_pow_of_two(div);
>> >> + calcp = calcp > 3 ? 3 : calcp;
>> >> + }
>> >> +
>> >> + req->rate = (req->parent_rate / calcm) >> calcp;
>> >> + req->p = calcp;
>> >> + req->m = calcm - 1;
>> >> +}
>> >> +
>> >> +/**
>> >> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
>> >> +* parent index
>> >> +*/
>> >> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
>> >> +{
>> >> + req->rate = req->parent_rate;
>> >> +
>> >> +/* apply pre-divider first if parent is pll6 */
>> >
>> > The comment indentation is wrong
>> >
>> >> + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
>> >
>> > And this is not the right define you're using.
>> >
>> > I still believe that duplicating the same logic just because of
>> > different dividers is not the way to go.
>> >
>> > You could solve that easily by adding a table for the muxes, and
>> > associate it with parents and dividers, that you could store in
>> > clk_factors.
>>
>> I've similar solution (please ignore a83 specific functions those will
>> be common for a31 and a83t).
>> https://github.com/vishnupatekar/linux/commit/f7de5b48d886a672b1f6db112fbfd5d2c9849afa
>>
>> is it aligned to what you're saying?
>
> Yep. I'd even go a step further, and allow to have directly the core
> deal with the pre-divider.
>
> I guess in your prediv table you could have the index, and either the
> offset and width of the divider (if it's a variable one), or its fixed
> value.
That's good idea, index with shift and width will do as prediv can be variable.
>
> The generic function would then be able to deal with the rate
> adjustments, and you wouldn't need to be able to have anything related
> to the parent index in the clock specific functions anymore.
>
> Does that make sense?
Adjusting rate in generic clk_factors_recalc_rate, with prediv shift
and width is straight forward, and we can remove recalc function
itself, currently it's used only for a31 ahb1.
I'm doubtful about getter, In sun6i_get_ahb1_factors we still need to
pass req->prediv_width instead of req->parent_index.
I'll send separate patch for this prediv handling.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com