On Tue, May 21, 2024 at 02:56:45PM -0400, Da Xue wrote:
> @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct
> gxl_mdio_mux *priv)
> * The only constraint is that it must match the one in
> * drivers/net/phy/meson-gxl.c to properly match the PHY.
> */
> - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
> + writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
> priv->regs + ETH_REG2);
>
> /* Enable the internal phy */
In addition to what Andrew said, you need to look at how you're sending
patches - this patch looks like it has been whitespace damaged, which
means it can't be applied.
--
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On Tue, May 21, 2024 at 3:24 PM Russell King (Oracle)
<[email protected]> wrote:
>
> On Tue, May 21, 2024 at 02:56:45PM -0400, Da Xue wrote:
> > @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct
> > gxl_mdio_mux *priv)
> > * The only constraint is that it must match the one in
> > * drivers/net/phy/meson-gxl.c to properly match the PHY.
> > */
> > - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
> > + writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
> > priv->regs + ETH_REG2);
> >
> > /* Enable the internal phy */
>
> In addition to what Andrew said, you need to look at how you're sending
> patches - this patch looks like it has been whitespace damaged, which
> means it can't be applied.
Thanks for the feedback. There's 2 reserved ranges in that register
with no further descriptions available.
If naming the bit offset after the field range is OK, I will make edit
and submit a V2 though send-email.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!