Instead of the 'amdgpu_ring_priority_level' type,
the 'amdgpu_gfx_pipe_priority' type was used,
which is an error when setting ring priority.
This is a minor error, but may cause problems in the future.
Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
code.
Signed-off-by: Grigory Vasilyev <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5554084ec1f1..9bc26395f833 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1929,7 +1929,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
+ ring->pipe;
hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
+ AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
hw_prio, NULL);
--
2.35.1
On Thu, Apr 7, 2022 at 2:21 AM Christian König
<[email protected]> wrote:
>
> Am 06.04.22 um 18:50 schrieb Grigory Vasilyev:
> > Instead of the 'amdgpu_ring_priority_level' type,
> > the 'amdgpu_gfx_pipe_priority' type was used,
> > which is an error when setting ring priority.
> > This is a minor error, but may cause problems in the future.
> >
> > Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
> > but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
> > AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
> > code.
> >
> > Signed-off-by: Grigory Vasilyev <[email protected]>
>
> Good catch, Acked-by: Christian König <[email protected]>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 5554084ec1f1..9bc26395f833 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -1929,7 +1929,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> > + ring->pipe;
> >
> > hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
> > - AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> > + AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
gfx_v8_0.c, gfx_v9_0.c, gfx_v10_0.c all do this. Care to fix them all up?
Alex
> > /* type-2 packets are deprecated on MEC, use type-3 instead */
> > r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
> > hw_prio, NULL);
>
Alex Deucher I will do it. Initially, I came across an error that
different enum types are used.
Now I looked at the files, and indeed AMDGPU_GFX_PIPE_PRIO_* is used
instead of AMDGPU_RING_PRIO_*.
The question remains whether it is worth increasing the priority to
AMDGPU_RING_PRIO_MAX=3 ?
Regards, Grigory.
чт, 7 апр. 2022 г. в 20:46, Alex Deucher <[email protected]>:
>
> On Thu, Apr 7, 2022 at 2:21 AM Christian König
> <[email protected]> wrote:
> >
> > Am 06.04.22 um 18:50 schrieb Grigory Vasilyev:
> > > Instead of the 'amdgpu_ring_priority_level' type,
> > > the 'amdgpu_gfx_pipe_priority' type was used,
> > > which is an error when setting ring priority.
> > > This is a minor error, but may cause problems in the future.
> > >
> > > Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
> > > but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
> > > AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
> > > code.
> > >
> > > Signed-off-by: Grigory Vasilyev <[email protected]>
> >
> > Good catch, Acked-by: Christian König <[email protected]>
> >
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > index 5554084ec1f1..9bc26395f833 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > @@ -1929,7 +1929,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> > > + ring->pipe;
> > >
> > > hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
> > > - AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> > > + AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
>
> gfx_v8_0.c, gfx_v9_0.c, gfx_v10_0.c all do this. Care to fix them all up?
>
> Alex
>
> > > /* type-2 packets are deprecated on MEC, use type-3 instead */
> > > r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
> > > hw_prio, NULL);
> >
Am 06.04.22 um 18:50 schrieb Grigory Vasilyev:
> Instead of the 'amdgpu_ring_priority_level' type,
> the 'amdgpu_gfx_pipe_priority' type was used,
> which is an error when setting ring priority.
> This is a minor error, but may cause problems in the future.
>
> Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
> but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
> AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
> code.
>
> Signed-off-by: Grigory Vasilyev <[email protected]>
Good catch, Acked-by: Christian König <[email protected]>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 5554084ec1f1..9bc26395f833 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1929,7 +1929,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> + ring->pipe;
>
> hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
> - AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> + AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
> hw_prio, NULL);