This patchset contains the initial common clock support for Broadcom's iProc
family of SoCs. The iProc clock architecture comprises of various PLLs, e.g.,
ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the
basic reference clock for these PLLs. Each PLL may have several leaf clocks.
One special group of clocks is the ASIU clocks, which are dervied directly
from the crystal reference clock.
This patchset also contains the basic clock support for the Broadcom Cygnus
SoC, which implements the iProc clock architecture
Ray Jui (4):
clk: iproc: define Broadcom iProc clock binding
clk: iproc: add initial common clock support
clk: cygnus: add clock support for Broadcom Cygnus
ARM: dts: enable clock support for Broadcom Cygnus
arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 110 +++++--
arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +-
brcm,iproc-clocks.txt | 178 ++++++++++++
drivers/clk/Makefile | 2 +-
drivers/clk/bcm/Kconfig | 9 +
drivers/clk/bcm/Makefile | 2 +
drivers/clk/bcm/clk-cygnus.c | 277 ++++++++++++++++++
drivers/clk/bcm/clk-iproc-armpll.c | 286 ++++++++++++++++++
drivers/clk/bcm/clk-iproc-asiu.c | 275 ++++++++++++++++++
drivers/clk/bcm/clk-iproc-clk.c | 238 +++++++++++++++
drivers/clk/bcm/clk-iproc-pll.c | 483 +++++++++++++++++++++++++++++++
drivers/clk/bcm/clk-iproc.h | 155 ++++++++++
include/dt-bindings/clock/bcm-cygnus.h | 77 +++++
13 files changed, 2067 insertions(+), 27 deletions(-)
create mode 100644 brcm,iproc-clocks.txt
create mode 100644 drivers/clk/bcm/clk-cygnus.c
create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
create mode 100644 drivers/clk/bcm/clk-iproc-clk.c
create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
create mode 100644 drivers/clk/bcm/clk-iproc.h
create mode 100644 include/dt-bindings/clock/bcm-cygnus.h
--
1.7.9.5
Replace current device tree dummy clocks with real clock support for
Broadcom Cygnus SoC
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 110 ++++++++++++++++++++++++-------
arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +-
2 files changed, 86 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
index 60d8389..f2da5e2 100644
--- a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -36,56 +36,116 @@ clocks {
ranges;
osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
- #clock-cells = <1>;
clock-frequency = <25000000>;
};
- apb_clk: apb_clk {
- compatible = "fixed-clock";
+ /* Cygnus ARM PLL */
+ armpll: armpll {
#clock-cells = <0>;
- clock-frequency = <1000000000>;
+ compatible = "brcm,cygnus-armpll";
+ clocks = <&osc>;
+ reg = <0x19000000 0x1000>;
};
- periph_clk: periph_clk {
- compatible = "fixed-clock";
+ /* peripheral clock for system timer */
+ arm_periph_clk: arm_periph_clk {
#clock-cells = <0>;
- clock-frequency = <500000000>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
- sdio_clk: lcpll_ch2 {
- compatible = "fixed-clock";
+ /* APB bus clock */
+ apb_clk: apb_clk {
#clock-cells = <0>;
- clock-frequency = <200000000>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
- axi81_clk: axi81_clk {
- compatible = "fixed-clock";
+ genpll: genpll {
#clock-cells = <0>;
- clock-frequency = <100000000>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
};
- keypad_clk: keypad_clk {
- compatible = "fixed-clock";
+ /* various clocks running off the GENPLL */
+ genpll_clks: genpll_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll-clk";
+ reg = <0x0301d000 0x2c>;
+ clocks = <&genpll>;
+ clock-output-names = "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
+ };
+
+ /* always 1/2 of the axi21 clock */
+ axi41_clk: axi41_clk {
#clock-cells = <0>;
- clock-frequency = <31806>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_clks 0>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
- adc_clk: adc_clk {
- compatible = "fixed-clock";
+ /* always 1/4 of the axi21 clock */
+ axi81_clk: axi81_clk {
#clock-cells = <0>;
- clock-frequency = <1562500>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_clks 0>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
- pwm_clk: pwm_clk {
- compatible = "fixed-clock";
+ lcpll0: lcpll0 {
#clock-cells = <0>;
- clock-frequency = <1000000>;
+ compatible = "brcm,cygnus-lcpll0";
+ reg = <0x0301d02c 0x1c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
};
- lcd_clk: mipipll_ch1 {
- compatible = "fixed-clock";
+ /* various clocks running off the LCPLL0 */
+ lcpll0_clks: lcpll0_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-lcpll0-clk";
+ reg = <0x0301d02c 0x1c>;
+ clocks = <&lcpll0>;
+ clock-output-names = "pcie_phy", "ddr_phy", "sdio",
+ "usb_phy", "smart_card", "ch5";
+ };
+
+ mipipll: mipipll {
#clock-cells = <0>;
- clock-frequency = <100000000>;
+ compatible = "brcm,cygnus-mipipll";
+ reg = <0x180a9800 0x2c>,
+ <0x0301c020 0x4>,
+ <0x180aa024 0x4>;
+ clock-frequency = <1350000000>;
+ clocks = <&osc>;
+ };
+
+ mipipll_clks: mipipll_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-mipipll-clk";
+ reg = <0x180a9800 0x2c>;
+ clocks = <&mipipll>;
+ clock-output-names = "ch0_unused", "ch1_lcd", "ch2_unused",
+ "ch3_unused", "ch4_unused", "ch5_unused";
+ };
+
+ asiu_clks: asiu_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-asiu-clk";
+ reg = <0x0301d048 0xc>,
+ <0x180aa024 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "keypad", "adc/touch", "pwm";
};
};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 5126f9e..2b99e9c 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -134,7 +134,7 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x19020200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&periph_clk>;
+ clocks = <&arm_periph_clk>;
};
};
--
1.7.9.5
The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-cygnus.c | 277 ++++++++++++++++++++++++++++++++
include/dt-bindings/clock/bcm-cygnus.h | 77 +++++++++
3 files changed, 355 insertions(+)
create mode 100644 drivers/clk/bcm/clk-cygnus.c
create mode 100644 include/dt-bindings/clock/bcm-cygnus.h
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 6926636..afcbe55 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-clk.o clk-iproc-asiu.o
+obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
new file mode 100644
index 0000000..f603d1d
--- /dev/null
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+
+#include <dt-bindings/clock/bcm-cygnus.h>
+#include "clk-iproc.h"
+
+#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define asiu_div_val(o, es, hs, hw, ls, lw) \
+ { .offset = o, .en_shift = es, .high_shift = hs, \
+ .high_width = hw, .low_shift = ls, .low_width = lw }
+
+#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+ .ka_width = kaw }
+
+#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
+
+#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
+
+static const struct iproc_pll_ctrl genpll = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC,
+ .aon = aon_val(0x0, 2, 1, 0),
+ .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .ndiv_int = reg_val(0x10, 20, 10),
+ .ndiv_frac = reg_val(0x10, 0, 20),
+ .pdiv = reg_val(0x14, 0, 4),
+ .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
+ .status = reg_val(0x28, 12, 1),
+};
+
+static const struct iproc_pll_ctrl lcpll0 = {
+ .flags = IPROC_CLK_AON,
+ .aon = aon_val(0x0, 2, 5, 4),
+ .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
+ .ndiv_int = reg_val(0x4, 16, 10),
+ .pdiv = reg_val(0x4, 26, 4),
+ .vco_ctrl = vco_ctrl_val(0x10, 0x14),
+ .status = reg_val(0x18, 12, 1),
+};
+
+/*
+ * MIPI PLL VCO frequency parameter table
+ */
+static const struct iproc_pll_vco_freq_param mipipll_vco_params[] = {
+ /* rate (Hz) ndiv_int ndiv_frac pdiv */
+ { 750000000UL, 30, 0, 1 },
+ { 1000000000UL, 40, 0, 1 },
+ { 1350000000ul, 54, 0, 1 },
+ { 2000000000UL, 80, 0, 1 },
+ { 2100000000UL, 84, 0, 1 },
+ { 2250000000UL, 90, 0, 1 },
+ { 2500000000UL, 100, 0, 1 },
+ { 2700000000UL, 54, 0, 0 },
+ { 2975000000UL, 119, 0, 1 },
+ { 3100000000UL, 124, 0, 1 },
+ { 3150000000UL, 126, 0, 1 },
+};
+
+static const struct iproc_pll_ctrl mipipll = {
+ .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC,
+ .aon = aon_val(0x0, 4, 17, 16),
+ .asiu = asiu_gate_val(0x0, 3),
+ .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
+ .ndiv_int = reg_val(0x10, 20, 10),
+ .ndiv_frac = reg_val(0x10, 0, 20),
+ .pdiv = reg_val(0x14, 0, 4),
+ .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
+ .status = reg_val(0x28, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll_clk[BCM_CYGNUS_NUM_GENPLL_CLKS] = {
+ [BCM_CYGNUS_GENPLL_AXI21_CLK] = {
+ .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x4, 6, 0, 12),
+ .mdiv = reg_val(0x20, 0, 8),
+ },
+ [BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
+ .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x4, 7, 1, 13),
+ .mdiv = reg_val(0x20, 10, 8),
+ },
+ [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
+ .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x4, 8, 2, 14),
+ .mdiv = reg_val(0x20, 20, 8),
+ },
+ [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
+ .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x4, 9, 3, 15),
+ .mdiv = reg_val(0x24, 0, 8),
+ },
+ [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
+ .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x4, 10, 4, 16),
+ .mdiv = reg_val(0x24, 10, 8),
+ },
+ [BCM_CYGNUS_GENPLL_CAN_CLK] = {
+ .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x4, 11, 5, 17),
+ .mdiv = reg_val(0x24, 20, 8),
+ },
+};
+
+static const struct iproc_clk_ctrl lcpll0_clk[BCM_CYGNUS_NUM_LCPLL0_CLKS] = {
+ [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
+ .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x0, 7, 1, 13),
+ .mdiv = reg_val(0x8, 0, 8),
+ },
+ [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
+ .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x0, 8, 2, 14),
+ .mdiv = reg_val(0x8, 10, 8),
+ },
+ [BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
+ .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x0, 9, 3, 15),
+ .mdiv = reg_val(0x8, 20, 8),
+ },
+ [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
+ .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x0, 10, 4, 16),
+ .mdiv = reg_val(0xc, 0, 8),
+ },
+ [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
+ .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x0, 11, 5, 17),
+ .mdiv = reg_val(0xc, 10, 8),
+ },
+ [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
+ .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
+ .flags = IPROC_CLK_AON,
+ .enable = enable_val(0x0, 12, 6, 18),
+ .mdiv = reg_val(0xc, 20, 8),
+ },
+};
+
+static const struct iproc_clk_ctrl mipipll_clk[BCM_CYGNUS_NUM_MIPIPLL_CLKS] = {
+ [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
+ .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
+ .enable = enable_val(0x4, 12, 6, 18),
+ .mdiv = reg_val(0x20, 0, 8),
+ },
+ [BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
+ .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
+ .enable = enable_val(0x4, 13, 7, 19),
+ .mdiv = reg_val(0x20, 10, 8),
+ },
+ [BCM_CYGNUS_MIPIPLL_CH2_UNUSED] = {
+ .channel = BCM_CYGNUS_MIPIPLL_CH2_UNUSED,
+ .enable = enable_val(0x4, 14, 8, 20),
+ .mdiv = reg_val(0x20, 20, 8),
+ },
+ [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
+ .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
+ .enable = enable_val(0x4, 15, 9, 21),
+ .mdiv = reg_val(0x24, 0, 8),
+ },
+ [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
+ .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
+ .enable = enable_val(0x4, 16, 10, 22),
+ .mdiv = reg_val(0x24, 10, 8),
+ },
+ [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
+ .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
+ .enable = enable_val(0x4, 17, 11, 23),
+ .mdiv = reg_val(0x24, 20, 8),
+ },
+};
+
+static const struct iproc_asiu_div asiu_div[BCM_CYGNUS_NUM_ASIU_CLKS] = {
+ [BCM_CYGNUS_ASIU_KEYPAD_CLK] =
+ asiu_div_val(0x0, 31, 16, 10, 0, 10),
+ [BCM_CYGNUS_ASIU_ADC_CLK] =
+ asiu_div_val(0x4, 31, 16, 10, 0, 10),
+ [BCM_CYGNUS_ASIU_PWM_CLK] =
+ asiu_div_val(0x8, 31, 16, 10, 0, 10),
+};
+
+static const struct iproc_asiu_gate asiu_gate[BCM_CYGNUS_NUM_ASIU_CLKS] = {
+ [BCM_CYGNUS_ASIU_KEYPAD_CLK] =
+ asiu_gate_val(0x0, 7),
+ [BCM_CYGNUS_ASIU_ADC_CLK] =
+ asiu_gate_val(0x0, 9),
+ [BCM_CYGNUS_ASIU_PWM_CLK] =
+ asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0),
+};
+
+static void __init cygnus_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
+
+static void __init cygnus_genpll_init(struct device_node *node)
+{
+ iproc_pll_setup(node, &genpll, NULL, 0);
+}
+CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_init);
+
+static void __init cygnus_lcpll0_init(struct device_node *node)
+{
+ iproc_pll_setup(node, &lcpll0, NULL, 0);
+}
+CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_init);
+
+static void __init cygnus_mipipll_init(struct device_node *node)
+{
+ iproc_pll_setup(node, &mipipll, mipipll_vco_params,
+ ARRAY_SIZE(mipipll_vco_params));
+}
+CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_init);
+
+static void __init cygnus_genpll_clk_init(struct device_node *node)
+{
+ iproc_clk_setup(node, genpll_clk, BCM_CYGNUS_NUM_GENPLL_CLKS);
+}
+CLK_OF_DECLARE(cygnus_genpll_clk, "brcm,cygnus-genpll-clk",
+ cygnus_genpll_clk_init);
+
+static void __init cygnus_lcpll0_clk_init(struct device_node *node)
+{
+ iproc_clk_setup(node, lcpll0_clk, BCM_CYGNUS_NUM_LCPLL0_CLKS);
+}
+CLK_OF_DECLARE(cygnus_lcpll0_clk, "brcm,cygnus-lcpll0-clk",
+ cygnus_lcpll0_clk_init);
+
+static void __init cygnus_mipipll_clk_init(struct device_node *node)
+{
+ iproc_clk_setup(node, mipipll_clk, BCM_CYGNUS_NUM_MIPIPLL_CLKS);
+}
+CLK_OF_DECLARE(cygnus_mipipll_clk, "brcm,cygnus-mipipll-clk",
+ cygnus_mipipll_clk_init);
+
+static void __init cygnus_asiu_init(struct device_node *node)
+{
+ iproc_asiu_setup(node, asiu_div, asiu_gate, BCM_CYGNUS_NUM_ASIU_CLKS);
+}
+CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
diff --git a/include/dt-bindings/clock/bcm-cygnus.h b/include/dt-bindings/clock/bcm-cygnus.h
new file mode 100644
index 0000000..45948b6
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-cygnus.h
@@ -0,0 +1,77 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_CYGNUS_H
+#define _CLOCK_BCM_CYGNUS_H
+
+/* number of GENPLL clocks */
+#define BCM_CYGNUS_NUM_GENPLL_CLKS 6
+
+/* GENPLL clock channel ID */
+#define BCM_CYGNUS_GENPLL_AXI21_CLK 0
+#define BCM_CYGNUS_GENPLL_250MHZ_CLK 1
+#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 2
+#define BCM_CYGNUS_GENPLL_ENET_SW_CLK 3
+#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK 4
+#define BCM_CYGNUS_GENPLL_CAN_CLK 5
+
+/* number of LCPLL0 clocks */
+#define BCM_CYGNUS_NUM_LCPLL0_CLKS 6
+
+/* LCPLL0 clock channel ID */
+#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 0
+#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 1
+#define BCM_CYGNUS_LCPLL0_SDIO_CLK 2
+#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 3
+#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 4
+#define BCM_CYGNUS_LCPLL0_CH5_UNUSED 5
+
+/* number of MIPI PLL clocks */
+#define BCM_CYGNUS_NUM_MIPIPLL_CLKS 6
+
+/* MIPI PLL clock channel ID */
+#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED 0
+#define BCM_CYGNUS_MIPIPLL_CH1_LCD 1
+#define BCM_CYGNUS_MIPIPLL_CH2_UNUSED 2
+#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED 3
+#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED 4
+#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED 5
+
+/* number of ASIU clocks */
+#define BCM_CYGNUS_NUM_ASIU_CLKS 3
+
+/* ASIU clock IDs */
+#define BCM_CYGNUS_ASIU_KEYPAD_CLK 0
+#define BCM_CYGNUS_ASIU_ADC_CLK 1
+#define BCM_CYGNUS_ASIU_PWM_CLK 2
+
+#endif /* _CLOCK_BCM_CYGNUS_H */
--
1.7.9.5
Document the device tree binding for Broadcom iProc architecture based
clock controller
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
brcm,iproc-clocks.txt | 178 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 brcm,iproc-clocks.txt
diff --git a/brcm,iproc-clocks.txt b/brcm,iproc-clocks.txt
new file mode 100644
index 0000000..cc64fd2
--- /dev/null
+++ b/brcm,iproc-clocks.txt
@@ -0,0 +1,178 @@
+Broadcom iProc Family Clocks
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The iProc clock controller manages clocks that are common to the iProc family.
+An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
+LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
+comprises of several leaf clocks
+
+Required properties for PLLs:
+- compatible:
+ Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
+Cygnus has a compatible string of "brcm,cygnus-genpll"
+
+- #clock-cells:
+ Must be <0>
+
+- reg:
+ Define the base and range of the I/O address space that contain the iProc
+clock control registers required for the PLL
+
+- clocks:
+ The input parent clock phandle for the PLL. For all iProc PLLs, this is an
+onboard crystal with a fixed rate
+
+Optional Properties for PLLs:
+- clock-frequency:
+ PLL frequency in Hz. If specified, PLL will be configured to run at
+<clock-frequency> instead of the default frequency after chip reset, provided
+that <clock-frequency> and its parameters are defined in the SoC specific
+frequency parameter table
+
+Example:
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ genpll: genpll {
+ #clock-cells = <0>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
+ };
+
+Required properties for leaf clocks of a PLL:
+
+- compatible:
+ Should have a value of the form "brcm,<soc>-<pll>-clk". For example, leaf
+clocks derived from the GENPLL on Cygnus SoC have a compatible string of
+"brcm,cygnus-genpll-clk"
+
+- #clock-cells:
+ Have a value of <1> since there are more than 1 leaf clock of a
+given PLL
+
+- reg:
+ Define the base and range of the I/O address space that contain the iProc
+clock control registers required for the PLL leaf clocks
+
+- clocks:
+ The input parent PLL phandle for the leaf clock
+
+- clock-output-names:
+ An ordered list of strings defining the names of the leaf clocks
+
+Example:
+
+ genpll: genpll {
+ #clock-cells = <0>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
+ };
+
+ genpll_clks: genpll_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll-clk";
+ reg = <0x0301d000 0x2c>;
+ clocks = <&genpll>;
+ clock-output-names = "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
+ };
+
+Required properties for ASIU clocks:
+
+ASIU clocks are a special case. These clocks are derived directly from the
+reference clock of the onboard crystal
+
+- compatible:
+ Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
+clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
+
+- #clock-cells:
+ Have a value of <1> since there are more than 1 ASIU clocks
+
+- reg:
+ Define the base and range of the I/O address space that contain the iProc
+clock control registers required for ASIU clocks
+
+- clocks:
+ The input parent clock phandle for the ASIU clock, i.e., the onboard
+crystal
+
+- clock-output-names:
+ An ordered list of strings defining the names of the ASIU clocks
+
+Example:
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ asiu_clks: asiu_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-asiu-clk";
+ reg = <0x0301d048 0xc>,
+ <0x180aa024 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "keypad", "adc/touch", "pwm";
+ };
+
+Cygnus
+------
+PLL and leaf clock compatible strings for Cygnus are:
+ "brcm,cygnus-armpll"
+ "brcm,cygnus-genpll"
+ "brcm,cygnus-lcpll0"
+ "brcm,cygnus-mipipll"
+ "brcm,cygnus-genpll-clk"
+ "brcm,cygnus-lcpll0-clk"
+ "brcm,cygnus-mipipll-clk"
+ "brcm,cygnus-asiu-clk"
+
+The following table defines the set of PLL/clock index and ID for Cygnus.
+These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-cygnus.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+ genpll crystal N/A N/A
+ lcpll0 crystal N/A N/A
+ mipipll crystal N/A N/A
+
+ keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
+ adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
+ pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
+
+ axi21 genpll 0 BCM_CYGNUS_GENPLL_AXI21_CLK
+ 250mhz genpll 1 BCM_CYGNUS_GENPLL_250MHZ_CLK
+ ihost_sys genpll 2 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
+ enet_sw genpll 3 BCM_CYGNUS_GENPLL_ENET_SW_CLK
+ audio_125 genpll 4 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
+ can genpll 5 BCM_CYGNUS_GENPLL_CAN_CLK
+
+ pcie_phy lcpll0 0 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
+ ddr_phy lcpll0 1 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
+ sdio lcpll0 2 BCM_CYGNUS_LCPLL0_SDIO_CLK
+ usb_phy lcpll0 3 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
+ smart_card lcpll0 4 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
+ ch5 lcpll0 5 BCM_CYGNUS_LCPLL0_CH5_UNUSED
+
+ ch0_unused mipipll 0 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
+ ch1_lcd mipipll 1 BCM_CYGNUS_MIPIPLL_CH1_LCD
+ ch2_unused mipipll 2 BCM_CYGNUS_MIPIPLL_CH2_UNUSED
+ ch3_unused mipipll 3 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
+ ch4_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
+ ch5_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
--
1.7.9.5
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.
SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functions
Derived from code originally provided by Jonathan Richardson
<[email protected]>
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
drivers/clk/Makefile | 2 +-
drivers/clk/bcm/Kconfig | 9 +
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-iproc-armpll.c | 286 +++++++++++++++++++++
drivers/clk/bcm/clk-iproc-asiu.c | 275 ++++++++++++++++++++
drivers/clk/bcm/clk-iproc-clk.c | 238 ++++++++++++++++++
drivers/clk/bcm/clk-iproc-pll.c | 483 ++++++++++++++++++++++++++++++++++++
drivers/clk/bcm/clk-iproc.h | 155 ++++++++++++
8 files changed, 1448 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
create mode 100644 drivers/clk/bcm/clk-iproc-clk.c
create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
create mode 100644 drivers/clk/bcm/clk-iproc.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..eff0213 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -41,7 +41,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
-obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
+obj-$(CONFIG_ARCH_BCM) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
obj-$(CONFIG_ARCH_HIP04) += hisilicon/
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 75506e5..66b5b7f 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -7,3 +7,12 @@ config CLK_BCM_KONA
Enable common clock framework support for Broadcom SoCs
using "Kona" style clock control units, including those
in the BCM281xx and BCM21664 families.
+
+config COMMON_CLK_IPROC
+ bool "Broadcom iProc clock support"
+ depends on ARCH_BCM_IPROC
+ depends on COMMON_CLK
+ default y
+ help
+ Enable common clock framework support for Broadcom SoCs
+ based on the "iProc" architecture
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 6297d05..6926636 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-clk.o clk-iproc-asiu.o
diff --git a/drivers/clk/bcm/clk-iproc-armpll.c b/drivers/clk/bcm/clk-iproc-armpll.c
new file mode 100644
index 0000000..ec9b130
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc-armpll.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+
+#define IPROC_CLK_MAX_FREQ_POLICY 0x3
+#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
+#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
+#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
+
+#define IPROC_CLK_PLLARMA_OFFSET 0xc00
+#define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
+#define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
+#define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
+#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
+#define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
+
+#define IPROC_CLK_PLLARMB_OFFSET 0xc04
+#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
+
+#define IPROC_CLK_PLLARMC_OFFSET 0xc08
+#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
+#define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
+
+#define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
+#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
+
+#define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
+#define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
+#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
+#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
+#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff
+
+#define IPROC_CLK_ARM_DIV_OFFSET 0xe00
+#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
+#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf
+
+#define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
+#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
+#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
+
+enum iproc_arm_pll_fid {
+ ARM_PLL_FID_CRYSTAL_CLK = 0,
+ ARM_PLL_FID_SYS_CLK = 2,
+ ARM_PLL_FID_CH0_SLOW_CLK = 6,
+ ARM_PLL_FID_CH1_FAST_CLK = 7
+};
+
+struct iproc_arm_pll {
+ struct clk_hw hw;
+ void __iomem *base;
+ struct clk_onecell_data clk_data;
+ unsigned long rate;
+};
+
+#define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)
+
+static unsigned int __get_fid(struct iproc_arm_pll *pll)
+{
+ u32 val;
+ unsigned int policy, fid, active_fid;
+
+ val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
+ if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
+ policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
+ else
+ policy = 0;
+
+ /* something is seriously wrong */
+ BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);
+
+ val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
+ fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
+ IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;
+
+ val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
+ active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
+ (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
+ if (fid != active_fid) {
+ pr_debug("%s: fid override %u->%u\n", __func__, fid,
+ active_fid);
+ fid = active_fid;
+ }
+
+ pr_debug("%s: active fid: %u\n", __func__, fid);
+
+ return fid;
+}
+
+/*
+ * Determine the mdiv (post divider) based on the frequency ID being used.
+ * There are 4 sources that can be used to derive the output clock rate:
+ * - 25 MHz Crystal
+ * - System clock
+ * - PLL channel 0 (slow clock)
+ * - PLL channel 1 (fast clock)
+ */
+static int __get_mdiv(struct iproc_arm_pll *pll)
+{
+ unsigned int fid;
+ int mdiv;
+ u32 val;
+
+ fid = __get_fid(pll);
+
+ switch (fid) {
+ case ARM_PLL_FID_CRYSTAL_CLK:
+ case ARM_PLL_FID_SYS_CLK:
+ mdiv = 1;
+ break;
+
+ case ARM_PLL_FID_CH0_SLOW_CLK:
+ val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
+ mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
+ if (mdiv == 0)
+ mdiv = 256;
+ break;
+
+ case ARM_PLL_FID_CH1_FAST_CLK:
+ val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
+ mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
+ if (mdiv == 0)
+ mdiv = 256;
+ break;
+
+ default:
+ mdiv = -EFAULT;
+ }
+
+ return mdiv;
+}
+
+static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
+{
+ u32 val;
+ unsigned int ndiv_int, ndiv_frac, ndiv;
+
+ val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
+ if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
+ /*
+ * offset mode is active. Read the ndiv from the PLLARM OFFSET
+ * register
+ */
+ ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
+ IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
+ if (ndiv_int == 0)
+ ndiv_int = 256;
+
+ ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
+ } else {
+ /* offset mode not active */
+ val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
+ ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
+ IPROC_CLK_PLLARMA_NDIV_INT_MASK;
+ if (ndiv_int == 0)
+ ndiv_int = 1024;
+
+ val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
+ ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
+ }
+
+ ndiv = (ndiv_int << 20) | ndiv_frac;
+
+ return ndiv;
+}
+
+/*
+ * The output frequency of the ARM PLL is calculated based on the ARM PLL
+ * divider values:
+ * pdiv = ARM PLL pre-divider
+ * ndiv = ARM PLL multiplier
+ * mdiv = ARM PLL post divider
+ *
+ * The frequency is calculated by:
+ * ((ndiv * parent clock rate) / pdiv) / mdiv
+ */
+static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
+ u32 val;
+ int mdiv;
+ u64 ndiv;
+ unsigned int pdiv;
+
+ /* in bypass mode, use parent rate */
+ val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
+ if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
+ pll->rate = parent_rate;
+ return pll->rate;
+ }
+
+ /* PLL needs to be locked */
+ val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
+ if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
+ pll->rate = 0;
+ return 0;
+ }
+
+ pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
+ IPROC_CLK_PLLARMA_PDIV_MASK;
+ if (pdiv == 0)
+ pdiv = 16;
+
+ ndiv = __get_ndiv(pll);
+ mdiv = __get_mdiv(pll);
+ if (mdiv <= 0) {
+ pll->rate = 0;
+ return 0;
+ }
+ pll->rate = (ndiv * parent_rate) >> 20;
+ pll->rate = (pll->rate / pdiv) / mdiv;
+
+ pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
+ pll->rate, parent_rate);
+ pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
+ (unsigned int)(ndiv >> 20), pdiv, mdiv);
+
+ return pll->rate;
+}
+
+static const struct clk_ops iproc_arm_pll_ops = {
+ .recalc_rate = iproc_arm_pll_recalc_rate,
+};
+
+void __init iproc_armpll_setup(struct device_node *node)
+{
+ int ret;
+ struct clk *clk;
+ struct iproc_arm_pll *pll;
+ struct clk_init_data init;
+ const char *parent_name;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (WARN_ON(!pll))
+ return;
+
+ pll->base = of_iomap(node, 0);
+ if (WARN_ON(!pll->base))
+ goto err_free_pll;
+
+ init.name = node->name;
+ init.ops = &iproc_arm_pll_ops;
+ init.flags = 0;
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (WARN_ON(IS_ERR(clk)))
+ goto err_iounmap;
+
+ pll->clk_data.clk_num = 1;
+ pll->clk_data.clks = &clk;
+
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data);
+ if (WARN_ON(ret))
+ goto err_clk_unregister;
+
+ return;
+
+err_clk_unregister:
+ clk_unregister(clk);
+err_iounmap:
+ iounmap(pll->base);
+err_free_pll:
+ kfree(pll);
+}
diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
new file mode 100644
index 0000000..ab86b8c
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc-asiu.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+
+#include "clk-iproc.h"
+
+struct iproc_asiu;
+
+struct iproc_asiu_clk {
+ struct clk_hw hw;
+ const char *name;
+ struct iproc_asiu *asiu;
+ unsigned long rate;
+ struct iproc_asiu_div div;
+ struct iproc_asiu_gate gate;
+};
+
+struct iproc_asiu {
+ void __iomem *div_base;
+ void __iomem *gate_base;
+
+ struct clk_onecell_data clk_data;
+ struct iproc_asiu_clk *clks;
+};
+
+#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
+
+static int iproc_asiu_clk_enable(struct clk_hw *hw)
+{
+ struct iproc_asiu_clk *clk = to_asiu_clk(hw);
+ struct iproc_asiu *asiu = clk->asiu;
+ u32 val;
+
+ /* some clocks at the ASIU level are always enabled */
+ if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
+ return 0;
+
+ val = readl(asiu->gate_base + clk->gate.offset);
+ val |= (1 << clk->gate.en_shift);
+ writel(val, asiu->gate_base + clk->gate.offset);
+
+ return 0;
+}
+
+static void iproc_asiu_clk_disable(struct clk_hw *hw)
+{
+ struct iproc_asiu_clk *clk = to_asiu_clk(hw);
+ struct iproc_asiu *asiu = clk->asiu;
+ u32 val;
+
+ /* some clocks at the ASIU level are always enabled */
+ if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
+ return;
+
+ val = readl(asiu->gate_base + clk->gate.offset);
+ val &= ~(1 << clk->gate.en_shift);
+ writel(val, asiu->gate_base + clk->gate.offset);
+}
+
+static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct iproc_asiu_clk *clk = to_asiu_clk(hw);
+ struct iproc_asiu *asiu = clk->asiu;
+ u32 val;
+ unsigned int div_h, div_l;
+
+ if (parent_rate == 0) {
+ clk->rate = 0;
+ return 0;
+ }
+
+ /* if clock divisor is not enabled, simply return parent rate */
+ val = readl(asiu->div_base + clk->div.offset);
+ if ((val & (1 << clk->div.en_shift)) == 0) {
+ clk->rate = parent_rate;
+ return parent_rate;
+ }
+
+ /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
+ div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
+ div_h++;
+ div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
+ div_l++;
+
+ clk->rate = parent_rate / (div_h + div_l);
+ pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
+ __func__, clk->rate, parent_rate, div_h, div_l);
+
+ return clk->rate;
+}
+
+static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned int div;
+
+ if (rate == 0 || *parent_rate == 0)
+ return -EINVAL;
+
+ if (rate == *parent_rate)
+ return *parent_rate;
+
+ div = DIV_ROUND_UP(*parent_rate, rate);
+ if (div < 2)
+ return *parent_rate;
+
+ return *parent_rate / div;
+}
+
+static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct iproc_asiu_clk *clk = to_asiu_clk(hw);
+ struct iproc_asiu *asiu = clk->asiu;
+ unsigned int div, div_h, div_l;
+ u32 val;
+
+ if (rate == 0 || parent_rate == 0)
+ return -EINVAL;
+
+ /* simply disable the divisor if one wants the same rate as parent */
+ if (rate == parent_rate) {
+ val = readl(asiu->div_base + clk->div.offset);
+ val &= ~(1 << clk->div.en_shift);
+ writel(val, asiu->div_base + clk->div.offset);
+ return 0;
+ }
+
+ div = DIV_ROUND_UP(parent_rate, rate);
+ if (div < 2)
+ return -EINVAL;
+
+ div_h = div_l = div >> 1;
+ div_h--;
+ div_l--;
+
+ val = readl(asiu->div_base + clk->div.offset);
+ val |= 1 << clk->div.en_shift;
+ if (div_h) {
+ val &= ~(bit_mask(clk->div.high_width)
+ << clk->div.high_shift);
+ val |= div_h << clk->div.high_shift;
+ } else {
+ val &= ~(bit_mask(clk->div.high_width)
+ << clk->div.high_shift);
+ }
+ if (div_l) {
+ val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
+ val |= div_l << clk->div.low_shift;
+ } else {
+ val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
+ }
+ writel(val, asiu->div_base + clk->div.offset);
+
+ return 0;
+}
+
+static const struct clk_ops iproc_asiu_ops = {
+ .enable = iproc_asiu_clk_enable,
+ .disable = iproc_asiu_clk_disable,
+ .recalc_rate = iproc_asiu_clk_recalc_rate,
+ .round_rate = iproc_asiu_clk_round_rate,
+ .set_rate = iproc_asiu_clk_set_rate,
+};
+
+void __init iproc_asiu_setup(struct device_node *node,
+ const struct iproc_asiu_div *div,
+ const struct iproc_asiu_gate *gate, unsigned int num_clks)
+{
+ int i, ret;
+ struct iproc_asiu *asiu;
+
+ if (WARN_ON(!gate || !div))
+ return;
+
+ asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
+ if (WARN_ON(!asiu))
+ return;
+
+ asiu->clk_data.clk_num = num_clks;
+ asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks),
+ GFP_KERNEL);
+ if (WARN_ON(!asiu->clk_data.clks))
+ goto err_clks;
+
+ asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
+ if (WARN_ON(!asiu->clks))
+ goto err_asiu_clks;
+
+ asiu->div_base = of_iomap(node, 0);
+ if (WARN_ON(!asiu->div_base))
+ goto err_iomap_div;
+
+ asiu->gate_base = of_iomap(node, 1);
+ if (WARN_ON(!asiu->gate_base))
+ goto err_iomap_gate;
+
+ for (i = 0; i < num_clks; i++) {
+ struct clk_init_data init;
+ struct clk *clk;
+ const char *parent_name;
+ struct iproc_asiu_clk *asiu_clk;
+ const char *clk_name;
+
+ clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
+ if (WARN_ON(!clk_name))
+ goto err_clk_register;
+
+ ret = of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+ if (WARN_ON(ret))
+ goto err_clk_register;
+
+ asiu_clk = &asiu->clks[i];
+ asiu_clk->name = clk_name;
+ asiu_clk->asiu = asiu;
+ asiu_clk->div = div[i];
+ asiu_clk->gate = gate[i];
+ init.name = clk_name;
+ init.ops = &iproc_asiu_ops;
+ init.flags = 0;
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ asiu_clk->hw.init = &init;
+
+ clk = clk_register(NULL, &asiu_clk->hw);
+ if (WARN_ON(IS_ERR(clk)))
+ goto err_clk_register;
+ asiu->clk_data.clks[i] = clk;
+ }
+
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get,
+ &asiu->clk_data);
+ if (WARN_ON(ret))
+ goto err_clk_register;
+
+ return;
+
+err_clk_register:
+ for (i = 0; i < num_clks; i++)
+ kfree(asiu->clks[i].name);
+ iounmap(asiu->gate_base);
+
+err_iomap_gate:
+ iounmap(asiu->div_base);
+
+err_iomap_div:
+ kfree(asiu->clks);
+
+err_asiu_clks:
+ kfree(asiu->clk_data.clks);
+
+err_clks:
+ kfree(asiu);
+}
diff --git a/drivers/clk/bcm/clk-iproc-clk.c b/drivers/clk/bcm/clk-iproc-clk.c
new file mode 100644
index 0000000..be3c42c
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc-clk.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+
+#include "clk-iproc.h"
+
+struct iproc_pll;
+
+struct iproc_clk {
+ struct clk_hw hw;
+ const char *name;
+ struct iproc_pll *pll;
+ unsigned long rate;
+ const struct iproc_clk_ctrl *ctrl;
+};
+
+struct iproc_pll {
+ void __iomem *base;
+ struct clk_onecell_data clk_data;
+ struct iproc_clk *clks;
+};
+
+#define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw)
+
+static int iproc_clk_enable(struct clk_hw *hw)
+{
+ struct iproc_clk *clk = to_iproc_clk(hw);
+ const struct iproc_clk_ctrl *ctrl = clk->ctrl;
+ struct iproc_pll *pll = clk->pll;
+ u32 val;
+
+ /* channel enable is active low */
+ val = readl(pll->base + ctrl->enable.offset);
+ val &= ~(1 << ctrl->enable.enable_shift);
+ writel(val, pll->base + ctrl->enable.offset);
+
+ /* also make sure channel is not held */
+ val = readl(pll->base + ctrl->enable.offset);
+ val &= ~(1 << ctrl->enable.hold_shift);
+ writel(val, pll->base + ctrl->enable.offset);
+
+ return 0;
+}
+
+static void iproc_clk_disable(struct clk_hw *hw)
+{
+ struct iproc_clk *clk = to_iproc_clk(hw);
+ const struct iproc_clk_ctrl *ctrl = clk->ctrl;
+ struct iproc_pll *pll = clk->pll;
+ u32 val;
+
+ if (ctrl->flags & IPROC_CLK_AON)
+ return;
+
+ val = readl(pll->base + ctrl->enable.offset);
+ val |= 1 << ctrl->enable.enable_shift;
+ writel(val, pll->base + ctrl->enable.offset);
+}
+
+static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct iproc_clk *clk = to_iproc_clk(hw);
+ const struct iproc_clk_ctrl *ctrl = clk->ctrl;
+ struct iproc_pll *pll = clk->pll;
+ u32 val;
+ unsigned int mdiv;
+
+ if (parent_rate == 0)
+ return 0;
+
+ val = readl(pll->base + ctrl->mdiv.offset);
+ mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width);
+ if (mdiv == 0)
+ mdiv = 256;
+
+ clk->rate = parent_rate / mdiv;
+
+ return clk->rate;
+}
+
+static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned int div;
+
+ if (rate == 0 || *parent_rate == 0)
+ return -EINVAL;
+
+ if (rate == *parent_rate)
+ return *parent_rate;
+
+ div = DIV_ROUND_UP(*parent_rate, rate);
+ if (div < 2)
+ return *parent_rate;
+
+ if (div > 256)
+ div = 256;
+
+ return *parent_rate / div;
+}
+
+static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct iproc_clk *clk = to_iproc_clk(hw);
+ const struct iproc_clk_ctrl *ctrl = clk->ctrl;
+ struct iproc_pll *pll = clk->pll;
+ u32 val;
+ unsigned int div;
+
+ if (rate == 0 || parent_rate == 0)
+ return -EINVAL;
+
+ div = DIV_ROUND_UP(parent_rate, rate);
+ if (div > 256)
+ return -EINVAL;
+
+ val = readl(pll->base + ctrl->mdiv.offset);
+ if (div == 256) {
+ val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
+ } else {
+ val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
+ val |= div << ctrl->mdiv.shift;
+ }
+ writel(val, pll->base + ctrl->mdiv.offset);
+ clk->rate = parent_rate / div;
+
+ return 0;
+}
+
+static const struct clk_ops iproc_clk_ops = {
+ .enable = iproc_clk_enable,
+ .disable = iproc_clk_disable,
+ .recalc_rate = iproc_clk_recalc_rate,
+ .round_rate = iproc_clk_round_rate,
+ .set_rate = iproc_clk_set_rate,
+};
+
+void __init iproc_clk_setup(struct device_node *node,
+ const struct iproc_clk_ctrl *ctrl, unsigned int num_clks)
+{
+ int i, ret;
+ struct iproc_pll *pll;
+
+ if (WARN_ON(!ctrl))
+ return;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (WARN_ON(!pll))
+ return;
+
+ pll->clk_data.clk_num = num_clks;
+ pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks),
+ GFP_KERNEL);
+ if (WARN_ON(!pll->clk_data.clks))
+ goto err_clks;
+
+ pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL);
+ if (WARN_ON(!pll->clks))
+ goto err_pll_clks;
+
+ pll->base = of_iomap(node, 0);
+ if (WARN_ON(!pll->base))
+ goto err_iomap;
+
+ for (i = 0; i < num_clks; i++) {
+ struct clk_init_data init;
+ struct clk *clk;
+ const char *parent_name;
+ struct iproc_clk *iclk;
+ const char *clk_name;
+
+ clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
+ if (WARN_ON(!clk_name))
+ goto err_clk_register;
+
+ ret = of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+ if (WARN_ON(ret))
+ goto err_clk_register;
+
+ iclk = &pll->clks[i];
+ iclk->name = clk_name;
+ iclk->pll = pll;
+ iclk->ctrl = &ctrl[i];
+ init.name = clk_name;
+ init.ops = &iproc_clk_ops;
+ init.flags = 0;
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ iclk->hw.init = &init;
+
+ clk = clk_register(NULL, &iclk->hw);
+ if (WARN_ON(IS_ERR(clk)))
+ goto err_clk_register;
+ pll->clk_data.clks[i] = clk;
+ }
+
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data);
+ if (WARN_ON(ret))
+ goto err_clk_register;
+
+ return;
+
+err_clk_register:
+ for (i = 0; i < num_clks; i++)
+ kfree(pll->clks[i].name);
+ iounmap(pll->base);
+
+err_iomap:
+ kfree(pll->clks);
+
+err_pll_clks:
+ kfree(pll->clk_data.clks);
+
+err_clks:
+ kfree(pll);
+}
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
new file mode 100644
index 0000000..cd3bd38
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+
+#include "clk-iproc.h"
+
+#define PLL_VCO_HIGH_SHIFT 19
+#define PLL_VCO_LOW_SHIFT 30
+
+/* number of delay loops waiting for PLL to lock */
+#define LOCK_DELAY 100
+
+/* number of VCO frequency bands */
+#define NUM_FREQ_BANDS 8
+
+#define NUM_KP_BANDS 3
+enum kp_band {
+ KP_BAND_MID = 0,
+ KP_BAND_HIGH,
+ KP_BAND_HIGH_HIGH
+};
+
+static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = {
+ { 5, 6, 6, 7, 7, 8, 9, 10 },
+ { 4, 4, 5, 5, 6, 7, 8, 9 },
+ { 4, 5, 5, 6, 7, 8, 9, 10 },
+};
+
+static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = {
+ { 10000000, 12500000 },
+ { 12500000, 15000000 },
+ { 15000000, 20000000 },
+ { 20000000, 25000000 },
+ { 25000000, 50000000 },
+ { 50000000, 75000000 },
+ { 75000000, 100000000 },
+ { 100000000, 125000000 },
+};
+
+enum vco_freq_range {
+ VCO_LOW = 700000000U,
+ VCO_MID = 1200000000U,
+ VCO_HIGH = 2200000000U,
+ VCO_HIGH_HIGH = 3100000000U,
+ VCO_MAX = 4000000000U,
+};
+
+struct iproc_pll {
+ struct clk_hw hw;
+ void __iomem *pll_base;
+ void __iomem *pwr_base;
+ void __iomem *asiu_base;
+ struct clk_onecell_data clk_data;
+ const char *name;
+ const struct iproc_pll_ctrl *ctrl;
+ const struct iproc_pll_vco_freq_param *vco_param;
+ unsigned int num_vco_entries;
+ unsigned long rate;
+};
+
+#define to_iproc_pll(hw) container_of(hw, struct iproc_pll, hw)
+
+/*
+ * Get the clock rate based on name
+ */
+static unsigned long __get_rate(const char *clk_name)
+{
+ struct clk *clk;
+
+ clk = __clk_lookup(clk_name);
+ if (!clk) {
+ pr_err("%s: unable to find clock by name: %s\n", __func__,
+ clk_name);
+ return 0;
+ }
+
+ return clk_get_rate(clk);
+}
+
+/*
+ * Based on the target frequency, find a match from the VCO frequency parameter
+ * table and return its index
+ */
+static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate)
+{
+ int i;
+
+ for (i = 0; i < pll->num_vco_entries; i++)
+ if (target_rate == pll->vco_param[i].rate)
+ break;
+
+ if (i >= pll->num_vco_entries)
+ return -EINVAL;
+
+ return i;
+}
+
+static int get_kp(unsigned long ref_freq, enum kp_band kp_index)
+{
+ int i;
+
+ if (ref_freq < ref_freq_table[0][0])
+ return -EINVAL;
+
+ for (i = 0; i < NUM_FREQ_BANDS; i++) {
+ if (ref_freq >= ref_freq_table[i][0] &&
+ ref_freq < ref_freq_table[i][1])
+ return kp_table[kp_index][i];
+ }
+ return -EINVAL;
+}
+
+static int pll_wait_for_lock(struct iproc_pll *pll)
+{
+ int i;
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+
+ for (i = 0; i < LOCK_DELAY; i++) {
+ u32 val = readl(pll->pll_base + ctrl->status.offset);
+
+ if (val & (1 << ctrl->status.shift))
+ return 0;
+ udelay(10);
+ }
+
+ return -EIO;
+}
+
+static void __pll_disable(struct iproc_pll *pll)
+{
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ u32 val;
+
+ if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
+ val = readl(pll->asiu_base + ctrl->asiu.offset);
+ val &= ~(1 << ctrl->asiu.en_shift);
+ writel(val, pll->asiu_base + ctrl->asiu.offset);
+ }
+
+ /* latch input value so core power can be shut down */
+ val = readl(pll->pwr_base + ctrl->aon.offset);
+ val |= (1 << ctrl->aon.iso_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+
+ /* power down the core */
+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+}
+
+static int __pll_enable(struct iproc_pll *pll)
+{
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ u32 val;
+
+ /* power up the PLL and make sure it's not latched */
+ val = readl(pll->pwr_base + ctrl->aon.offset);
+ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
+ val &= ~(1 << ctrl->aon.iso_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+
+ /* certain PLLs also need to be ungated from the ASIU top level */
+ if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
+ val = readl(pll->asiu_base + ctrl->asiu.offset);
+ val |= (1 << ctrl->asiu.en_shift);
+ writel(val, pll->asiu_base + ctrl->asiu.offset);
+ }
+
+ return 0;
+}
+
+static void __pll_put_in_reset(struct iproc_pll *pll)
+{
+ u32 val;
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
+
+ val = readl(pll->pll_base + reset->offset);
+ val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
+ writel(val, pll->pll_base + reset->offset);
+}
+
+static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
+ unsigned int ka, unsigned int ki)
+{
+ u32 val;
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
+
+ val = readl(pll->pll_base + reset->offset);
+ val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
+ bit_mask(reset->kp_width) << reset->kp_shift |
+ bit_mask(reset->ka_width) << reset->ka_shift);
+ val |= ki << reset->ki_shift | kp << reset->kp_shift |
+ ka << reset->ka_shift;
+ val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
+ writel(val, pll->pll_base + reset->offset);
+}
+
+static int pll_set_rate(struct iproc_pll *pll, unsigned int rate_index,
+ unsigned long parent_rate)
+{
+ const struct iproc_pll_vco_freq_param *vco =
+ &pll->vco_param[rate_index];
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ int ka = 0, ki, kp, ret;
+ unsigned long rate = vco->rate;
+ u32 val;
+ enum kp_band kp_index;
+ unsigned long ref_freq;
+
+ /*
+ * reference frequency = parent frequency / PDIV
+ * If PDIV = 0, then it becomes a multiplier (x2)
+ */
+ if (vco->pdiv == 0)
+ ref_freq = parent_rate * 2;
+ else
+ ref_freq = parent_rate / vco->pdiv;
+
+ /* determine Ki and Kp index based on target VCO frequency */
+ if (rate >= VCO_LOW && rate < VCO_HIGH) {
+ ki = 4;
+ kp_index = KP_BAND_MID;
+ } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) {
+ ki = 3;
+ kp_index = KP_BAND_HIGH;
+ } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) {
+ ki = 3;
+ kp_index = KP_BAND_HIGH_HIGH;
+ } else {
+ pr_err("%s: pll: %s has invalid rate: %lu\n", __func__,
+ pll->name, rate);
+ return -EINVAL;
+ }
+
+ kp = get_kp(ref_freq, kp_index);
+ if (kp < 0) {
+ pr_err("%s: pll: %s has invalid kp\n", __func__, pll->name);
+ return kp;
+ }
+
+ ret = __pll_enable(pll);
+ if (ret) {
+ pr_err("%s: pll: %s fails to enable\n", __func__, pll->name);
+ return ret;
+ }
+
+ /* put PLL in reset */
+ __pll_put_in_reset(pll);
+
+ writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset);
+ val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset);
+
+ if (rate >= VCO_LOW && rate < VCO_MID)
+ val |= (1 << PLL_VCO_LOW_SHIFT);
+
+ if (rate < VCO_HIGH)
+ val &= ~(1 << PLL_VCO_HIGH_SHIFT);
+ else
+ val |= (1 << PLL_VCO_HIGH_SHIFT);
+
+ writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset);
+
+ /* program integer part of NDIV */
+ val = readl(pll->pll_base + ctrl->ndiv_int.offset);
+ val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift);
+ val |= vco->ndiv_int << ctrl->ndiv_int.shift;
+ writel(val, pll->pll_base + ctrl->ndiv_int.offset);
+
+ /* program fractional part of NDIV */
+ if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
+ val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
+ val &= ~(bit_mask(ctrl->ndiv_frac.width) <<
+ ctrl->ndiv_frac.shift);
+ val |= vco->ndiv_frac << ctrl->ndiv_frac.shift;
+ writel(val, pll->pll_base + ctrl->ndiv_frac.offset);
+ }
+
+ /* program PDIV */
+ val = readl(pll->pll_base + ctrl->pdiv.offset);
+ val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift);
+ val |= vco->pdiv << ctrl->pdiv.shift;
+ writel(val, pll->pll_base + ctrl->pdiv.offset);
+
+ __pll_bring_out_reset(pll, kp, ka, ki);
+
+ ret = pll_wait_for_lock(pll);
+ if (ret < 0) {
+ pr_err("%s: pll: %s failed to lock\n", __func__, pll->name);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int iproc_pll_enable(struct clk_hw *hw)
+{
+ struct iproc_pll *pll = to_iproc_pll(hw);
+
+ return __pll_enable(pll);
+}
+
+static void iproc_pll_disable(struct clk_hw *hw)
+{
+ struct iproc_pll *pll = to_iproc_pll(hw);
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+
+ if (ctrl->flags & IPROC_CLK_AON)
+ return;
+
+ __pll_disable(pll);
+}
+
+static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct iproc_pll *pll = to_iproc_pll(hw);
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+ u32 val;
+ u64 ndiv;
+ unsigned int ndiv_int, ndiv_frac, pdiv;
+
+ if (parent_rate == 0)
+ return 0;
+
+ /* PLL needs to be locked */
+ val = readl(pll->pll_base + ctrl->status.offset);
+ if ((val & (1 << ctrl->status.shift)) == 0) {
+ pll->rate = 0;
+ return 0;
+ }
+
+ /*
+ * PLL output frequency =
+ *
+ * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv)
+ */
+ val = readl(pll->pll_base + ctrl->ndiv_int.offset);
+ ndiv_int = (val >> ctrl->ndiv_int.shift) &
+ bit_mask(ctrl->ndiv_int.width);
+ ndiv = ndiv_int << ctrl->ndiv_int.shift;
+
+ if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
+ val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
+ ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
+ bit_mask(ctrl->ndiv_frac.width);
+
+ if (ndiv_frac != 0)
+ ndiv = (ndiv_int << ctrl->ndiv_int.shift) | ndiv_frac;
+ }
+
+ val = readl(pll->pll_base + ctrl->pdiv.offset);
+ pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
+
+ pll->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
+
+ if (pdiv == 0)
+ pll->rate *= 2;
+ else
+ pll->rate /= pdiv;
+
+ return pll->rate;
+}
+
+static const struct clk_ops iproc_pll_ops = {
+ .enable = iproc_pll_enable,
+ .disable = iproc_pll_disable,
+ .recalc_rate = iproc_pll_recalc_rate,
+};
+
+void __init iproc_pll_setup(struct device_node *node,
+ const struct iproc_pll_ctrl *ctrl,
+ const struct iproc_pll_vco_freq_param *vco_param,
+ unsigned int num_vco_entries)
+{
+ int ret;
+ struct clk *clk;
+ struct iproc_pll *pll;
+ struct clk_init_data init;
+ const char *parent_name;
+ unsigned int rate;
+
+ if (WARN_ON(!ctrl))
+ return;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (WARN_ON(!pll))
+ return;
+
+ pll->pll_base = of_iomap(node, 0);
+ if (WARN_ON(!pll->pll_base))
+ goto err_pll_iomap;
+
+ pll->pwr_base = of_iomap(node, 1);
+ if (WARN_ON(!pll->pwr_base))
+ goto err_pwr_iomap;
+
+ /* some PLLs require gating control at the top ASIU level */
+ if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
+ pll->asiu_base = of_iomap(node, 2);
+ if (WARN_ON(!pll->asiu_base))
+ goto err_asiu_iomap;
+ }
+
+ pll->ctrl = ctrl;
+ pll->name = node->name;
+ init.name = node->name;
+ init.ops = &iproc_pll_ops;
+ init.flags = 0;
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ pll->hw.init = &init;
+
+ /* configure the PLL to the desired VCO frequency if specified */
+ ret = of_property_read_u32(node, "clock-frequency", &rate);
+ if (!ret) {
+ unsigned long parent_rate;
+ int rate_index;
+
+ if (WARN_ON(!vco_param))
+ goto err_clk_register;
+
+ pll->num_vco_entries = num_vco_entries;
+ pll->vco_param = vco_param;
+
+ parent_rate = __get_rate(parent_name);
+ if (WARN_ON(!parent_rate))
+ goto err_clk_register;
+
+ rate_index = pll_get_rate_index(pll, rate);
+ if (WARN_ON(rate_index < 0))
+ goto err_clk_register;
+
+ ret = pll_set_rate(pll, rate_index, parent_rate);
+ if (WARN_ON(ret))
+ goto err_clk_register;
+ }
+
+ clk = clk_register(NULL, &pll->hw);
+ if (WARN_ON(IS_ERR(clk)))
+ goto err_clk_register;
+
+ pll->clk_data.clk_num = 1;
+ pll->clk_data.clks = &clk;
+
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get,
+ &pll->clk_data);
+ if (WARN_ON(ret))
+ goto err_clk_add;
+
+ return;
+
+err_clk_add:
+ clk_unregister(clk);
+err_clk_register:
+ if (pll->asiu_base)
+ iounmap(pll->asiu_base);
+err_asiu_iomap:
+ iounmap(pll->pwr_base);
+err_pwr_iomap:
+ iounmap(pll->pll_base);
+err_pll_iomap:
+ kfree(pll);
+}
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
new file mode 100644
index 0000000..4aa0479
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLK_IPROC_H
+#define _CLK_IPROC_H
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/clk-provider.h>
+
+#define IPROC_CLK_NAME_LEN 25
+#define IPROC_CLK_INVALID_OFFSET 0xffffffff
+#define bit_mask(width) ((1 << (width)) - 1)
+
+/* clock should not be disabled at runtime */
+#define IPROC_CLK_AON BIT(0)
+
+/* PLL requires gating through ASIU */
+#define IPROC_CLK_PLL_ASIU BIT(1)
+
+/* PLL has fractional part of the NDIV */
+#define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
+
+/*
+ * Parameters for VCO frequency configuration
+ *
+ * VCO frequency =
+ * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
+ */
+struct iproc_pll_vco_freq_param {
+ unsigned long rate;
+ unsigned int ndiv_int;
+ unsigned int ndiv_frac;
+ unsigned int pdiv;
+};
+
+struct iproc_clk_reg_op {
+ unsigned int offset;
+ unsigned int shift;
+ unsigned int width;
+};
+
+/*
+ * Clock gating control at the top ASIU level
+ */
+struct iproc_asiu_gate {
+ unsigned int offset;
+ unsigned int en_shift;
+};
+
+/*
+ * Control of powering on/off of a PLL
+ *
+ * Before powering off a PLL, input isolation (ISO) needs to be enabled
+ */
+struct iproc_pll_aon_pwr_ctrl {
+ unsigned int offset;
+ unsigned int pwr_width;
+ unsigned int pwr_shift;
+ unsigned int iso_shift;
+};
+
+/*
+ * Control of the PLL reset, with Ki, Kp, and Ka parameters
+ */
+struct iproc_pll_reset_ctrl {
+ unsigned int offset;
+ unsigned int reset_shift;
+ unsigned int p_reset_shift;
+ unsigned int ki_shift;
+ unsigned int ki_width;
+ unsigned int kp_shift;
+ unsigned int kp_width;
+ unsigned int ka_shift;
+ unsigned int ka_width;
+};
+
+struct iproc_pll_vco_ctrl {
+ unsigned int u_offset;
+ unsigned int l_offset;
+};
+
+/*
+ * Main PLL control parameters
+ */
+struct iproc_pll_ctrl {
+ unsigned long flags;
+ struct iproc_pll_aon_pwr_ctrl aon;
+ struct iproc_asiu_gate asiu;
+ struct iproc_pll_reset_ctrl reset;
+ struct iproc_clk_reg_op ndiv_int;
+ struct iproc_clk_reg_op ndiv_frac;
+ struct iproc_clk_reg_op pdiv;
+ struct iproc_pll_vco_ctrl vco_ctrl;
+ struct iproc_clk_reg_op status;
+};
+
+/*
+ * Controls enabling/disabling a PLL derived clock
+ */
+struct iproc_clk_enable_ctrl {
+ unsigned int offset;
+ unsigned int enable_shift;
+ unsigned int hold_shift;
+ unsigned int bypass_shift;
+};
+
+/*
+ * Main clock control parameters for clocks derived from the PLLs
+ */
+struct iproc_clk_ctrl {
+ unsigned int channel;
+ unsigned long flags;
+ struct iproc_clk_enable_ctrl enable;
+ struct iproc_clk_reg_op mdiv;
+};
+
+/*
+ * Divisor of the ASIU clocks
+ */
+struct iproc_asiu_div {
+ unsigned int offset;
+ unsigned int en_shift;
+ unsigned int high_shift;
+ unsigned int high_width;
+ unsigned int low_shift;
+ unsigned int low_width;
+};
+
+extern void __init iproc_armpll_setup(struct device_node *node);
+extern void __init iproc_pll_setup(struct device_node *node,
+ const struct iproc_pll_ctrl *ctrl,
+ const struct iproc_pll_vco_freq_param *vco_param,
+ unsigned int num_freqs);
+extern void __init iproc_clk_setup(struct device_node *node,
+ const struct iproc_clk_ctrl *ctrl, unsigned int num_clks);
+extern void __init iproc_asiu_setup(struct device_node *node,
+ const struct iproc_asiu_div *div,
+ const struct iproc_asiu_gate *gate, unsigned int num_clks);
+
+#endif /* _CLK_IPROC_H */
--
1.7.9.5
On Thu, Dec 4, 2014 at 1:43 PM, Ray Jui <[email protected]> wrote:
> This adds basic and generic support for various iProc PLLs and clocks
> including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.
>
> SoCs under the iProc architecture can define their specific register
> offsets and clock parameters for their PLL and clock controllers. These
> parameters can be passed as arugments into the generic iProc PLL and
> clock setup functions
>
> Derived from code originally provided by Jonathan Richardson
> <[email protected]>
>
> Signed-off-by: Ray Jui <[email protected]>
> Reviewed-by: Scott Branden <[email protected]>
> ---
> drivers/clk/Makefile | 2 +-
> drivers/clk/bcm/Kconfig | 9 +
> drivers/clk/bcm/Makefile | 1 +
> drivers/clk/bcm/clk-iproc-armpll.c | 286 +++++++++++++++++++++
> drivers/clk/bcm/clk-iproc-asiu.c | 275 ++++++++++++++++++++
> drivers/clk/bcm/clk-iproc-clk.c | 238 ++++++++++++++++++
> drivers/clk/bcm/clk-iproc-pll.c | 483 ++++++++++++++++++++++++++++++++++++
> drivers/clk/bcm/clk-iproc.h | 155 ++++++++++++
> 8 files changed, 1448 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
> create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
> create mode 100644 drivers/clk/bcm/clk-iproc-clk.c
> create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
> create mode 100644 drivers/clk/bcm/clk-iproc.h
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index d5fba5b..eff0213 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -41,7 +41,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
> obj-$(CONFIG_COMMON_CLK_AT91) += at91/
> -obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
> +obj-$(CONFIG_ARCH_BCM) += bcm/
> obj-$(CONFIG_ARCH_BERLIN) += berlin/
> obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
> obj-$(CONFIG_ARCH_HIP04) += hisilicon/
It may be best to move the above change into its own commit.
> diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
> index 75506e5..66b5b7f 100644
> --- a/drivers/clk/bcm/Kconfig
> +++ b/drivers/clk/bcm/Kconfig
> @@ -7,3 +7,12 @@ config CLK_BCM_KONA
> Enable common clock framework support for Broadcom SoCs
> using "Kona" style clock control units, including those
> in the BCM281xx and BCM21664 families.
> +
> +config COMMON_CLK_IPROC
> + bool "Broadcom iProc clock support"
> + depends on ARCH_BCM_IPROC
> + depends on COMMON_CLK
> + default y
> + help
> + Enable common clock framework support for Broadcom SoCs
> + based on the "iProc" architecture
> diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
> index 6297d05..6926636 100644
> --- a/drivers/clk/bcm/Makefile
> +++ b/drivers/clk/bcm/Makefile
> @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
> obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
> obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
> obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
> +obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-clk.o clk-iproc-asiu.o
> diff --git a/drivers/clk/bcm/clk-iproc-armpll.c b/drivers/clk/bcm/clk-iproc-armpll.c
> new file mode 100644
> index 0000000..ec9b130
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-iproc-armpll.c
> @@ -0,0 +1,286 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/clkdev.h>
> +#include <linux/of_address.h>
> +
> +#define IPROC_CLK_MAX_FREQ_POLICY 0x3
> +#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
> +#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
> +#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
> +
> +#define IPROC_CLK_PLLARMA_OFFSET 0xc00
> +#define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
> +#define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
> +#define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
> +#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
> +#define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
> +
> +#define IPROC_CLK_PLLARMB_OFFSET 0xc04
> +#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
> +
> +#define IPROC_CLK_PLLARMC_OFFSET 0xc08
> +#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
> +#define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
> +
> +#define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
> +#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
> +
> +#define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
> +#define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
> +#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
> +#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
> +#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff
> +
> +#define IPROC_CLK_ARM_DIV_OFFSET 0xe00
> +#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
> +#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf
> +
> +#define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
> +#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
> +#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
> +
> +enum iproc_arm_pll_fid {
> + ARM_PLL_FID_CRYSTAL_CLK = 0,
> + ARM_PLL_FID_SYS_CLK = 2,
> + ARM_PLL_FID_CH0_SLOW_CLK = 6,
> + ARM_PLL_FID_CH1_FAST_CLK = 7
> +};
> +
> +struct iproc_arm_pll {
> + struct clk_hw hw;
> + void __iomem *base;
> + struct clk_onecell_data clk_data;
> + unsigned long rate;
> +};
> +
> +#define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)
> +
> +static unsigned int __get_fid(struct iproc_arm_pll *pll)
> +{
> + u32 val;
> + unsigned int policy, fid, active_fid;
> +
> + val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
> + if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
> + policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
> + else
> + policy = 0;
> +
> + /* something is seriously wrong */
> + BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);
> +
> + val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
> + fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
> + IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;
> +
> + val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
> + active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
> + (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
> + if (fid != active_fid) {
> + pr_debug("%s: fid override %u->%u\n", __func__, fid,
> + active_fid);
> + fid = active_fid;
> + }
> +
> + pr_debug("%s: active fid: %u\n", __func__, fid);
> +
> + return fid;
> +}
> +
> +/*
> + * Determine the mdiv (post divider) based on the frequency ID being used.
> + * There are 4 sources that can be used to derive the output clock rate:
> + * - 25 MHz Crystal
> + * - System clock
> + * - PLL channel 0 (slow clock)
> + * - PLL channel 1 (fast clock)
> + */
> +static int __get_mdiv(struct iproc_arm_pll *pll)
> +{
> + unsigned int fid;
> + int mdiv;
> + u32 val;
> +
> + fid = __get_fid(pll);
> +
> + switch (fid) {
> + case ARM_PLL_FID_CRYSTAL_CLK:
> + case ARM_PLL_FID_SYS_CLK:
> + mdiv = 1;
> + break;
> +
> + case ARM_PLL_FID_CH0_SLOW_CLK:
> + val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
> + mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
> + if (mdiv == 0)
> + mdiv = 256;
> + break;
> +
> + case ARM_PLL_FID_CH1_FAST_CLK:
> + val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
> + mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
> + if (mdiv == 0)
> + mdiv = 256;
> + break;
> +
> + default:
> + mdiv = -EFAULT;
> + }
> +
> + return mdiv;
> +}
> +
> +static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
> +{
> + u32 val;
> + unsigned int ndiv_int, ndiv_frac, ndiv;
> +
> + val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
> + if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
> + /*
> + * offset mode is active. Read the ndiv from the PLLARM OFFSET
> + * register
> + */
> + ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
> + IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
> + if (ndiv_int == 0)
> + ndiv_int = 256;
> +
> + ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
> + } else {
> + /* offset mode not active */
> + val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
> + ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
> + IPROC_CLK_PLLARMA_NDIV_INT_MASK;
> + if (ndiv_int == 0)
> + ndiv_int = 1024;
> +
> + val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
> + ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
> + }
> +
> + ndiv = (ndiv_int << 20) | ndiv_frac;
> +
> + return ndiv;
> +}
> +
> +/*
> + * The output frequency of the ARM PLL is calculated based on the ARM PLL
> + * divider values:
> + * pdiv = ARM PLL pre-divider
> + * ndiv = ARM PLL multiplier
> + * mdiv = ARM PLL post divider
> + *
> + * The frequency is calculated by:
> + * ((ndiv * parent clock rate) / pdiv) / mdiv
> + */
> +static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
> + u32 val;
> + int mdiv;
> + u64 ndiv;
> + unsigned int pdiv;
> +
> + /* in bypass mode, use parent rate */
> + val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
> + if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
> + pll->rate = parent_rate;
> + return pll->rate;
> + }
> +
> + /* PLL needs to be locked */
> + val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
> + if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
> + pll->rate = 0;
> + return 0;
> + }
> +
> + pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
> + IPROC_CLK_PLLARMA_PDIV_MASK;
> + if (pdiv == 0)
> + pdiv = 16;
> +
> + ndiv = __get_ndiv(pll);
> + mdiv = __get_mdiv(pll);
> + if (mdiv <= 0) {
> + pll->rate = 0;
> + return 0;
> + }
> + pll->rate = (ndiv * parent_rate) >> 20;
> + pll->rate = (pll->rate / pdiv) / mdiv;
> +
> + pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
> + pll->rate, parent_rate);
> + pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
> + (unsigned int)(ndiv >> 20), pdiv, mdiv);
> +
> + return pll->rate;
> +}
> +
> +static const struct clk_ops iproc_arm_pll_ops = {
> + .recalc_rate = iproc_arm_pll_recalc_rate,
> +};
> +
> +void __init iproc_armpll_setup(struct device_node *node)
> +{
> + int ret;
> + struct clk *clk;
> + struct iproc_arm_pll *pll;
> + struct clk_init_data init;
> + const char *parent_name;
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (WARN_ON(!pll))
> + return;
> +
> + pll->base = of_iomap(node, 0);
> + if (WARN_ON(!pll->base))
> + goto err_free_pll;
> +
> + init.name = node->name;
> + init.ops = &iproc_arm_pll_ops;
> + init.flags = 0;
> + parent_name = of_clk_get_parent_name(node, 0);
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> + pll->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll->hw);
> + if (WARN_ON(IS_ERR(clk)))
> + goto err_iounmap;
> +
> + pll->clk_data.clk_num = 1;
> + pll->clk_data.clks = &clk;
> +
> + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data);
> + if (WARN_ON(ret))
> + goto err_clk_unregister;
> +
> + return;
> +
> +err_clk_unregister:
> + clk_unregister(clk);
> +err_iounmap:
> + iounmap(pll->base);
> +err_free_pll:
> + kfree(pll);
> +}
> diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
> new file mode 100644
> index 0000000..ab86b8c
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-iproc-asiu.c
> @@ -0,0 +1,275 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/clkdev.h>
> +#include <linux/of_address.h>
> +#include <linux/delay.h>
> +
> +#include "clk-iproc.h"
> +
> +struct iproc_asiu;
> +
> +struct iproc_asiu_clk {
> + struct clk_hw hw;
> + const char *name;
> + struct iproc_asiu *asiu;
> + unsigned long rate;
> + struct iproc_asiu_div div;
> + struct iproc_asiu_gate gate;
> +};
> +
> +struct iproc_asiu {
> + void __iomem *div_base;
> + void __iomem *gate_base;
> +
> + struct clk_onecell_data clk_data;
> + struct iproc_asiu_clk *clks;
> +};
> +
> +#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
> +
> +static int iproc_asiu_clk_enable(struct clk_hw *hw)
> +{
> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
> + struct iproc_asiu *asiu = clk->asiu;
> + u32 val;
> +
> + /* some clocks at the ASIU level are always enabled */
> + if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
> + return 0;
> +
> + val = readl(asiu->gate_base + clk->gate.offset);
> + val |= (1 << clk->gate.en_shift);
> + writel(val, asiu->gate_base + clk->gate.offset);
> +
> + return 0;
> +}
> +
> +static void iproc_asiu_clk_disable(struct clk_hw *hw)
> +{
> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
> + struct iproc_asiu *asiu = clk->asiu;
> + u32 val;
> +
> + /* some clocks at the ASIU level are always enabled */
> + if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
> + return;
> +
> + val = readl(asiu->gate_base + clk->gate.offset);
> + val &= ~(1 << clk->gate.en_shift);
> + writel(val, asiu->gate_base + clk->gate.offset);
> +}
> +
> +static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
> + struct iproc_asiu *asiu = clk->asiu;
> + u32 val;
> + unsigned int div_h, div_l;
> +
> + if (parent_rate == 0) {
> + clk->rate = 0;
> + return 0;
> + }
> +
> + /* if clock divisor is not enabled, simply return parent rate */
> + val = readl(asiu->div_base + clk->div.offset);
> + if ((val & (1 << clk->div.en_shift)) == 0) {
> + clk->rate = parent_rate;
> + return parent_rate;
> + }
> +
> + /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
> + div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
> + div_h++;
> + div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
> + div_l++;
> +
> + clk->rate = parent_rate / (div_h + div_l);
> + pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
> + __func__, clk->rate, parent_rate, div_h, div_l);
> +
> + return clk->rate;
> +}
> +
> +static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *parent_rate)
> +{
> + unsigned int div;
> +
> + if (rate == 0 || *parent_rate == 0)
> + return -EINVAL;
> +
> + if (rate == *parent_rate)
> + return *parent_rate;
> +
> + div = DIV_ROUND_UP(*parent_rate, rate);
> + if (div < 2)
> + return *parent_rate;
> +
> + return *parent_rate / div;
> +}
> +
> +static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
> + struct iproc_asiu *asiu = clk->asiu;
> + unsigned int div, div_h, div_l;
> + u32 val;
> +
> + if (rate == 0 || parent_rate == 0)
> + return -EINVAL;
> +
> + /* simply disable the divisor if one wants the same rate as parent */
> + if (rate == parent_rate) {
> + val = readl(asiu->div_base + clk->div.offset);
> + val &= ~(1 << clk->div.en_shift);
> + writel(val, asiu->div_base + clk->div.offset);
> + return 0;
> + }
> +
> + div = DIV_ROUND_UP(parent_rate, rate);
> + if (div < 2)
> + return -EINVAL;
> +
> + div_h = div_l = div >> 1;
> + div_h--;
> + div_l--;
> +
> + val = readl(asiu->div_base + clk->div.offset);
> + val |= 1 << clk->div.en_shift;
> + if (div_h) {
> + val &= ~(bit_mask(clk->div.high_width)
> + << clk->div.high_shift);
> + val |= div_h << clk->div.high_shift;
> + } else {
> + val &= ~(bit_mask(clk->div.high_width)
> + << clk->div.high_shift);
> + }
> + if (div_l) {
> + val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
> + val |= div_l << clk->div.low_shift;
> + } else {
> + val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
> + }
> + writel(val, asiu->div_base + clk->div.offset);
> +
> + return 0;
> +}
> +
> +static const struct clk_ops iproc_asiu_ops = {
> + .enable = iproc_asiu_clk_enable,
> + .disable = iproc_asiu_clk_disable,
> + .recalc_rate = iproc_asiu_clk_recalc_rate,
> + .round_rate = iproc_asiu_clk_round_rate,
> + .set_rate = iproc_asiu_clk_set_rate,
> +};
> +
> +void __init iproc_asiu_setup(struct device_node *node,
> + const struct iproc_asiu_div *div,
> + const struct iproc_asiu_gate *gate, unsigned int num_clks)
> +{
> + int i, ret;
> + struct iproc_asiu *asiu;
> +
> + if (WARN_ON(!gate || !div))
> + return;
> +
> + asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
> + if (WARN_ON(!asiu))
> + return;
> +
> + asiu->clk_data.clk_num = num_clks;
> + asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks),
> + GFP_KERNEL);
> + if (WARN_ON(!asiu->clk_data.clks))
> + goto err_clks;
> +
> + asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
> + if (WARN_ON(!asiu->clks))
> + goto err_asiu_clks;
> +
> + asiu->div_base = of_iomap(node, 0);
> + if (WARN_ON(!asiu->div_base))
> + goto err_iomap_div;
> +
> + asiu->gate_base = of_iomap(node, 1);
> + if (WARN_ON(!asiu->gate_base))
> + goto err_iomap_gate;
> +
> + for (i = 0; i < num_clks; i++) {
> + struct clk_init_data init;
> + struct clk *clk;
> + const char *parent_name;
> + struct iproc_asiu_clk *asiu_clk;
> + const char *clk_name;
> +
> + clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
> + if (WARN_ON(!clk_name))
> + goto err_clk_register;
> +
> + ret = of_property_read_string_index(node, "clock-output-names",
> + i, &clk_name);
> + if (WARN_ON(ret))
> + goto err_clk_register;
> +
> + asiu_clk = &asiu->clks[i];
> + asiu_clk->name = clk_name;
> + asiu_clk->asiu = asiu;
> + asiu_clk->div = div[i];
> + asiu_clk->gate = gate[i];
> + init.name = clk_name;
> + init.ops = &iproc_asiu_ops;
> + init.flags = 0;
> + parent_name = of_clk_get_parent_name(node, 0);
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> + asiu_clk->hw.init = &init;
> +
> + clk = clk_register(NULL, &asiu_clk->hw);
> + if (WARN_ON(IS_ERR(clk)))
> + goto err_clk_register;
> + asiu->clk_data.clks[i] = clk;
> + }
> +
> + ret = of_clk_add_provider(node, of_clk_src_onecell_get,
> + &asiu->clk_data);
> + if (WARN_ON(ret))
> + goto err_clk_register;
> +
> + return;
> +
> +err_clk_register:
> + for (i = 0; i < num_clks; i++)
> + kfree(asiu->clks[i].name);
> + iounmap(asiu->gate_base);
> +
> +err_iomap_gate:
> + iounmap(asiu->div_base);
> +
> +err_iomap_div:
> + kfree(asiu->clks);
> +
> +err_asiu_clks:
> + kfree(asiu->clk_data.clks);
> +
> +err_clks:
> + kfree(asiu);
> +}
> diff --git a/drivers/clk/bcm/clk-iproc-clk.c b/drivers/clk/bcm/clk-iproc-clk.c
> new file mode 100644
> index 0000000..be3c42c
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-iproc-clk.c
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/clkdev.h>
> +#include <linux/of_address.h>
> +#include <linux/delay.h>
> +
> +#include "clk-iproc.h"
> +
> +struct iproc_pll;
> +
> +struct iproc_clk {
> + struct clk_hw hw;
> + const char *name;
> + struct iproc_pll *pll;
> + unsigned long rate;
> + const struct iproc_clk_ctrl *ctrl;
> +};
> +
> +struct iproc_pll {
> + void __iomem *base;
> + struct clk_onecell_data clk_data;
> + struct iproc_clk *clks;
> +};
> +
> +#define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw)
> +
> +static int iproc_clk_enable(struct clk_hw *hw)
> +{
> + struct iproc_clk *clk = to_iproc_clk(hw);
> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
> + struct iproc_pll *pll = clk->pll;
> + u32 val;
> +
> + /* channel enable is active low */
> + val = readl(pll->base + ctrl->enable.offset);
> + val &= ~(1 << ctrl->enable.enable_shift);
> + writel(val, pll->base + ctrl->enable.offset);
> +
> + /* also make sure channel is not held */
> + val = readl(pll->base + ctrl->enable.offset);
> + val &= ~(1 << ctrl->enable.hold_shift);
> + writel(val, pll->base + ctrl->enable.offset);
> +
> + return 0;
> +}
> +
> +static void iproc_clk_disable(struct clk_hw *hw)
> +{
> + struct iproc_clk *clk = to_iproc_clk(hw);
> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
> + struct iproc_pll *pll = clk->pll;
> + u32 val;
> +
> + if (ctrl->flags & IPROC_CLK_AON)
> + return;
> +
> + val = readl(pll->base + ctrl->enable.offset);
> + val |= 1 << ctrl->enable.enable_shift;
> + writel(val, pll->base + ctrl->enable.offset);
> +}
> +
> +static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct iproc_clk *clk = to_iproc_clk(hw);
> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
> + struct iproc_pll *pll = clk->pll;
> + u32 val;
> + unsigned int mdiv;
> +
> + if (parent_rate == 0)
> + return 0;
> +
> + val = readl(pll->base + ctrl->mdiv.offset);
> + mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width);
> + if (mdiv == 0)
> + mdiv = 256;
> +
> + clk->rate = parent_rate / mdiv;
> +
> + return clk->rate;
> +}
> +
> +static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *parent_rate)
> +{
> + unsigned int div;
> +
> + if (rate == 0 || *parent_rate == 0)
> + return -EINVAL;
> +
> + if (rate == *parent_rate)
> + return *parent_rate;
> +
> + div = DIV_ROUND_UP(*parent_rate, rate);
> + if (div < 2)
> + return *parent_rate;
> +
> + if (div > 256)
> + div = 256;
> +
> + return *parent_rate / div;
> +}
> +
> +static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct iproc_clk *clk = to_iproc_clk(hw);
> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
> + struct iproc_pll *pll = clk->pll;
> + u32 val;
> + unsigned int div;
> +
> + if (rate == 0 || parent_rate == 0)
> + return -EINVAL;
> +
> + div = DIV_ROUND_UP(parent_rate, rate);
> + if (div > 256)
> + return -EINVAL;
> +
> + val = readl(pll->base + ctrl->mdiv.offset);
> + if (div == 256) {
> + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
> + } else {
> + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
> + val |= div << ctrl->mdiv.shift;
> + }
> + writel(val, pll->base + ctrl->mdiv.offset);
> + clk->rate = parent_rate / div;
> +
> + return 0;
> +}
> +
> +static const struct clk_ops iproc_clk_ops = {
> + .enable = iproc_clk_enable,
> + .disable = iproc_clk_disable,
> + .recalc_rate = iproc_clk_recalc_rate,
> + .round_rate = iproc_clk_round_rate,
> + .set_rate = iproc_clk_set_rate,
> +};
> +
> +void __init iproc_clk_setup(struct device_node *node,
> + const struct iproc_clk_ctrl *ctrl, unsigned int num_clks)
> +{
> + int i, ret;
> + struct iproc_pll *pll;
> +
> + if (WARN_ON(!ctrl))
> + return;
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (WARN_ON(!pll))
> + return;
> +
> + pll->clk_data.clk_num = num_clks;
> + pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks),
> + GFP_KERNEL);
> + if (WARN_ON(!pll->clk_data.clks))
> + goto err_clks;
> +
> + pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL);
> + if (WARN_ON(!pll->clks))
> + goto err_pll_clks;
> +
> + pll->base = of_iomap(node, 0);
> + if (WARN_ON(!pll->base))
> + goto err_iomap;
> +
> + for (i = 0; i < num_clks; i++) {
> + struct clk_init_data init;
> + struct clk *clk;
> + const char *parent_name;
> + struct iproc_clk *iclk;
> + const char *clk_name;
> +
> + clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
> + if (WARN_ON(!clk_name))
> + goto err_clk_register;
> +
> + ret = of_property_read_string_index(node, "clock-output-names",
> + i, &clk_name);
> + if (WARN_ON(ret))
> + goto err_clk_register;
> +
> + iclk = &pll->clks[i];
> + iclk->name = clk_name;
> + iclk->pll = pll;
> + iclk->ctrl = &ctrl[i];
> + init.name = clk_name;
> + init.ops = &iproc_clk_ops;
> + init.flags = 0;
> + parent_name = of_clk_get_parent_name(node, 0);
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> + iclk->hw.init = &init;
> +
> + clk = clk_register(NULL, &iclk->hw);
> + if (WARN_ON(IS_ERR(clk)))
> + goto err_clk_register;
> + pll->clk_data.clks[i] = clk;
> + }
> +
> + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data);
> + if (WARN_ON(ret))
> + goto err_clk_register;
> +
> + return;
> +
> +err_clk_register:
> + for (i = 0; i < num_clks; i++)
> + kfree(pll->clks[i].name);
> + iounmap(pll->base);
> +
> +err_iomap:
> + kfree(pll->clks);
> +
> +err_pll_clks:
> + kfree(pll->clk_data.clks);
> +
> +err_clks:
> + kfree(pll);
> +}
> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
> new file mode 100644
> index 0000000..cd3bd38
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-iproc-pll.c
> @@ -0,0 +1,483 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/clkdev.h>
> +#include <linux/of_address.h>
> +#include <linux/delay.h>
> +
> +#include "clk-iproc.h"
> +
> +#define PLL_VCO_HIGH_SHIFT 19
> +#define PLL_VCO_LOW_SHIFT 30
> +
> +/* number of delay loops waiting for PLL to lock */
> +#define LOCK_DELAY 100
> +
> +/* number of VCO frequency bands */
> +#define NUM_FREQ_BANDS 8
> +
> +#define NUM_KP_BANDS 3
> +enum kp_band {
> + KP_BAND_MID = 0,
> + KP_BAND_HIGH,
> + KP_BAND_HIGH_HIGH
> +};
> +
> +static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = {
> + { 5, 6, 6, 7, 7, 8, 9, 10 },
> + { 4, 4, 5, 5, 6, 7, 8, 9 },
> + { 4, 5, 5, 6, 7, 8, 9, 10 },
> +};
> +
> +static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = {
> + { 10000000, 12500000 },
> + { 12500000, 15000000 },
> + { 15000000, 20000000 },
> + { 20000000, 25000000 },
> + { 25000000, 50000000 },
> + { 50000000, 75000000 },
> + { 75000000, 100000000 },
> + { 100000000, 125000000 },
> +};
> +
> +enum vco_freq_range {
> + VCO_LOW = 700000000U,
> + VCO_MID = 1200000000U,
> + VCO_HIGH = 2200000000U,
> + VCO_HIGH_HIGH = 3100000000U,
> + VCO_MAX = 4000000000U,
> +};
> +
> +struct iproc_pll {
> + struct clk_hw hw;
> + void __iomem *pll_base;
> + void __iomem *pwr_base;
> + void __iomem *asiu_base;
> + struct clk_onecell_data clk_data;
> + const char *name;
> + const struct iproc_pll_ctrl *ctrl;
> + const struct iproc_pll_vco_freq_param *vco_param;
> + unsigned int num_vco_entries;
> + unsigned long rate;
> +};
> +
> +#define to_iproc_pll(hw) container_of(hw, struct iproc_pll, hw)
> +
> +/*
> + * Get the clock rate based on name
> + */
> +static unsigned long __get_rate(const char *clk_name)
> +{
> + struct clk *clk;
> +
> + clk = __clk_lookup(clk_name);
> + if (!clk) {
> + pr_err("%s: unable to find clock by name: %s\n", __func__,
> + clk_name);
> + return 0;
> + }
> +
> + return clk_get_rate(clk);
> +}
> +
> +/*
> + * Based on the target frequency, find a match from the VCO frequency parameter
> + * table and return its index
> + */
> +static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate)
> +{
> + int i;
> +
> + for (i = 0; i < pll->num_vco_entries; i++)
> + if (target_rate == pll->vco_param[i].rate)
> + break;
> +
> + if (i >= pll->num_vco_entries)
> + return -EINVAL;
> +
> + return i;
> +}
> +
> +static int get_kp(unsigned long ref_freq, enum kp_band kp_index)
> +{
> + int i;
> +
> + if (ref_freq < ref_freq_table[0][0])
> + return -EINVAL;
> +
> + for (i = 0; i < NUM_FREQ_BANDS; i++) {
> + if (ref_freq >= ref_freq_table[i][0] &&
> + ref_freq < ref_freq_table[i][1])
> + return kp_table[kp_index][i];
> + }
> + return -EINVAL;
> +}
> +
> +static int pll_wait_for_lock(struct iproc_pll *pll)
> +{
> + int i;
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> +
> + for (i = 0; i < LOCK_DELAY; i++) {
> + u32 val = readl(pll->pll_base + ctrl->status.offset);
> +
> + if (val & (1 << ctrl->status.shift))
> + return 0;
> + udelay(10);
> + }
> +
> + return -EIO;
> +}
> +
> +static void __pll_disable(struct iproc_pll *pll)
> +{
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> + u32 val;
> +
> + if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
> + val = readl(pll->asiu_base + ctrl->asiu.offset);
> + val &= ~(1 << ctrl->asiu.en_shift);
> + writel(val, pll->asiu_base + ctrl->asiu.offset);
> + }
> +
> + /* latch input value so core power can be shut down */
> + val = readl(pll->pwr_base + ctrl->aon.offset);
> + val |= (1 << ctrl->aon.iso_shift);
> + writel(val, pll->pwr_base + ctrl->aon.offset);
> +
> + /* power down the core */
> + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
> + writel(val, pll->pwr_base + ctrl->aon.offset);
> +}
> +
> +static int __pll_enable(struct iproc_pll *pll)
> +{
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> + u32 val;
> +
> + /* power up the PLL and make sure it's not latched */
> + val = readl(pll->pwr_base + ctrl->aon.offset);
> + val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
> + val &= ~(1 << ctrl->aon.iso_shift);
> + writel(val, pll->pwr_base + ctrl->aon.offset);
> +
> + /* certain PLLs also need to be ungated from the ASIU top level */
> + if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
> + val = readl(pll->asiu_base + ctrl->asiu.offset);
> + val |= (1 << ctrl->asiu.en_shift);
> + writel(val, pll->asiu_base + ctrl->asiu.offset);
> + }
> +
> + return 0;
> +}
> +
> +static void __pll_put_in_reset(struct iproc_pll *pll)
> +{
> + u32 val;
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
> +
> + val = readl(pll->pll_base + reset->offset);
> + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
> + writel(val, pll->pll_base + reset->offset);
> +}
> +
> +static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
> + unsigned int ka, unsigned int ki)
> +{
> + u32 val;
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
> +
> + val = readl(pll->pll_base + reset->offset);
> + val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
> + bit_mask(reset->kp_width) << reset->kp_shift |
> + bit_mask(reset->ka_width) << reset->ka_shift);
> + val |= ki << reset->ki_shift | kp << reset->kp_shift |
> + ka << reset->ka_shift;
> + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
> + writel(val, pll->pll_base + reset->offset);
> +}
> +
> +static int pll_set_rate(struct iproc_pll *pll, unsigned int rate_index,
> + unsigned long parent_rate)
> +{
> + const struct iproc_pll_vco_freq_param *vco =
> + &pll->vco_param[rate_index];
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> + int ka = 0, ki, kp, ret;
> + unsigned long rate = vco->rate;
> + u32 val;
> + enum kp_band kp_index;
> + unsigned long ref_freq;
> +
> + /*
> + * reference frequency = parent frequency / PDIV
> + * If PDIV = 0, then it becomes a multiplier (x2)
> + */
> + if (vco->pdiv == 0)
> + ref_freq = parent_rate * 2;
> + else
> + ref_freq = parent_rate / vco->pdiv;
> +
> + /* determine Ki and Kp index based on target VCO frequency */
> + if (rate >= VCO_LOW && rate < VCO_HIGH) {
> + ki = 4;
> + kp_index = KP_BAND_MID;
> + } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) {
> + ki = 3;
> + kp_index = KP_BAND_HIGH;
> + } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) {
> + ki = 3;
> + kp_index = KP_BAND_HIGH_HIGH;
> + } else {
> + pr_err("%s: pll: %s has invalid rate: %lu\n", __func__,
> + pll->name, rate);
> + return -EINVAL;
> + }
> +
> + kp = get_kp(ref_freq, kp_index);
> + if (kp < 0) {
> + pr_err("%s: pll: %s has invalid kp\n", __func__, pll->name);
> + return kp;
> + }
> +
> + ret = __pll_enable(pll);
> + if (ret) {
> + pr_err("%s: pll: %s fails to enable\n", __func__, pll->name);
> + return ret;
> + }
> +
> + /* put PLL in reset */
> + __pll_put_in_reset(pll);
> +
> + writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset);
> + val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset);
> +
> + if (rate >= VCO_LOW && rate < VCO_MID)
> + val |= (1 << PLL_VCO_LOW_SHIFT);
> +
> + if (rate < VCO_HIGH)
> + val &= ~(1 << PLL_VCO_HIGH_SHIFT);
> + else
> + val |= (1 << PLL_VCO_HIGH_SHIFT);
> +
> + writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset);
> +
> + /* program integer part of NDIV */
> + val = readl(pll->pll_base + ctrl->ndiv_int.offset);
> + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift);
> + val |= vco->ndiv_int << ctrl->ndiv_int.shift;
> + writel(val, pll->pll_base + ctrl->ndiv_int.offset);
> +
> + /* program fractional part of NDIV */
> + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
> + val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
> + val &= ~(bit_mask(ctrl->ndiv_frac.width) <<
> + ctrl->ndiv_frac.shift);
> + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift;
> + writel(val, pll->pll_base + ctrl->ndiv_frac.offset);
> + }
> +
> + /* program PDIV */
> + val = readl(pll->pll_base + ctrl->pdiv.offset);
> + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift);
> + val |= vco->pdiv << ctrl->pdiv.shift;
> + writel(val, pll->pll_base + ctrl->pdiv.offset);
> +
> + __pll_bring_out_reset(pll, kp, ka, ki);
> +
> + ret = pll_wait_for_lock(pll);
> + if (ret < 0) {
> + pr_err("%s: pll: %s failed to lock\n", __func__, pll->name);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int iproc_pll_enable(struct clk_hw *hw)
> +{
> + struct iproc_pll *pll = to_iproc_pll(hw);
> +
> + return __pll_enable(pll);
> +}
> +
> +static void iproc_pll_disable(struct clk_hw *hw)
> +{
> + struct iproc_pll *pll = to_iproc_pll(hw);
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> +
> + if (ctrl->flags & IPROC_CLK_AON)
> + return;
> +
> + __pll_disable(pll);
> +}
> +
> +static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct iproc_pll *pll = to_iproc_pll(hw);
> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
> + u32 val;
> + u64 ndiv;
> + unsigned int ndiv_int, ndiv_frac, pdiv;
> +
> + if (parent_rate == 0)
> + return 0;
> +
> + /* PLL needs to be locked */
> + val = readl(pll->pll_base + ctrl->status.offset);
> + if ((val & (1 << ctrl->status.shift)) == 0) {
> + pll->rate = 0;
> + return 0;
> + }
> +
> + /*
> + * PLL output frequency =
> + *
> + * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv)
> + */
> + val = readl(pll->pll_base + ctrl->ndiv_int.offset);
> + ndiv_int = (val >> ctrl->ndiv_int.shift) &
> + bit_mask(ctrl->ndiv_int.width);
> + ndiv = ndiv_int << ctrl->ndiv_int.shift;
> +
> + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
> + val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
> + ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
> + bit_mask(ctrl->ndiv_frac.width);
> +
> + if (ndiv_frac != 0)
> + ndiv = (ndiv_int << ctrl->ndiv_int.shift) | ndiv_frac;
> + }
> +
> + val = readl(pll->pll_base + ctrl->pdiv.offset);
> + pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
> +
> + pll->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
> +
> + if (pdiv == 0)
> + pll->rate *= 2;
> + else
> + pll->rate /= pdiv;
> +
> + return pll->rate;
> +}
> +
> +static const struct clk_ops iproc_pll_ops = {
> + .enable = iproc_pll_enable,
> + .disable = iproc_pll_disable,
> + .recalc_rate = iproc_pll_recalc_rate,
> +};
> +
> +void __init iproc_pll_setup(struct device_node *node,
> + const struct iproc_pll_ctrl *ctrl,
> + const struct iproc_pll_vco_freq_param *vco_param,
> + unsigned int num_vco_entries)
> +{
> + int ret;
> + struct clk *clk;
> + struct iproc_pll *pll;
> + struct clk_init_data init;
> + const char *parent_name;
> + unsigned int rate;
> +
> + if (WARN_ON(!ctrl))
> + return;
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (WARN_ON(!pll))
> + return;
> +
> + pll->pll_base = of_iomap(node, 0);
> + if (WARN_ON(!pll->pll_base))
> + goto err_pll_iomap;
> +
> + pll->pwr_base = of_iomap(node, 1);
> + if (WARN_ON(!pll->pwr_base))
> + goto err_pwr_iomap;
> +
> + /* some PLLs require gating control at the top ASIU level */
> + if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
> + pll->asiu_base = of_iomap(node, 2);
> + if (WARN_ON(!pll->asiu_base))
> + goto err_asiu_iomap;
> + }
> +
> + pll->ctrl = ctrl;
> + pll->name = node->name;
> + init.name = node->name;
> + init.ops = &iproc_pll_ops;
> + init.flags = 0;
> + parent_name = of_clk_get_parent_name(node, 0);
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> + pll->hw.init = &init;
> +
> + /* configure the PLL to the desired VCO frequency if specified */
> + ret = of_property_read_u32(node, "clock-frequency", &rate);
> + if (!ret) {
> + unsigned long parent_rate;
> + int rate_index;
> +
> + if (WARN_ON(!vco_param))
> + goto err_clk_register;
> +
> + pll->num_vco_entries = num_vco_entries;
> + pll->vco_param = vco_param;
> +
> + parent_rate = __get_rate(parent_name);
> + if (WARN_ON(!parent_rate))
> + goto err_clk_register;
> +
> + rate_index = pll_get_rate_index(pll, rate);
> + if (WARN_ON(rate_index < 0))
> + goto err_clk_register;
> +
> + ret = pll_set_rate(pll, rate_index, parent_rate);
> + if (WARN_ON(ret))
> + goto err_clk_register;
> + }
> +
> + clk = clk_register(NULL, &pll->hw);
> + if (WARN_ON(IS_ERR(clk)))
> + goto err_clk_register;
> +
> + pll->clk_data.clk_num = 1;
> + pll->clk_data.clks = &clk;
> +
> + ret = of_clk_add_provider(node, of_clk_src_onecell_get,
> + &pll->clk_data);
> + if (WARN_ON(ret))
> + goto err_clk_add;
> +
> + return;
> +
> +err_clk_add:
> + clk_unregister(clk);
> +err_clk_register:
> + if (pll->asiu_base)
> + iounmap(pll->asiu_base);
> +err_asiu_iomap:
> + iounmap(pll->pwr_base);
> +err_pwr_iomap:
> + iounmap(pll->pll_base);
> +err_pll_iomap:
> + kfree(pll);
> +}
> diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
> new file mode 100644
> index 0000000..4aa0479
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-iproc.h
> @@ -0,0 +1,155 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _CLK_IPROC_H
> +#define _CLK_IPROC_H
> +
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/spinlock.h>
> +#include <linux/slab.h>
> +#include <linux/device.h>
> +#include <linux/of.h>
> +#include <linux/clk-provider.h>
> +
> +#define IPROC_CLK_NAME_LEN 25
> +#define IPROC_CLK_INVALID_OFFSET 0xffffffff
> +#define bit_mask(width) ((1 << (width)) - 1)
> +
> +/* clock should not be disabled at runtime */
> +#define IPROC_CLK_AON BIT(0)
> +
> +/* PLL requires gating through ASIU */
> +#define IPROC_CLK_PLL_ASIU BIT(1)
> +
> +/* PLL has fractional part of the NDIV */
> +#define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
> +
> +/*
> + * Parameters for VCO frequency configuration
> + *
> + * VCO frequency =
> + * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
> + */
> +struct iproc_pll_vco_freq_param {
> + unsigned long rate;
> + unsigned int ndiv_int;
> + unsigned int ndiv_frac;
> + unsigned int pdiv;
> +};
> +
> +struct iproc_clk_reg_op {
> + unsigned int offset;
> + unsigned int shift;
> + unsigned int width;
> +};
> +
> +/*
> + * Clock gating control at the top ASIU level
> + */
> +struct iproc_asiu_gate {
> + unsigned int offset;
> + unsigned int en_shift;
> +};
> +
> +/*
> + * Control of powering on/off of a PLL
> + *
> + * Before powering off a PLL, input isolation (ISO) needs to be enabled
> + */
> +struct iproc_pll_aon_pwr_ctrl {
> + unsigned int offset;
> + unsigned int pwr_width;
> + unsigned int pwr_shift;
> + unsigned int iso_shift;
> +};
> +
> +/*
> + * Control of the PLL reset, with Ki, Kp, and Ka parameters
> + */
> +struct iproc_pll_reset_ctrl {
> + unsigned int offset;
> + unsigned int reset_shift;
> + unsigned int p_reset_shift;
> + unsigned int ki_shift;
> + unsigned int ki_width;
> + unsigned int kp_shift;
> + unsigned int kp_width;
> + unsigned int ka_shift;
> + unsigned int ka_width;
> +};
> +
> +struct iproc_pll_vco_ctrl {
> + unsigned int u_offset;
> + unsigned int l_offset;
> +};
> +
> +/*
> + * Main PLL control parameters
> + */
> +struct iproc_pll_ctrl {
> + unsigned long flags;
> + struct iproc_pll_aon_pwr_ctrl aon;
> + struct iproc_asiu_gate asiu;
> + struct iproc_pll_reset_ctrl reset;
> + struct iproc_clk_reg_op ndiv_int;
> + struct iproc_clk_reg_op ndiv_frac;
> + struct iproc_clk_reg_op pdiv;
> + struct iproc_pll_vco_ctrl vco_ctrl;
> + struct iproc_clk_reg_op status;
> +};
> +
> +/*
> + * Controls enabling/disabling a PLL derived clock
> + */
> +struct iproc_clk_enable_ctrl {
> + unsigned int offset;
> + unsigned int enable_shift;
> + unsigned int hold_shift;
> + unsigned int bypass_shift;
> +};
> +
> +/*
> + * Main clock control parameters for clocks derived from the PLLs
> + */
> +struct iproc_clk_ctrl {
> + unsigned int channel;
> + unsigned long flags;
> + struct iproc_clk_enable_ctrl enable;
> + struct iproc_clk_reg_op mdiv;
> +};
> +
> +/*
> + * Divisor of the ASIU clocks
> + */
> +struct iproc_asiu_div {
> + unsigned int offset;
> + unsigned int en_shift;
> + unsigned int high_shift;
> + unsigned int high_width;
> + unsigned int low_shift;
> + unsigned int low_width;
> +};
> +
> +extern void __init iproc_armpll_setup(struct device_node *node);
> +extern void __init iproc_pll_setup(struct device_node *node,
> + const struct iproc_pll_ctrl *ctrl,
> + const struct iproc_pll_vco_freq_param *vco_param,
> + unsigned int num_freqs);
> +extern void __init iproc_clk_setup(struct device_node *node,
> + const struct iproc_clk_ctrl *ctrl, unsigned int num_clks);
> +extern void __init iproc_asiu_setup(struct device_node *node,
> + const struct iproc_asiu_div *div,
> + const struct iproc_asiu_gate *gate, unsigned int num_clks);
> +
> +#endif /* _CLK_IPROC_H */
> --
> 1.7.9.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 12/6/2014 2:20 PM, Tim Kryger wrote:
> On Thu, Dec 4, 2014 at 1:43 PM, Ray Jui <[email protected]> wrote:
>> This adds basic and generic support for various iProc PLLs and clocks
>> including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.
>>
>> SoCs under the iProc architecture can define their specific register
>> offsets and clock parameters for their PLL and clock controllers. These
>> parameters can be passed as arugments into the generic iProc PLL and
>> clock setup functions
>>
>> Derived from code originally provided by Jonathan Richardson
>> <[email protected]>
>>
>> Signed-off-by: Ray Jui <[email protected]>
>> Reviewed-by: Scott Branden <[email protected]>
>> ---
>> drivers/clk/Makefile | 2 +-
>> drivers/clk/bcm/Kconfig | 9 +
>> drivers/clk/bcm/Makefile | 1 +
>> drivers/clk/bcm/clk-iproc-armpll.c | 286 +++++++++++++++++++++
>> drivers/clk/bcm/clk-iproc-asiu.c | 275 ++++++++++++++++++++
>> drivers/clk/bcm/clk-iproc-clk.c | 238 ++++++++++++++++++
>> drivers/clk/bcm/clk-iproc-pll.c | 483 ++++++++++++++++++++++++++++++++++++
>> drivers/clk/bcm/clk-iproc.h | 155 ++++++++++++
>> 8 files changed, 1448 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
>> create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
>> create mode 100644 drivers/clk/bcm/clk-iproc-clk.c
>> create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
>> create mode 100644 drivers/clk/bcm/clk-iproc.h
>>
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index d5fba5b..eff0213 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -41,7 +41,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
>> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
>> obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
>> obj-$(CONFIG_COMMON_CLK_AT91) += at91/
>> -obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
>> +obj-$(CONFIG_ARCH_BCM) += bcm/
>> obj-$(CONFIG_ARCH_BERLIN) += berlin/
>> obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
>> obj-$(CONFIG_ARCH_HIP04) += hisilicon/
>
> It may be best to move the above change into its own commit.
>
Okay. Will make this change along with other changes if required. Still
waiting for more code review comments at this point.
>> diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
>> index 75506e5..66b5b7f 100644
>> --- a/drivers/clk/bcm/Kconfig
>> +++ b/drivers/clk/bcm/Kconfig
>> @@ -7,3 +7,12 @@ config CLK_BCM_KONA
>> Enable common clock framework support for Broadcom SoCs
>> using "Kona" style clock control units, including those
>> in the BCM281xx and BCM21664 families.
>> +
>> +config COMMON_CLK_IPROC
>> + bool "Broadcom iProc clock support"
>> + depends on ARCH_BCM_IPROC
>> + depends on COMMON_CLK
>> + default y
>> + help
>> + Enable common clock framework support for Broadcom SoCs
>> + based on the "iProc" architecture
>> diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
>> index 6297d05..6926636 100644
>> --- a/drivers/clk/bcm/Makefile
>> +++ b/drivers/clk/bcm/Makefile
>> @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
>> obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
>> obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
>> obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
>> +obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-clk.o clk-iproc-asiu.o
>> diff --git a/drivers/clk/bcm/clk-iproc-armpll.c b/drivers/clk/bcm/clk-iproc-armpll.c
>> new file mode 100644
>> index 0000000..ec9b130
>> --- /dev/null
>> +++ b/drivers/clk/bcm/clk-iproc-armpll.c
>> @@ -0,0 +1,286 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/slab.h>
>> +#include <linux/err.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/of_address.h>
>> +
>> +#define IPROC_CLK_MAX_FREQ_POLICY 0x3
>> +#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
>> +#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
>> +#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
>> +
>> +#define IPROC_CLK_PLLARMA_OFFSET 0xc00
>> +#define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
>> +#define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
>> +#define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
>> +#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
>> +#define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
>> +
>> +#define IPROC_CLK_PLLARMB_OFFSET 0xc04
>> +#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
>> +
>> +#define IPROC_CLK_PLLARMC_OFFSET 0xc08
>> +#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
>> +#define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
>> +
>> +#define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
>> +#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
>> +
>> +#define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
>> +#define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
>> +#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
>> +#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
>> +#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff
>> +
>> +#define IPROC_CLK_ARM_DIV_OFFSET 0xe00
>> +#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
>> +#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf
>> +
>> +#define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
>> +#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
>> +#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
>> +
>> +enum iproc_arm_pll_fid {
>> + ARM_PLL_FID_CRYSTAL_CLK = 0,
>> + ARM_PLL_FID_SYS_CLK = 2,
>> + ARM_PLL_FID_CH0_SLOW_CLK = 6,
>> + ARM_PLL_FID_CH1_FAST_CLK = 7
>> +};
>> +
>> +struct iproc_arm_pll {
>> + struct clk_hw hw;
>> + void __iomem *base;
>> + struct clk_onecell_data clk_data;
>> + unsigned long rate;
>> +};
>> +
>> +#define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)
>> +
>> +static unsigned int __get_fid(struct iproc_arm_pll *pll)
>> +{
>> + u32 val;
>> + unsigned int policy, fid, active_fid;
>> +
>> + val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
>> + if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
>> + policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
>> + else
>> + policy = 0;
>> +
>> + /* something is seriously wrong */
>> + BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);
>> +
>> + val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
>> + fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
>> + IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;
>> +
>> + val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
>> + active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
>> + (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
>> + if (fid != active_fid) {
>> + pr_debug("%s: fid override %u->%u\n", __func__, fid,
>> + active_fid);
>> + fid = active_fid;
>> + }
>> +
>> + pr_debug("%s: active fid: %u\n", __func__, fid);
>> +
>> + return fid;
>> +}
>> +
>> +/*
>> + * Determine the mdiv (post divider) based on the frequency ID being used.
>> + * There are 4 sources that can be used to derive the output clock rate:
>> + * - 25 MHz Crystal
>> + * - System clock
>> + * - PLL channel 0 (slow clock)
>> + * - PLL channel 1 (fast clock)
>> + */
>> +static int __get_mdiv(struct iproc_arm_pll *pll)
>> +{
>> + unsigned int fid;
>> + int mdiv;
>> + u32 val;
>> +
>> + fid = __get_fid(pll);
>> +
>> + switch (fid) {
>> + case ARM_PLL_FID_CRYSTAL_CLK:
>> + case ARM_PLL_FID_SYS_CLK:
>> + mdiv = 1;
>> + break;
>> +
>> + case ARM_PLL_FID_CH0_SLOW_CLK:
>> + val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
>> + mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
>> + if (mdiv == 0)
>> + mdiv = 256;
>> + break;
>> +
>> + case ARM_PLL_FID_CH1_FAST_CLK:
>> + val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
>> + mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
>> + if (mdiv == 0)
>> + mdiv = 256;
>> + break;
>> +
>> + default:
>> + mdiv = -EFAULT;
>> + }
>> +
>> + return mdiv;
>> +}
>> +
>> +static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
>> +{
>> + u32 val;
>> + unsigned int ndiv_int, ndiv_frac, ndiv;
>> +
>> + val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
>> + if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
>> + /*
>> + * offset mode is active. Read the ndiv from the PLLARM OFFSET
>> + * register
>> + */
>> + ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
>> + IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
>> + if (ndiv_int == 0)
>> + ndiv_int = 256;
>> +
>> + ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
>> + } else {
>> + /* offset mode not active */
>> + val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
>> + ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
>> + IPROC_CLK_PLLARMA_NDIV_INT_MASK;
>> + if (ndiv_int == 0)
>> + ndiv_int = 1024;
>> +
>> + val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
>> + ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
>> + }
>> +
>> + ndiv = (ndiv_int << 20) | ndiv_frac;
>> +
>> + return ndiv;
>> +}
>> +
>> +/*
>> + * The output frequency of the ARM PLL is calculated based on the ARM PLL
>> + * divider values:
>> + * pdiv = ARM PLL pre-divider
>> + * ndiv = ARM PLL multiplier
>> + * mdiv = ARM PLL post divider
>> + *
>> + * The frequency is calculated by:
>> + * ((ndiv * parent clock rate) / pdiv) / mdiv
>> + */
>> +static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
>> + u32 val;
>> + int mdiv;
>> + u64 ndiv;
>> + unsigned int pdiv;
>> +
>> + /* in bypass mode, use parent rate */
>> + val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
>> + if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
>> + pll->rate = parent_rate;
>> + return pll->rate;
>> + }
>> +
>> + /* PLL needs to be locked */
>> + val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
>> + if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
>> + pll->rate = 0;
>> + return 0;
>> + }
>> +
>> + pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
>> + IPROC_CLK_PLLARMA_PDIV_MASK;
>> + if (pdiv == 0)
>> + pdiv = 16;
>> +
>> + ndiv = __get_ndiv(pll);
>> + mdiv = __get_mdiv(pll);
>> + if (mdiv <= 0) {
>> + pll->rate = 0;
>> + return 0;
>> + }
>> + pll->rate = (ndiv * parent_rate) >> 20;
>> + pll->rate = (pll->rate / pdiv) / mdiv;
>> +
>> + pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
>> + pll->rate, parent_rate);
>> + pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
>> + (unsigned int)(ndiv >> 20), pdiv, mdiv);
>> +
>> + return pll->rate;
>> +}
>> +
>> +static const struct clk_ops iproc_arm_pll_ops = {
>> + .recalc_rate = iproc_arm_pll_recalc_rate,
>> +};
>> +
>> +void __init iproc_armpll_setup(struct device_node *node)
>> +{
>> + int ret;
>> + struct clk *clk;
>> + struct iproc_arm_pll *pll;
>> + struct clk_init_data init;
>> + const char *parent_name;
>> +
>> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
>> + if (WARN_ON(!pll))
>> + return;
>> +
>> + pll->base = of_iomap(node, 0);
>> + if (WARN_ON(!pll->base))
>> + goto err_free_pll;
>> +
>> + init.name = node->name;
>> + init.ops = &iproc_arm_pll_ops;
>> + init.flags = 0;
>> + parent_name = of_clk_get_parent_name(node, 0);
>> + init.parent_names = (parent_name ? &parent_name : NULL);
>> + init.num_parents = (parent_name ? 1 : 0);
>> + pll->hw.init = &init;
>> +
>> + clk = clk_register(NULL, &pll->hw);
>> + if (WARN_ON(IS_ERR(clk)))
>> + goto err_iounmap;
>> +
>> + pll->clk_data.clk_num = 1;
>> + pll->clk_data.clks = &clk;
>> +
>> + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data);
>> + if (WARN_ON(ret))
>> + goto err_clk_unregister;
>> +
>> + return;
>> +
>> +err_clk_unregister:
>> + clk_unregister(clk);
>> +err_iounmap:
>> + iounmap(pll->base);
>> +err_free_pll:
>> + kfree(pll);
>> +}
>> diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
>> new file mode 100644
>> index 0000000..ab86b8c
>> --- /dev/null
>> +++ b/drivers/clk/bcm/clk-iproc-asiu.c
>> @@ -0,0 +1,275 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/of_address.h>
>> +#include <linux/delay.h>
>> +
>> +#include "clk-iproc.h"
>> +
>> +struct iproc_asiu;
>> +
>> +struct iproc_asiu_clk {
>> + struct clk_hw hw;
>> + const char *name;
>> + struct iproc_asiu *asiu;
>> + unsigned long rate;
>> + struct iproc_asiu_div div;
>> + struct iproc_asiu_gate gate;
>> +};
>> +
>> +struct iproc_asiu {
>> + void __iomem *div_base;
>> + void __iomem *gate_base;
>> +
>> + struct clk_onecell_data clk_data;
>> + struct iproc_asiu_clk *clks;
>> +};
>> +
>> +#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
>> +
>> +static int iproc_asiu_clk_enable(struct clk_hw *hw)
>> +{
>> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
>> + struct iproc_asiu *asiu = clk->asiu;
>> + u32 val;
>> +
>> + /* some clocks at the ASIU level are always enabled */
>> + if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
>> + return 0;
>> +
>> + val = readl(asiu->gate_base + clk->gate.offset);
>> + val |= (1 << clk->gate.en_shift);
>> + writel(val, asiu->gate_base + clk->gate.offset);
>> +
>> + return 0;
>> +}
>> +
>> +static void iproc_asiu_clk_disable(struct clk_hw *hw)
>> +{
>> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
>> + struct iproc_asiu *asiu = clk->asiu;
>> + u32 val;
>> +
>> + /* some clocks at the ASIU level are always enabled */
>> + if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
>> + return;
>> +
>> + val = readl(asiu->gate_base + clk->gate.offset);
>> + val &= ~(1 << clk->gate.en_shift);
>> + writel(val, asiu->gate_base + clk->gate.offset);
>> +}
>> +
>> +static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
>> + struct iproc_asiu *asiu = clk->asiu;
>> + u32 val;
>> + unsigned int div_h, div_l;
>> +
>> + if (parent_rate == 0) {
>> + clk->rate = 0;
>> + return 0;
>> + }
>> +
>> + /* if clock divisor is not enabled, simply return parent rate */
>> + val = readl(asiu->div_base + clk->div.offset);
>> + if ((val & (1 << clk->div.en_shift)) == 0) {
>> + clk->rate = parent_rate;
>> + return parent_rate;
>> + }
>> +
>> + /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
>> + div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
>> + div_h++;
>> + div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
>> + div_l++;
>> +
>> + clk->rate = parent_rate / (div_h + div_l);
>> + pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
>> + __func__, clk->rate, parent_rate, div_h, div_l);
>> +
>> + return clk->rate;
>> +}
>> +
>> +static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *parent_rate)
>> +{
>> + unsigned int div;
>> +
>> + if (rate == 0 || *parent_rate == 0)
>> + return -EINVAL;
>> +
>> + if (rate == *parent_rate)
>> + return *parent_rate;
>> +
>> + div = DIV_ROUND_UP(*parent_rate, rate);
>> + if (div < 2)
>> + return *parent_rate;
>> +
>> + return *parent_rate / div;
>> +}
>> +
>> +static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct iproc_asiu_clk *clk = to_asiu_clk(hw);
>> + struct iproc_asiu *asiu = clk->asiu;
>> + unsigned int div, div_h, div_l;
>> + u32 val;
>> +
>> + if (rate == 0 || parent_rate == 0)
>> + return -EINVAL;
>> +
>> + /* simply disable the divisor if one wants the same rate as parent */
>> + if (rate == parent_rate) {
>> + val = readl(asiu->div_base + clk->div.offset);
>> + val &= ~(1 << clk->div.en_shift);
>> + writel(val, asiu->div_base + clk->div.offset);
>> + return 0;
>> + }
>> +
>> + div = DIV_ROUND_UP(parent_rate, rate);
>> + if (div < 2)
>> + return -EINVAL;
>> +
>> + div_h = div_l = div >> 1;
>> + div_h--;
>> + div_l--;
>> +
>> + val = readl(asiu->div_base + clk->div.offset);
>> + val |= 1 << clk->div.en_shift;
>> + if (div_h) {
>> + val &= ~(bit_mask(clk->div.high_width)
>> + << clk->div.high_shift);
>> + val |= div_h << clk->div.high_shift;
>> + } else {
>> + val &= ~(bit_mask(clk->div.high_width)
>> + << clk->div.high_shift);
>> + }
>> + if (div_l) {
>> + val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
>> + val |= div_l << clk->div.low_shift;
>> + } else {
>> + val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
>> + }
>> + writel(val, asiu->div_base + clk->div.offset);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct clk_ops iproc_asiu_ops = {
>> + .enable = iproc_asiu_clk_enable,
>> + .disable = iproc_asiu_clk_disable,
>> + .recalc_rate = iproc_asiu_clk_recalc_rate,
>> + .round_rate = iproc_asiu_clk_round_rate,
>> + .set_rate = iproc_asiu_clk_set_rate,
>> +};
>> +
>> +void __init iproc_asiu_setup(struct device_node *node,
>> + const struct iproc_asiu_div *div,
>> + const struct iproc_asiu_gate *gate, unsigned int num_clks)
>> +{
>> + int i, ret;
>> + struct iproc_asiu *asiu;
>> +
>> + if (WARN_ON(!gate || !div))
>> + return;
>> +
>> + asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
>> + if (WARN_ON(!asiu))
>> + return;
>> +
>> + asiu->clk_data.clk_num = num_clks;
>> + asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks),
>> + GFP_KERNEL);
>> + if (WARN_ON(!asiu->clk_data.clks))
>> + goto err_clks;
>> +
>> + asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
>> + if (WARN_ON(!asiu->clks))
>> + goto err_asiu_clks;
>> +
>> + asiu->div_base = of_iomap(node, 0);
>> + if (WARN_ON(!asiu->div_base))
>> + goto err_iomap_div;
>> +
>> + asiu->gate_base = of_iomap(node, 1);
>> + if (WARN_ON(!asiu->gate_base))
>> + goto err_iomap_gate;
>> +
>> + for (i = 0; i < num_clks; i++) {
>> + struct clk_init_data init;
>> + struct clk *clk;
>> + const char *parent_name;
>> + struct iproc_asiu_clk *asiu_clk;
>> + const char *clk_name;
>> +
>> + clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
>> + if (WARN_ON(!clk_name))
>> + goto err_clk_register;
>> +
>> + ret = of_property_read_string_index(node, "clock-output-names",
>> + i, &clk_name);
>> + if (WARN_ON(ret))
>> + goto err_clk_register;
>> +
>> + asiu_clk = &asiu->clks[i];
>> + asiu_clk->name = clk_name;
>> + asiu_clk->asiu = asiu;
>> + asiu_clk->div = div[i];
>> + asiu_clk->gate = gate[i];
>> + init.name = clk_name;
>> + init.ops = &iproc_asiu_ops;
>> + init.flags = 0;
>> + parent_name = of_clk_get_parent_name(node, 0);
>> + init.parent_names = (parent_name ? &parent_name : NULL);
>> + init.num_parents = (parent_name ? 1 : 0);
>> + asiu_clk->hw.init = &init;
>> +
>> + clk = clk_register(NULL, &asiu_clk->hw);
>> + if (WARN_ON(IS_ERR(clk)))
>> + goto err_clk_register;
>> + asiu->clk_data.clks[i] = clk;
>> + }
>> +
>> + ret = of_clk_add_provider(node, of_clk_src_onecell_get,
>> + &asiu->clk_data);
>> + if (WARN_ON(ret))
>> + goto err_clk_register;
>> +
>> + return;
>> +
>> +err_clk_register:
>> + for (i = 0; i < num_clks; i++)
>> + kfree(asiu->clks[i].name);
>> + iounmap(asiu->gate_base);
>> +
>> +err_iomap_gate:
>> + iounmap(asiu->div_base);
>> +
>> +err_iomap_div:
>> + kfree(asiu->clks);
>> +
>> +err_asiu_clks:
>> + kfree(asiu->clk_data.clks);
>> +
>> +err_clks:
>> + kfree(asiu);
>> +}
>> diff --git a/drivers/clk/bcm/clk-iproc-clk.c b/drivers/clk/bcm/clk-iproc-clk.c
>> new file mode 100644
>> index 0000000..be3c42c
>> --- /dev/null
>> +++ b/drivers/clk/bcm/clk-iproc-clk.c
>> @@ -0,0 +1,238 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/of_address.h>
>> +#include <linux/delay.h>
>> +
>> +#include "clk-iproc.h"
>> +
>> +struct iproc_pll;
>> +
>> +struct iproc_clk {
>> + struct clk_hw hw;
>> + const char *name;
>> + struct iproc_pll *pll;
>> + unsigned long rate;
>> + const struct iproc_clk_ctrl *ctrl;
>> +};
>> +
>> +struct iproc_pll {
>> + void __iomem *base;
>> + struct clk_onecell_data clk_data;
>> + struct iproc_clk *clks;
>> +};
>> +
>> +#define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw)
>> +
>> +static int iproc_clk_enable(struct clk_hw *hw)
>> +{
>> + struct iproc_clk *clk = to_iproc_clk(hw);
>> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
>> + struct iproc_pll *pll = clk->pll;
>> + u32 val;
>> +
>> + /* channel enable is active low */
>> + val = readl(pll->base + ctrl->enable.offset);
>> + val &= ~(1 << ctrl->enable.enable_shift);
>> + writel(val, pll->base + ctrl->enable.offset);
>> +
>> + /* also make sure channel is not held */
>> + val = readl(pll->base + ctrl->enable.offset);
>> + val &= ~(1 << ctrl->enable.hold_shift);
>> + writel(val, pll->base + ctrl->enable.offset);
>> +
>> + return 0;
>> +}
>> +
>> +static void iproc_clk_disable(struct clk_hw *hw)
>> +{
>> + struct iproc_clk *clk = to_iproc_clk(hw);
>> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
>> + struct iproc_pll *pll = clk->pll;
>> + u32 val;
>> +
>> + if (ctrl->flags & IPROC_CLK_AON)
>> + return;
>> +
>> + val = readl(pll->base + ctrl->enable.offset);
>> + val |= 1 << ctrl->enable.enable_shift;
>> + writel(val, pll->base + ctrl->enable.offset);
>> +}
>> +
>> +static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct iproc_clk *clk = to_iproc_clk(hw);
>> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
>> + struct iproc_pll *pll = clk->pll;
>> + u32 val;
>> + unsigned int mdiv;
>> +
>> + if (parent_rate == 0)
>> + return 0;
>> +
>> + val = readl(pll->base + ctrl->mdiv.offset);
>> + mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width);
>> + if (mdiv == 0)
>> + mdiv = 256;
>> +
>> + clk->rate = parent_rate / mdiv;
>> +
>> + return clk->rate;
>> +}
>> +
>> +static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *parent_rate)
>> +{
>> + unsigned int div;
>> +
>> + if (rate == 0 || *parent_rate == 0)
>> + return -EINVAL;
>> +
>> + if (rate == *parent_rate)
>> + return *parent_rate;
>> +
>> + div = DIV_ROUND_UP(*parent_rate, rate);
>> + if (div < 2)
>> + return *parent_rate;
>> +
>> + if (div > 256)
>> + div = 256;
>> +
>> + return *parent_rate / div;
>> +}
>> +
>> +static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct iproc_clk *clk = to_iproc_clk(hw);
>> + const struct iproc_clk_ctrl *ctrl = clk->ctrl;
>> + struct iproc_pll *pll = clk->pll;
>> + u32 val;
>> + unsigned int div;
>> +
>> + if (rate == 0 || parent_rate == 0)
>> + return -EINVAL;
>> +
>> + div = DIV_ROUND_UP(parent_rate, rate);
>> + if (div > 256)
>> + return -EINVAL;
>> +
>> + val = readl(pll->base + ctrl->mdiv.offset);
>> + if (div == 256) {
>> + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
>> + } else {
>> + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
>> + val |= div << ctrl->mdiv.shift;
>> + }
>> + writel(val, pll->base + ctrl->mdiv.offset);
>> + clk->rate = parent_rate / div;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct clk_ops iproc_clk_ops = {
>> + .enable = iproc_clk_enable,
>> + .disable = iproc_clk_disable,
>> + .recalc_rate = iproc_clk_recalc_rate,
>> + .round_rate = iproc_clk_round_rate,
>> + .set_rate = iproc_clk_set_rate,
>> +};
>> +
>> +void __init iproc_clk_setup(struct device_node *node,
>> + const struct iproc_clk_ctrl *ctrl, unsigned int num_clks)
>> +{
>> + int i, ret;
>> + struct iproc_pll *pll;
>> +
>> + if (WARN_ON(!ctrl))
>> + return;
>> +
>> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
>> + if (WARN_ON(!pll))
>> + return;
>> +
>> + pll->clk_data.clk_num = num_clks;
>> + pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks),
>> + GFP_KERNEL);
>> + if (WARN_ON(!pll->clk_data.clks))
>> + goto err_clks;
>> +
>> + pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL);
>> + if (WARN_ON(!pll->clks))
>> + goto err_pll_clks;
>> +
>> + pll->base = of_iomap(node, 0);
>> + if (WARN_ON(!pll->base))
>> + goto err_iomap;
>> +
>> + for (i = 0; i < num_clks; i++) {
>> + struct clk_init_data init;
>> + struct clk *clk;
>> + const char *parent_name;
>> + struct iproc_clk *iclk;
>> + const char *clk_name;
>> +
>> + clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
>> + if (WARN_ON(!clk_name))
>> + goto err_clk_register;
>> +
>> + ret = of_property_read_string_index(node, "clock-output-names",
>> + i, &clk_name);
>> + if (WARN_ON(ret))
>> + goto err_clk_register;
>> +
>> + iclk = &pll->clks[i];
>> + iclk->name = clk_name;
>> + iclk->pll = pll;
>> + iclk->ctrl = &ctrl[i];
>> + init.name = clk_name;
>> + init.ops = &iproc_clk_ops;
>> + init.flags = 0;
>> + parent_name = of_clk_get_parent_name(node, 0);
>> + init.parent_names = (parent_name ? &parent_name : NULL);
>> + init.num_parents = (parent_name ? 1 : 0);
>> + iclk->hw.init = &init;
>> +
>> + clk = clk_register(NULL, &iclk->hw);
>> + if (WARN_ON(IS_ERR(clk)))
>> + goto err_clk_register;
>> + pll->clk_data.clks[i] = clk;
>> + }
>> +
>> + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data);
>> + if (WARN_ON(ret))
>> + goto err_clk_register;
>> +
>> + return;
>> +
>> +err_clk_register:
>> + for (i = 0; i < num_clks; i++)
>> + kfree(pll->clks[i].name);
>> + iounmap(pll->base);
>> +
>> +err_iomap:
>> + kfree(pll->clks);
>> +
>> +err_pll_clks:
>> + kfree(pll->clk_data.clks);
>> +
>> +err_clks:
>> + kfree(pll);
>> +}
>> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
>> new file mode 100644
>> index 0000000..cd3bd38
>> --- /dev/null
>> +++ b/drivers/clk/bcm/clk-iproc-pll.c
>> @@ -0,0 +1,483 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/of_address.h>
>> +#include <linux/delay.h>
>> +
>> +#include "clk-iproc.h"
>> +
>> +#define PLL_VCO_HIGH_SHIFT 19
>> +#define PLL_VCO_LOW_SHIFT 30
>> +
>> +/* number of delay loops waiting for PLL to lock */
>> +#define LOCK_DELAY 100
>> +
>> +/* number of VCO frequency bands */
>> +#define NUM_FREQ_BANDS 8
>> +
>> +#define NUM_KP_BANDS 3
>> +enum kp_band {
>> + KP_BAND_MID = 0,
>> + KP_BAND_HIGH,
>> + KP_BAND_HIGH_HIGH
>> +};
>> +
>> +static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = {
>> + { 5, 6, 6, 7, 7, 8, 9, 10 },
>> + { 4, 4, 5, 5, 6, 7, 8, 9 },
>> + { 4, 5, 5, 6, 7, 8, 9, 10 },
>> +};
>> +
>> +static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = {
>> + { 10000000, 12500000 },
>> + { 12500000, 15000000 },
>> + { 15000000, 20000000 },
>> + { 20000000, 25000000 },
>> + { 25000000, 50000000 },
>> + { 50000000, 75000000 },
>> + { 75000000, 100000000 },
>> + { 100000000, 125000000 },
>> +};
>> +
>> +enum vco_freq_range {
>> + VCO_LOW = 700000000U,
>> + VCO_MID = 1200000000U,
>> + VCO_HIGH = 2200000000U,
>> + VCO_HIGH_HIGH = 3100000000U,
>> + VCO_MAX = 4000000000U,
>> +};
>> +
>> +struct iproc_pll {
>> + struct clk_hw hw;
>> + void __iomem *pll_base;
>> + void __iomem *pwr_base;
>> + void __iomem *asiu_base;
>> + struct clk_onecell_data clk_data;
>> + const char *name;
>> + const struct iproc_pll_ctrl *ctrl;
>> + const struct iproc_pll_vco_freq_param *vco_param;
>> + unsigned int num_vco_entries;
>> + unsigned long rate;
>> +};
>> +
>> +#define to_iproc_pll(hw) container_of(hw, struct iproc_pll, hw)
>> +
>> +/*
>> + * Get the clock rate based on name
>> + */
>> +static unsigned long __get_rate(const char *clk_name)
>> +{
>> + struct clk *clk;
>> +
>> + clk = __clk_lookup(clk_name);
>> + if (!clk) {
>> + pr_err("%s: unable to find clock by name: %s\n", __func__,
>> + clk_name);
>> + return 0;
>> + }
>> +
>> + return clk_get_rate(clk);
>> +}
>> +
>> +/*
>> + * Based on the target frequency, find a match from the VCO frequency parameter
>> + * table and return its index
>> + */
>> +static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < pll->num_vco_entries; i++)
>> + if (target_rate == pll->vco_param[i].rate)
>> + break;
>> +
>> + if (i >= pll->num_vco_entries)
>> + return -EINVAL;
>> +
>> + return i;
>> +}
>> +
>> +static int get_kp(unsigned long ref_freq, enum kp_band kp_index)
>> +{
>> + int i;
>> +
>> + if (ref_freq < ref_freq_table[0][0])
>> + return -EINVAL;
>> +
>> + for (i = 0; i < NUM_FREQ_BANDS; i++) {
>> + if (ref_freq >= ref_freq_table[i][0] &&
>> + ref_freq < ref_freq_table[i][1])
>> + return kp_table[kp_index][i];
>> + }
>> + return -EINVAL;
>> +}
>> +
>> +static int pll_wait_for_lock(struct iproc_pll *pll)
>> +{
>> + int i;
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> +
>> + for (i = 0; i < LOCK_DELAY; i++) {
>> + u32 val = readl(pll->pll_base + ctrl->status.offset);
>> +
>> + if (val & (1 << ctrl->status.shift))
>> + return 0;
>> + udelay(10);
>> + }
>> +
>> + return -EIO;
>> +}
>> +
>> +static void __pll_disable(struct iproc_pll *pll)
>> +{
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> + u32 val;
>> +
>> + if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
>> + val = readl(pll->asiu_base + ctrl->asiu.offset);
>> + val &= ~(1 << ctrl->asiu.en_shift);
>> + writel(val, pll->asiu_base + ctrl->asiu.offset);
>> + }
>> +
>> + /* latch input value so core power can be shut down */
>> + val = readl(pll->pwr_base + ctrl->aon.offset);
>> + val |= (1 << ctrl->aon.iso_shift);
>> + writel(val, pll->pwr_base + ctrl->aon.offset);
>> +
>> + /* power down the core */
>> + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
>> + writel(val, pll->pwr_base + ctrl->aon.offset);
>> +}
>> +
>> +static int __pll_enable(struct iproc_pll *pll)
>> +{
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> + u32 val;
>> +
>> + /* power up the PLL and make sure it's not latched */
>> + val = readl(pll->pwr_base + ctrl->aon.offset);
>> + val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
>> + val &= ~(1 << ctrl->aon.iso_shift);
>> + writel(val, pll->pwr_base + ctrl->aon.offset);
>> +
>> + /* certain PLLs also need to be ungated from the ASIU top level */
>> + if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
>> + val = readl(pll->asiu_base + ctrl->asiu.offset);
>> + val |= (1 << ctrl->asiu.en_shift);
>> + writel(val, pll->asiu_base + ctrl->asiu.offset);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void __pll_put_in_reset(struct iproc_pll *pll)
>> +{
>> + u32 val;
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
>> +
>> + val = readl(pll->pll_base + reset->offset);
>> + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
>> + writel(val, pll->pll_base + reset->offset);
>> +}
>> +
>> +static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
>> + unsigned int ka, unsigned int ki)
>> +{
>> + u32 val;
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
>> +
>> + val = readl(pll->pll_base + reset->offset);
>> + val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
>> + bit_mask(reset->kp_width) << reset->kp_shift |
>> + bit_mask(reset->ka_width) << reset->ka_shift);
>> + val |= ki << reset->ki_shift | kp << reset->kp_shift |
>> + ka << reset->ka_shift;
>> + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
>> + writel(val, pll->pll_base + reset->offset);
>> +}
>> +
>> +static int pll_set_rate(struct iproc_pll *pll, unsigned int rate_index,
>> + unsigned long parent_rate)
>> +{
>> + const struct iproc_pll_vco_freq_param *vco =
>> + &pll->vco_param[rate_index];
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> + int ka = 0, ki, kp, ret;
>> + unsigned long rate = vco->rate;
>> + u32 val;
>> + enum kp_band kp_index;
>> + unsigned long ref_freq;
>> +
>> + /*
>> + * reference frequency = parent frequency / PDIV
>> + * If PDIV = 0, then it becomes a multiplier (x2)
>> + */
>> + if (vco->pdiv == 0)
>> + ref_freq = parent_rate * 2;
>> + else
>> + ref_freq = parent_rate / vco->pdiv;
>> +
>> + /* determine Ki and Kp index based on target VCO frequency */
>> + if (rate >= VCO_LOW && rate < VCO_HIGH) {
>> + ki = 4;
>> + kp_index = KP_BAND_MID;
>> + } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) {
>> + ki = 3;
>> + kp_index = KP_BAND_HIGH;
>> + } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) {
>> + ki = 3;
>> + kp_index = KP_BAND_HIGH_HIGH;
>> + } else {
>> + pr_err("%s: pll: %s has invalid rate: %lu\n", __func__,
>> + pll->name, rate);
>> + return -EINVAL;
>> + }
>> +
>> + kp = get_kp(ref_freq, kp_index);
>> + if (kp < 0) {
>> + pr_err("%s: pll: %s has invalid kp\n", __func__, pll->name);
>> + return kp;
>> + }
>> +
>> + ret = __pll_enable(pll);
>> + if (ret) {
>> + pr_err("%s: pll: %s fails to enable\n", __func__, pll->name);
>> + return ret;
>> + }
>> +
>> + /* put PLL in reset */
>> + __pll_put_in_reset(pll);
>> +
>> + writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset);
>> + val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset);
>> +
>> + if (rate >= VCO_LOW && rate < VCO_MID)
>> + val |= (1 << PLL_VCO_LOW_SHIFT);
>> +
>> + if (rate < VCO_HIGH)
>> + val &= ~(1 << PLL_VCO_HIGH_SHIFT);
>> + else
>> + val |= (1 << PLL_VCO_HIGH_SHIFT);
>> +
>> + writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset);
>> +
>> + /* program integer part of NDIV */
>> + val = readl(pll->pll_base + ctrl->ndiv_int.offset);
>> + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift);
>> + val |= vco->ndiv_int << ctrl->ndiv_int.shift;
>> + writel(val, pll->pll_base + ctrl->ndiv_int.offset);
>> +
>> + /* program fractional part of NDIV */
>> + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
>> + val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
>> + val &= ~(bit_mask(ctrl->ndiv_frac.width) <<
>> + ctrl->ndiv_frac.shift);
>> + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift;
>> + writel(val, pll->pll_base + ctrl->ndiv_frac.offset);
>> + }
>> +
>> + /* program PDIV */
>> + val = readl(pll->pll_base + ctrl->pdiv.offset);
>> + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift);
>> + val |= vco->pdiv << ctrl->pdiv.shift;
>> + writel(val, pll->pll_base + ctrl->pdiv.offset);
>> +
>> + __pll_bring_out_reset(pll, kp, ka, ki);
>> +
>> + ret = pll_wait_for_lock(pll);
>> + if (ret < 0) {
>> + pr_err("%s: pll: %s failed to lock\n", __func__, pll->name);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int iproc_pll_enable(struct clk_hw *hw)
>> +{
>> + struct iproc_pll *pll = to_iproc_pll(hw);
>> +
>> + return __pll_enable(pll);
>> +}
>> +
>> +static void iproc_pll_disable(struct clk_hw *hw)
>> +{
>> + struct iproc_pll *pll = to_iproc_pll(hw);
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> +
>> + if (ctrl->flags & IPROC_CLK_AON)
>> + return;
>> +
>> + __pll_disable(pll);
>> +}
>> +
>> +static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct iproc_pll *pll = to_iproc_pll(hw);
>> + const struct iproc_pll_ctrl *ctrl = pll->ctrl;
>> + u32 val;
>> + u64 ndiv;
>> + unsigned int ndiv_int, ndiv_frac, pdiv;
>> +
>> + if (parent_rate == 0)
>> + return 0;
>> +
>> + /* PLL needs to be locked */
>> + val = readl(pll->pll_base + ctrl->status.offset);
>> + if ((val & (1 << ctrl->status.shift)) == 0) {
>> + pll->rate = 0;
>> + return 0;
>> + }
>> +
>> + /*
>> + * PLL output frequency =
>> + *
>> + * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv)
>> + */
>> + val = readl(pll->pll_base + ctrl->ndiv_int.offset);
>> + ndiv_int = (val >> ctrl->ndiv_int.shift) &
>> + bit_mask(ctrl->ndiv_int.width);
>> + ndiv = ndiv_int << ctrl->ndiv_int.shift;
>> +
>> + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
>> + val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
>> + ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
>> + bit_mask(ctrl->ndiv_frac.width);
>> +
>> + if (ndiv_frac != 0)
>> + ndiv = (ndiv_int << ctrl->ndiv_int.shift) | ndiv_frac;
>> + }
>> +
>> + val = readl(pll->pll_base + ctrl->pdiv.offset);
>> + pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
>> +
>> + pll->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
>> +
>> + if (pdiv == 0)
>> + pll->rate *= 2;
>> + else
>> + pll->rate /= pdiv;
>> +
>> + return pll->rate;
>> +}
>> +
>> +static const struct clk_ops iproc_pll_ops = {
>> + .enable = iproc_pll_enable,
>> + .disable = iproc_pll_disable,
>> + .recalc_rate = iproc_pll_recalc_rate,
>> +};
>> +
>> +void __init iproc_pll_setup(struct device_node *node,
>> + const struct iproc_pll_ctrl *ctrl,
>> + const struct iproc_pll_vco_freq_param *vco_param,
>> + unsigned int num_vco_entries)
>> +{
>> + int ret;
>> + struct clk *clk;
>> + struct iproc_pll *pll;
>> + struct clk_init_data init;
>> + const char *parent_name;
>> + unsigned int rate;
>> +
>> + if (WARN_ON(!ctrl))
>> + return;
>> +
>> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
>> + if (WARN_ON(!pll))
>> + return;
>> +
>> + pll->pll_base = of_iomap(node, 0);
>> + if (WARN_ON(!pll->pll_base))
>> + goto err_pll_iomap;
>> +
>> + pll->pwr_base = of_iomap(node, 1);
>> + if (WARN_ON(!pll->pwr_base))
>> + goto err_pwr_iomap;
>> +
>> + /* some PLLs require gating control at the top ASIU level */
>> + if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
>> + pll->asiu_base = of_iomap(node, 2);
>> + if (WARN_ON(!pll->asiu_base))
>> + goto err_asiu_iomap;
>> + }
>> +
>> + pll->ctrl = ctrl;
>> + pll->name = node->name;
>> + init.name = node->name;
>> + init.ops = &iproc_pll_ops;
>> + init.flags = 0;
>> + parent_name = of_clk_get_parent_name(node, 0);
>> + init.parent_names = (parent_name ? &parent_name : NULL);
>> + init.num_parents = (parent_name ? 1 : 0);
>> + pll->hw.init = &init;
>> +
>> + /* configure the PLL to the desired VCO frequency if specified */
>> + ret = of_property_read_u32(node, "clock-frequency", &rate);
>> + if (!ret) {
>> + unsigned long parent_rate;
>> + int rate_index;
>> +
>> + if (WARN_ON(!vco_param))
>> + goto err_clk_register;
>> +
>> + pll->num_vco_entries = num_vco_entries;
>> + pll->vco_param = vco_param;
>> +
>> + parent_rate = __get_rate(parent_name);
>> + if (WARN_ON(!parent_rate))
>> + goto err_clk_register;
>> +
>> + rate_index = pll_get_rate_index(pll, rate);
>> + if (WARN_ON(rate_index < 0))
>> + goto err_clk_register;
>> +
>> + ret = pll_set_rate(pll, rate_index, parent_rate);
>> + if (WARN_ON(ret))
>> + goto err_clk_register;
>> + }
>> +
>> + clk = clk_register(NULL, &pll->hw);
>> + if (WARN_ON(IS_ERR(clk)))
>> + goto err_clk_register;
>> +
>> + pll->clk_data.clk_num = 1;
>> + pll->clk_data.clks = &clk;
>> +
>> + ret = of_clk_add_provider(node, of_clk_src_onecell_get,
>> + &pll->clk_data);
>> + if (WARN_ON(ret))
>> + goto err_clk_add;
>> +
>> + return;
>> +
>> +err_clk_add:
>> + clk_unregister(clk);
>> +err_clk_register:
>> + if (pll->asiu_base)
>> + iounmap(pll->asiu_base);
>> +err_asiu_iomap:
>> + iounmap(pll->pwr_base);
>> +err_pwr_iomap:
>> + iounmap(pll->pll_base);
>> +err_pll_iomap:
>> + kfree(pll);
>> +}
>> diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
>> new file mode 100644
>> index 0000000..4aa0479
>> --- /dev/null
>> +++ b/drivers/clk/bcm/clk-iproc.h
>> @@ -0,0 +1,155 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#ifndef _CLK_IPROC_H
>> +#define _CLK_IPROC_H
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/slab.h>
>> +#include <linux/device.h>
>> +#include <linux/of.h>
>> +#include <linux/clk-provider.h>
>> +
>> +#define IPROC_CLK_NAME_LEN 25
>> +#define IPROC_CLK_INVALID_OFFSET 0xffffffff
>> +#define bit_mask(width) ((1 << (width)) - 1)
>> +
>> +/* clock should not be disabled at runtime */
>> +#define IPROC_CLK_AON BIT(0)
>> +
>> +/* PLL requires gating through ASIU */
>> +#define IPROC_CLK_PLL_ASIU BIT(1)
>> +
>> +/* PLL has fractional part of the NDIV */
>> +#define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
>> +
>> +/*
>> + * Parameters for VCO frequency configuration
>> + *
>> + * VCO frequency =
>> + * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
>> + */
>> +struct iproc_pll_vco_freq_param {
>> + unsigned long rate;
>> + unsigned int ndiv_int;
>> + unsigned int ndiv_frac;
>> + unsigned int pdiv;
>> +};
>> +
>> +struct iproc_clk_reg_op {
>> + unsigned int offset;
>> + unsigned int shift;
>> + unsigned int width;
>> +};
>> +
>> +/*
>> + * Clock gating control at the top ASIU level
>> + */
>> +struct iproc_asiu_gate {
>> + unsigned int offset;
>> + unsigned int en_shift;
>> +};
>> +
>> +/*
>> + * Control of powering on/off of a PLL
>> + *
>> + * Before powering off a PLL, input isolation (ISO) needs to be enabled
>> + */
>> +struct iproc_pll_aon_pwr_ctrl {
>> + unsigned int offset;
>> + unsigned int pwr_width;
>> + unsigned int pwr_shift;
>> + unsigned int iso_shift;
>> +};
>> +
>> +/*
>> + * Control of the PLL reset, with Ki, Kp, and Ka parameters
>> + */
>> +struct iproc_pll_reset_ctrl {
>> + unsigned int offset;
>> + unsigned int reset_shift;
>> + unsigned int p_reset_shift;
>> + unsigned int ki_shift;
>> + unsigned int ki_width;
>> + unsigned int kp_shift;
>> + unsigned int kp_width;
>> + unsigned int ka_shift;
>> + unsigned int ka_width;
>> +};
>> +
>> +struct iproc_pll_vco_ctrl {
>> + unsigned int u_offset;
>> + unsigned int l_offset;
>> +};
>> +
>> +/*
>> + * Main PLL control parameters
>> + */
>> +struct iproc_pll_ctrl {
>> + unsigned long flags;
>> + struct iproc_pll_aon_pwr_ctrl aon;
>> + struct iproc_asiu_gate asiu;
>> + struct iproc_pll_reset_ctrl reset;
>> + struct iproc_clk_reg_op ndiv_int;
>> + struct iproc_clk_reg_op ndiv_frac;
>> + struct iproc_clk_reg_op pdiv;
>> + struct iproc_pll_vco_ctrl vco_ctrl;
>> + struct iproc_clk_reg_op status;
>> +};
>> +
>> +/*
>> + * Controls enabling/disabling a PLL derived clock
>> + */
>> +struct iproc_clk_enable_ctrl {
>> + unsigned int offset;
>> + unsigned int enable_shift;
>> + unsigned int hold_shift;
>> + unsigned int bypass_shift;
>> +};
>> +
>> +/*
>> + * Main clock control parameters for clocks derived from the PLLs
>> + */
>> +struct iproc_clk_ctrl {
>> + unsigned int channel;
>> + unsigned long flags;
>> + struct iproc_clk_enable_ctrl enable;
>> + struct iproc_clk_reg_op mdiv;
>> +};
>> +
>> +/*
>> + * Divisor of the ASIU clocks
>> + */
>> +struct iproc_asiu_div {
>> + unsigned int offset;
>> + unsigned int en_shift;
>> + unsigned int high_shift;
>> + unsigned int high_width;
>> + unsigned int low_shift;
>> + unsigned int low_width;
>> +};
>> +
>> +extern void __init iproc_armpll_setup(struct device_node *node);
>> +extern void __init iproc_pll_setup(struct device_node *node,
>> + const struct iproc_pll_ctrl *ctrl,
>> + const struct iproc_pll_vco_freq_param *vco_param,
>> + unsigned int num_freqs);
>> +extern void __init iproc_clk_setup(struct device_node *node,
>> + const struct iproc_clk_ctrl *ctrl, unsigned int num_clks);
>> +extern void __init iproc_asiu_setup(struct device_node *node,
>> + const struct iproc_asiu_div *div,
>> + const struct iproc_asiu_gate *gate, unsigned int num_clks);
>> +
>> +#endif /* _CLK_IPROC_H */
>> --
>> 1.7.9.5
>>
>>
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