2023-08-01 04:46:35

by Ran Sun

Subject: [PATCH] drm/amd/pm: Clean up errors in smu10_hwmgr.c

Fix the following errors reported by checkpatch:

ERROR: spaces required around that '=' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)

Signed-off-by: Ran Sun <[email protected]>
---
.../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 86d6e88c7386..02ba68d7c654 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -430,37 +430,37 @@ static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
}

/* temporary hardcoded clock voltage breakdown tables */
-static const DpmClock_t VddDcfClk[]= {
+static const DpmClock_t VddDcfClk[] = {
{ 300, 2600},
{ 600, 3200},
{ 600, 3600},
};

-static const DpmClock_t VddSocClk[]= {
+static const DpmClock_t VddSocClk[] = {
{ 478, 2600},
{ 722, 3200},
{ 722, 3600},
};

-static const DpmClock_t VddFClk[]= {
+static const DpmClock_t VddFClk[] = {
{ 400, 2600},
{1200, 3200},
{1200, 3600},
};

-static const DpmClock_t VddDispClk[]= {
+static const DpmClock_t VddDispClk[] = {
{ 435, 2600},
{ 661, 3200},
{1086, 3600},
};

-static const DpmClock_t VddDppClk[]= {
+static const DpmClock_t VddDppClk[] = {
{ 435, 2600},
{ 661, 3200},
{ 661, 3600},
};

-static const DpmClock_t VddPhyClk[]= {
+static const DpmClock_t VddPhyClk[] = {
{ 540, 2600},
{ 810, 3200},
{ 810, 3600},
@@ -1358,7 +1358,7 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct amdgpu_device *adev = hwmgr->adev;
int i;

- smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
+ smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);

if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
for (i = 0; i < NUM_WM_RANGES; i++)
@@ -1461,7 +1461,7 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)

phm_get_sysfs_buf(&buf, &size);

- size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
+ size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n", title[0],
title[1], title[2], title[3], title[4], title[5]);

for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
--
2.17.1

2023-08-07 18:23:55

by Alex Deucher

Subject: Re: [PATCH] drm/amd/pm: Clean up errors in smu10_hwmgr.c

Applied. Thanks!

On Mon, Jul 31, 2023 at 11:09 PM Ran Sun <[email protected]> wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: spaces required around that '=' (ctx:VxW)
> ERROR: space required after that ',' (ctx:VxV)
>
> Signed-off-by: Ran Sun <[email protected]>
> ---
> .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 86d6e88c7386..02ba68d7c654 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -430,37 +430,37 @@ static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
> }
>
> /* temporary hardcoded clock voltage breakdown tables */
> -static const DpmClock_t VddDcfClk[]= {
> +static const DpmClock_t VddDcfClk[] = {
> { 300, 2600},
> { 600, 3200},
> { 600, 3600},
> };
>
> -static const DpmClock_t VddSocClk[]= {
> +static const DpmClock_t VddSocClk[] = {
> { 478, 2600},
> { 722, 3200},
> { 722, 3600},
> };
>
> -static const DpmClock_t VddFClk[]= {
> +static const DpmClock_t VddFClk[] = {
> { 400, 2600},
> {1200, 3200},
> {1200, 3600},
> };
>
> -static const DpmClock_t VddDispClk[]= {
> +static const DpmClock_t VddDispClk[] = {
> { 435, 2600},
> { 661, 3200},
> {1086, 3600},
> };
>
> -static const DpmClock_t VddDppClk[]= {
> +static const DpmClock_t VddDppClk[] = {
> { 435, 2600},
> { 661, 3200},
> { 661, 3600},
> };
>
> -static const DpmClock_t VddPhyClk[]= {
> +static const DpmClock_t VddPhyClk[] = {
> { 540, 2600},
> { 810, 3200},
> { 810, 3600},
> @@ -1358,7 +1358,7 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> struct amdgpu_device *adev = hwmgr->adev;
> int i;
>
> - smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
> + smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
>
> if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> for (i = 0; i < NUM_WM_RANGES; i++)
> @@ -1461,7 +1461,7 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>
> phm_get_sysfs_buf(&buf, &size);
>
> - size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
> + size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n", title[0],
> title[1], title[2], title[3], title[4], title[5]);
>
> for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
> --
> 2.17.1
>