From: Randy Dunlap <[email protected]>
Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
Correct INVPID to INVVPID.
Add UD0, UD1, and UD2 instruction opcodes.
Signed-off-by: Randy Dunlap <[email protected]>
Cc: Masami Hiramatsu <[email protected]>
Cc: Josh Poimboeuf <[email protected]>
Cc: x86 maintainers <[email protected]>
---
arch/x86/lib/x86-opcode-map.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
Are these following file updated automatically or manually?
./tools/objtool/arch/x86/lib/x86-opcode-map.txt
./tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
--- lnx-415-rc2.orig/arch/x86/lib/x86-opcode-map.txt
+++ lnx-415-rc2/arch/x86/lib/x86-opcode-map.txt
@@ -533,7 +533,7 @@ b5: LGS Gv,Mp
b6: MOVZX Gv,Eb
b7: MOVZX Gv,Ew
b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
-b9: Grp10 (1A)
+b9: Grp10 (1A) [all UD1]
ba: Grp8 Ev,Ib (1A)
bb: BTC Ev,Gv
bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
@@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(
fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
-ff:
+ff: UD0
EndTable
Table: 3-byte opcode 1 (0x0f 0x38)
@@ -717,7 +717,7 @@ AVXcode: 2
7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
80: INVEPT Gy,Mdq (66)
-81: INVPID Gy,Mdq (66)
+81: INVVPID Gy,Mdq (66)
82: INVPCID Gy,Mdq (66)
83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
88: vexpandps/d Vpd,Wpd (66),(ev)
@@ -970,6 +970,7 @@ GrpTable: Grp9
EndTable
GrpTable: Grp10
+# all are UD1
EndTable
# Grp11A and Grp11B are expressed as Grp11 in Intel SDM
Hi Randy,
2017-12-11 9:33 GMT+09:00 Randy Dunlap <[email protected]>:
> From: Randy Dunlap <[email protected]>
>
> Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
> Correct INVPID to INVVPID.
> Add UD0, UD1, and UD2 instruction opcodes.
Thanks for update! I have some comments on it.
>
> Signed-off-by: Randy Dunlap <[email protected]>
> Cc: Masami Hiramatsu <[email protected]>
> Cc: Josh Poimboeuf <[email protected]>
> Cc: x86 maintainers <[email protected]>
> ---
>
> arch/x86/lib/x86-opcode-map.txt | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> Are these following file updated automatically or manually?
> ./tools/objtool/arch/x86/lib/x86-opcode-map.txt
> ./tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
>
> --- lnx-415-rc2.orig/arch/x86/lib/x86-opcode-map.txt
> +++ lnx-415-rc2/arch/x86/lib/x86-opcode-map.txt
> @@ -533,7 +533,7 @@ b5: LGS Gv,Mp
> b6: MOVZX Gv,Eb
> b7: MOVZX Gv,Ew
> b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
> -b9: Grp10 (1A)
> +b9: Grp10 (1A) [all UD1]
Could you make this [all UD1] to just a comment? like "# all UD1".
I would like to keep "[]" for other usecase.
> ba: Grp8 Ev,Ib (1A)
> bb: BTC Ev,Gv
> bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
> @@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(
> fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
> fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
> fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
> -ff:
> +ff: UD0
> EndTable
>
> Table: 3-byte opcode 1 (0x0f 0x38)
> @@ -717,7 +717,7 @@ AVXcode: 2
> 7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
> 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
> 80: INVEPT Gy,Mdq (66)
> -81: INVPID Gy,Mdq (66)
> +81: INVVPID Gy,Mdq (66)
> 82: INVPCID Gy,Mdq (66)
> 83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
> 88: vexpandps/d Vpd,Wpd (66),(ev)
> @@ -970,6 +970,7 @@ GrpTable: Grp9
> EndTable
>
> GrpTable: Grp10
> +# all are UD1
And could you expand this UD1 to a table? like
0: UD1
1: UD1
...
Thank you,
> EndTable
>
> # Grp11A and Grp11B are expressed as Grp11 in Intel SDM
>
>
--
Masami Hiramatsu
mailto:[email protected]
* Randy Dunlap <[email protected]> wrote:
> From: Randy Dunlap <[email protected]>
>
> Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
> Correct INVPID to INVVPID.
> Add UD0, UD1, and UD2 instruction opcodes.
>
> Signed-off-by: Randy Dunlap <[email protected]>
> Cc: Masami Hiramatsu <[email protected]>
> Cc: Josh Poimboeuf <[email protected]>
> Cc: x86 maintainers <[email protected]>
> ---
>
> arch/x86/lib/x86-opcode-map.txt | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> Are these following file updated automatically or manually?
> ./tools/objtool/arch/x86/lib/x86-opcode-map.txt
> ./tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
Manually, but I'll do that when applying to patch, no need to complicate your
workflow.
Thanks,
Ingo
On 12/11/2017 05:49 AM, Ingo Molnar wrote:
>
> * Randy Dunlap <[email protected]> wrote:
>
>> From: Randy Dunlap <[email protected]>
>>
>> Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
>> Correct INVPID to INVVPID.
>> Add UD0, UD1, and UD2 instruction opcodes.
>>
>> Signed-off-by: Randy Dunlap <[email protected]>
>> Cc: Masami Hiramatsu <[email protected]>
>> Cc: Josh Poimboeuf <[email protected]>
>> Cc: x86 maintainers <[email protected]>
>> ---
>>
>> arch/x86/lib/x86-opcode-map.txt | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> Are these following file updated automatically or manually?
>> ./tools/objtool/arch/x86/lib/x86-opcode-map.txt
>> ./tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
>
> Manually, but I'll do that when applying to patch, no need to complicate your
> workflow.
Sounds good. I'll send a replacement patch as requested by Masami.
--
~Randy