Hi,
Let's add watchdog, arm-pmu, dma, usb, mmc..... support for allwinner
a100 soc.
Yangtao Li (19):
pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
pinctrl: sunxi: Mark the irq bank not found in
sunxi_pinctrl_irq_handler() with WARN_ON
pinctrl: sunxi: Always call chained_irq_{enter, exit} in
sunxi_pinctrl_irq_handler
dt-bindings: dma: allwinner,sun50i-a64-dma: Add A100 compatible
dmaengine: sun6i: Add support for A100 DMA
arm64: allwinner: a100: Add device node for DMA controller
arm64: dts: allwinner: A100: Add PMU mode
phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg
phy: allwinner: Convert to devm_platform_ioremap_* API
dt-bindings: watchdog: sun4i: Add A100 compatible
arm64: dts: allwinner: a100: add watchdog node
dt-bindings: Add bindings for USB phy on Allwinner A100
phy: sun4i-usb: add support for A100 USB PHY
arm64: dts: allwinner: a100: add usb related nodes
arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
dt-bindings: mmc: sunxi: Add A100 compatibles
mmc: sunxi: add support for A100 mmc controller
arm64: allwinner: a100: Add MMC related nodes
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
.../dma/allwinner,sun50i-a64-dma.yaml | 5 +-
.../bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 2 +
.../phy/allwinner,sun50i-a100-usb-phy.yaml | 105 ++++++++++
.../watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 54 +++++
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 197 +++++++++++++++++-
drivers/dma/sun6i-dma.c | 25 +++
drivers/mmc/host/sunxi-mmc.c | 28 ++-
drivers/phy/allwinner/phy-sun4i-usb.c | 29 ++-
drivers/phy/allwinner/phy-sun50i-usb3.c | 4 +-
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 +-
drivers/phy/allwinner/phy-sun9i-usb.c | 4 +-
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +-
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 +-
14 files changed, 443 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
--
2.28.0
From: Yangtao Li <[email protected]>
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Cc: [email protected]
Signed-off-by: Yangtao Li <[email protected]>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 9d8b59dafa4b..dc8d39ae045b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -1141,20 +1141,22 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
WARN_ON(bank == pctl->desc->irq_banks);
+ chained_irq_enter(chip, desc);
+
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
if (val) {
int irqoffset;
- chained_irq_enter(chip, desc);
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
int pin_irq = irq_find_mapping(pctl->domain,
bank * IRQ_PER_BANK + irqoffset);
generic_handle_irq(pin_irq);
}
- chained_irq_exit(chip, desc);
}
+
+ chained_irq_exit(chip, desc);
}
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
--
2.28.0
From: Yangtao Li <[email protected]>
Add a binding for A100's dma controller.
Signed-off-by: Yangtao Li <[email protected]>
---
.../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
index 372679dbd216..b6e1ebfaf366 100644
--- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
@@ -21,6 +21,7 @@ properties:
compatible:
oneOf:
- const: allwinner,sun50i-a64-dma
+ - const: allwinner,sun50i-a100-dma
- const: allwinner,sun50i-h6-dma
- items:
- const: allwinner,sun8i-r40-dma
@@ -56,7 +57,9 @@ required:
if:
properties:
compatible:
- const: allwinner,sun50i-h6-dma
+ enum:
+ - allwinner,sun50i-a100-dma
+ - allwinner,sun50i-h6-dma
then:
properties:
--
2.28.0
From: Yangtao Li <[email protected]>
Use the devm_platform_ioremap_resource_byname() and
devm_platform_ioremap_resource helper to simplify the code.
Signed-off-by: Yangtao Li <[email protected]>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 9 +++------
drivers/phy/allwinner/phy-sun50i-usb3.c | 4 +---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 +---
drivers/phy/allwinner/phy-sun9i-usb.c | 4 +---
4 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 0f1888b55dbd..a6900495baa5 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -686,7 +686,6 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- struct resource *res;
int i, ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -700,8 +699,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (!data->cfg)
return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
- data->base = devm_ioremap_resource(dev, res);
+ data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
if (IS_ERR(data->base))
return PTR_ERR(data->base);
@@ -796,9 +794,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
snprintf(name, sizeof(name), "pmu%d", i);
- res = platform_get_resource_byname(pdev,
- IORESOURCE_MEM, name);
- phy->pmu = devm_ioremap_resource(dev, res);
+ phy->pmu = devm_platform_ioremap_resource_byname(pdev,
+ name);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
}
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
index b1c04f71a31d..84055b720016 100644
--- a/drivers/phy/allwinner/phy-sun50i-usb3.c
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -134,7 +134,6 @@ static int sun50i_usb3_phy_probe(struct platform_device *pdev)
struct sun50i_usb3_phy *phy;
struct device *dev = &pdev->dev;
struct phy_provider *phy_provider;
- struct resource *res;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
@@ -153,8 +152,7 @@ static int sun50i_usb3_phy_probe(struct platform_device *pdev)
return PTR_ERR(phy->reset);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->regs = devm_ioremap_resource(dev, res);
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->regs))
return PTR_ERR(phy->regs);
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..f0bc87d654d4 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -253,15 +253,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
struct sun6i_dphy *dphy;
- struct resource *res;
void __iomem *regs;
dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
if (!dphy)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs)) {
dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
return PTR_ERR(regs);
diff --git a/drivers/phy/allwinner/phy-sun9i-usb.c b/drivers/phy/allwinner/phy-sun9i-usb.c
index fc6784dd7fa0..2f9e60c188b8 100644
--- a/drivers/phy/allwinner/phy-sun9i-usb.c
+++ b/drivers/phy/allwinner/phy-sun9i-usb.c
@@ -117,7 +117,6 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- struct resource *res;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
@@ -156,8 +155,7 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
}
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->pmu = devm_ioremap_resource(dev, res);
+ phy->pmu = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
--
2.28.0
From: Yangtao Li <[email protected]>
The A100 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals.
Add a device node for it.
Signed-off-by: Yangtao Li <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index cc321c04f121..c34ed8045363 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,18 @@ ccu: clock@3001000 {
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-a100-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ dma-channels = <8>;
+ dma-requests = <51>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
--
2.28.0
From: Yangtao Li <[email protected]>
For the current code, enable_pmu_unk1 only works in non-a83t and non-h6
types. So let's delete it from the sun50i_h6_cfg.
Signed-off-by: Yangtao Li <[email protected]>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 651d5e2a25ce..0f1888b55dbd 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -969,7 +969,6 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
.phy0_dual_route = true,
.missing_phys = BIT(1) | BIT(2),
};
--
2.28.0
From: Yangtao Li <[email protected]>
The interrupt descriptor cannot be found in the interrupt processing
function, and this situation cannot happen when the system is running
normally. It doesn't seem right to return directly to the status of not
handling gic. In this case, it must be a bug, let's mark it with
BUG_ON.
Signed-off-by: Yangtao Li <[email protected]>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 8e792f8e2dc9..9d8b59dafa4b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -1139,8 +1139,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (irq == pctl->irq[bank])
break;
- if (bank == pctl->desc->irq_banks)
- return;
+ WARN_ON(bank == pctl->desc->irq_banks);
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
--
2.28.0
From: Yangtao Li <[email protected]>
A100's pin starts with PB, so it should start with 1.
Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
Signed-off-by: Yangtao Li <[email protected]>
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index 19cfd1e76ee2..e69f6da40dc0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -677,7 +677,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
};
-static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6};
+static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
.pins = a100_pins,
--
2.28.0
From: Yangtao Li <[email protected]>
Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.
Signed-off-by: Yangtao Li <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index c34ed8045363..01ff53b5a7a8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
enable-method = "psci";
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
};
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
--
2.28.0
From: Yangtao Li <[email protected]>
The dma of a100 is similar to h6, with some minor changes to
support greater addressing capabilities.
Add support for it.
Signed-off-by: Yangtao Li <[email protected]>
---
drivers/dma/sun6i-dma.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index f5f9c86c50bc..5cadd4d2b824 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -1173,6 +1173,30 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
};
+/*
+ * TODO: Add support for more than 4g physical addressing.
+ *
+ * The A100 binding uses the number of dma channels from the
+ * device tree node.
+ */
+static struct sun6i_dma_config sun50i_a100_dma_cfg = {
+ .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
+ .set_burst_length = sun6i_set_burst_length_h3,
+ .set_drq = sun6i_set_drq_h6,
+ .set_mode = sun6i_set_mode_h6,
+ .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+ .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+ .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+ .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+ .has_mbus_clk = true,
+};
+
/*
* The H6 binding uses the number of dma channels from the
* device tree node.
@@ -1225,6 +1249,7 @@ static const struct of_device_id sun6i_dma_match[] = {
{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
{ .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
+ { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg },
{ .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
{ /* sentinel */ }
};
--
2.28.0
It seems that sending too many e-mails at one time will cause some
emails to fail to be sent out. I will try again.
BR / Yangtao
On Tue, 10 Nov 2020 at 07:00, Frank Lee <[email protected]> wrote:
>
> It seems that sending too many e-mails at one time will cause some
> emails to fail to be sent out. I will try again.
Hi,
Instead please reduce the address list to relevant people, as pointed
out by scripts/get_maintainer.pl. Don't Cc irrelevant developers
unless a file is abandoned and you need to get as much audience as
possible... but sunxi is not abandoned.
Best regards,
Krzysztof
On Tue, Nov 10, 2020 at 4:43 PM Krzysztof Kozlowski <[email protected]> wrote:
>
> On Tue, 10 Nov 2020 at 07:00, Frank Lee <[email protected]> wrote:
> >
> > It seems that sending too many e-mails at one time will cause some
> > emails to fail to be sent out. I will try again.
>
> Hi,
>
> Instead please reduce the address list to relevant people, as pointed
> out by scripts/get_maintainer.pl. Don't Cc irrelevant developers
> unless a file is abandoned and you need to get as much audience as
> possible... but sunxi is not abandoned.
Thank you for the reminder. I resend the version in the afternoon,
only CC the relevant people. I'm not sure. Should the cover be copied
to everyone?
Yangtao
On 10-11-20, 16:51, Frank Lee wrote:
> On Tue, Nov 10, 2020 at 4:43 PM Krzysztof Kozlowski <[email protected]> wrote:
> >
> > On Tue, 10 Nov 2020 at 07:00, Frank Lee <[email protected]> wrote:
> > >
> > > It seems that sending too many e-mails at one time will cause some
> > > emails to fail to be sent out. I will try again.
> >
> > Hi,
> >
> > Instead please reduce the address list to relevant people, as pointed
> > out by scripts/get_maintainer.pl. Don't Cc irrelevant developers
> > unless a file is abandoned and you need to get as much audience as
> > possible... but sunxi is not abandoned.
>
> Thank you for the reminder. I resend the version in the afternoon,
> only CC the relevant people. I'm not sure. Should the cover be copied
> to everyone?
Any reason why this should be a single series.. why not split it to
bunch of chunks, one per subsystem like pinctrl, phy, dmaengine, etc...
And then DTS parts and CC relevant list and maintainers. I do not think
there is any dependency, right?
--
~Vinod
On Tue, Nov 10, 2020 at 06:18:29PM +0530, Vinod Koul wrote:
> On 10-11-20, 16:51, Frank Lee wrote:
> > On Tue, Nov 10, 2020 at 4:43 PM Krzysztof Kozlowski <[email protected]> wrote:
> > >
> > > On Tue, 10 Nov 2020 at 07:00, Frank Lee <[email protected]> wrote:
> > > >
> > > > It seems that sending too many e-mails at one time will cause some
> > > > emails to fail to be sent out. I will try again.
> > >
> > > Hi,
> > >
> > > Instead please reduce the address list to relevant people, as pointed
> > > out by scripts/get_maintainer.pl. Don't Cc irrelevant developers
> > > unless a file is abandoned and you need to get as much audience as
> > > possible... but sunxi is not abandoned.
> >
> > Thank you for the reminder. I resend the version in the afternoon,
> > only CC the relevant people. I'm not sure. Should the cover be copied
> > to everyone?
>
> Any reason why this should be a single series.. why not split it to
> bunch of chunks, one per subsystem like pinctrl, phy, dmaengine, etc...
> And then DTS parts and CC relevant list and maintainers. I do not think
> there is any dependency, right?
Yeah, I agree.
One series should be about one topic, so you should have at least:
- One for the pinctrl fixes
- One for the DMA controller and related DT patches
- One for the MMC controller and related DT patches
- One for the USB controllers and related DT patches
* And for the PHY, the enable_pmu_unk1 and devm_* patches should be
sent independently as well
- One for the watchdog
- And the PMU patch should be sent independently too
Maxime